Gigabit Ethernet Research Articles

Ethernet's Impact on PCB Design and Solutions

Ethernet is a technology that connects computers to form a local network through which devices can communicate with other devices. For example, 800 GBE (800 Gigabit Ethernet) is a high-speed network technology in the Ethernet standard that supports 800 Gbit/s (800 gigabit per second) data transfer rate. However, over the years, Ethernet has developed into a worldwide data communication system, with speeds ranging from the original 10 Mbit/s to 800 Gbit/s and even 1.6 Tbit/s today. In this context, the complexity of PCB (printed circuit board) chip test design continues to increase.

REMOTE VEHICLE DIAGNOSTIC SYSTEM DEVELOPMENT BASED ON THE INTERNET OF THINGS TECHNOLOGY

Background. Advanced artificial intelligence and IoT gateways are working together in the automotive industry to predict potential vehicle problems by analysing sensor data and optimizing quality control processes. Manufacturers can detect anomalies, improve product reliability, and eliminate manufacturing defects or malfunctions in advance. Predictive analytics also lead to improved fuel efficiency, performance and overall vehicle reliability. Objective. The purpose of this work is to develop a model for remote diagnosis of vehicle faults using a Raspberry Pi model B microcomputer and a SIM7600G-H GSM module. Configure data modules, install the necessary software and configure it, demonstrate step-by-step actions, and perform diagnostics and testing of this module for data transmission. Methods. A prototype was created on the basis of Raspberry Pi 4. and provides monitoring of machine operation in remote mode using the SIM7600E-H LTE Cat-4 4G/3G module. The design has small dimensions, easy installation, requires only initial adjustment and has a wide range of improvements. Results. This prototype uses a diagnostic OBD-II car scanner ELM327 with Bluetooth connection support, a Raspberry PI 4 model B microcomputer with 8 GB of RAM, 4 USB connectors (2 ports type USB3 and 2 ports type USB2), a Gigabit Ethernet port, a USB-C power supply port, and two micro HDMI 4K display connectors. On top of the module there are 48 pins (contacts) with which you can connect modules of different types and directions. The SIM7600G-H communication module is connected to these pins. The last element of the prototype is the SIM card of one of the telephone service providers and the micro SD card, which will act as the main memory element on which the operating system will be written and data will be stored. Conclusions. The article proposes the development of a device model using Internet of Things technologies, which is capable of providing remote diagnosis of car malfunctions. This model is based on the use of the SIM7600G-H module, which provides data transmission through the mobile network. The developed model allows you to read data from various car sensors, as well as transfer this data to a remote device for further analysis. This makes it possible to quickly detect malfunctions and make timely decisions on their correction.

Multi-Hop GigaBit Ethernet Routing for Gigabit Passive Optical System using Genetic Algorithm

Multi-Hop GigaBit Ethernet Routing for Gigabit Passive Optical System using Genetic Algorithm

Optimal Implementations of 8b/10b Encoders and Decoders for AMD FPGAs

The 8b/10b IBM encoding scheme is used in a plethora of communication technologies, including USB, Gigabit Ethernet, and Serial ATA. We propose two primitive-based structural designs of an 8b/10b encoder and two of an 8b/10b decoder, all targeted at modern AMD FPGA architectures. Our aim is to reduce the amount of resources used for the implementations. We compare our designs with implementations resulting from behavioral models as well as with state-of-the-art solutions from the literature. The implementation results show that our solutions provide the lowest resource utilization with comparable maximum operating frequency and power consumption. The proposed structural designs are suitable for resource-constrained data communication protocol implementations that employ the IBM 8b/10b encoding scheme. This paper is an extended version of our paper published at the 2022 International Symposium on Electronics and Telecommunications (ISETC), Timisoara, Romania, 10–11 November 2022.

Hardware nanosecond‐precision timestamping for line‐rate packet capture

AbstractCybersecurity events occur frequently. When it comes to investigating security threats, it is essential to offer a 100 percent accurate and packet‐level network history, which depends on packet capture with high precision packet timestamping. Many packet capture applications are developed based on data plane development kit (DPDK)—a set of libraries and drivers for fast packet processing. However, DPDK cannot give an accurate timestamp for every packet, and it is unable to truly reflect the order in which packets arrive at the network interface card. In addition, DPDK‐based applications cannot achieve zero packet loss when the packet is small such as 64 B for beyond 10 Gigabit Ethernet. Therefore, the authors proposed a new method based on Field‐Programmable Gate Array (FPGA) to solve this problem. The authors also develop a DPDK driver for FPGA devices to make the design compatible with all DPDK‐based applications. The proposed method performs timestamping at line‐rate for 10 Gigabit Ethernet traffic at 4 ns precision and 1 ns precision for 25 Gigabit, which greatly improves the accuracy of security incident retrospective analysis. Furthermore, the design can capture full‐size packets for any protocol with zero packet loss and can be applied to 40/100 Gigabit systems as well.

Flat ball topology basics multi‐transceivers 100 km/2.5 Tbps gigabit‐ethernet PON architecture for energy efficiency in data centers

AbstractExisting electronic data sources desire high‐power requisites, in order to obtain a large bandwidth, minimum power dissipation and low latency in networks. In this instance, a gigabit ethernet passive optical network (GEPON) architecture based on a dynamic Flat Ball topology incorporating multi‐transceivers to minimize network energy consumption via passive devices along with bandwidth reconfiguration potential and low latency is reported in this paper. The proposed architecture connected with 200 nodes exhibits 26 as well as 40 dB total loss in uplink as well as downlink considerably, compared to Sirius and Sandwich tree. Also, Flat ball GEPON architecture permits 9 and 10 dBm energy saving in downlink as well as uplink, respectively, than conventional GEPON architecture at 1 ms delay. The proposed architecture with 50 Erlang load allows energy ratio of 39% in downlink and 37% in uplink, at 25 × 100 Gbps traffic rate for 55 nodes. Besides this, the faithful fiber range of 100 km considering fiber no‐linearities and impairments can be obtained successfully. The architecture can be bordered with 1:64 splitting ratio with 35 ms in downlink as well as 31 ms in uplink transmission delay at bit error rate of 10−3. Additionally, on comparing the proposed topology with existing architectures depict its superiority with minimal implementation cost, low‐power dissipation, less traffic delay as well as high scalability and high flexibility.

Bi-Directional All-Optical Wireless Gigabit Ethernet Communication System Using Automatic Self-Aligned Beam Steering

Bi-Directional All-Optical Wireless Gigabit Ethernet Communication System Using Automatic Self-Aligned Beam Steering

Analysis of ICONNET Fiber Optic Network Improvement in Cluster Rayon Panam at Strategic Business Unit Central Sumatra PT PLN ICON PLUS

Optical fiber is a telecommunications transmission medium that has a large bandwidth and bit rate so that it can meet the needs of today's data services with great reliability and efficiency. Optical fiber applications continue to be broad and have included seabed networks, terrestrial networks, metropolitan and regional scope networks, and small-scale networks. Optical fiber communication systems have 2 factors that affect the quality of network performance, namely internal aspects and external aspects. These internal and external aspects can degrade the performance quality of the optical fiber used and can cause attenuation and other transmission losses. As an effort to prevent sudden and significant deterioration in the quality of a network, it is necessary to try regular maintenance activities such as scheduled fiber optic cable network service quality measurements. These maintenance activities can help ensure network capacity increase decisions. One of the quality of service parameters that is often measured is transmission attenuation and received signal energy (received power). This research examines increasing the bandwidth capacity of PT PLN ICON PLUS in the Central Sumatra region during a network anomaly, namely a slow internet connection in the Rayon Panam Cluster. The sample taken from one of the customers shows the results of measuring the internet speed of 4-5 Mbps only, while the service taken is 10 Mbps. The results of checking on the up-link side to OLT Rayon Panam found that the data output was close to its capacity, which was 940,919,000 bits/sec or 0.9 Gb/sec. Increasing bandwidth capacity is done by moving the OLT port on the up-link side from the gigabit ethernet port to the tengigabit ethernet port, then replacing the SR type SFP with SFP ER and adding fiber optic attenuators so that the speed test results on the customer side have returned to their original appearance., 10 Mbps.

Development of the Readout Electronics for a MAPS-Based Beam Telescope

Along with the change of the Deutsches Elektronen-Synchrotron (DESY) II test beam facility operation mode, the existing beam telescope built with the Mimosa26 chips will be unable to meet the requirements of the much-increased beam particle rate. In this article, we present the readout electronics of a new beam telescope built with ALice PIxel Detector (ALPIDE) chips which are originally designed for the upgrade of A Large Ion Collider Experiment (ALICE). The gigabit Ethernet implemented in the high-speed transceiver of Kintex field programmable gate array (FPGA) enables individual data acquisition and control of each ALPIDE chip. The data from the multidetector plane are transmitted to the remote platform via an Ethernet switch. The global trigger is generated by an AIDA2020-trigger logic unit (TLU) by the coincidence of two pairs of plastic scintillators. The results of long-term beam tests show that the new beam telescope can achieve a lower fake hit rate and a trigger rate of 220 kHz, which increases beam utilization and reduces the difficulty of track reconstruction. The biased resolution of distribution using all six planes for tracking in a 6 GeV electron beam is measured to be about 5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> .

Demonstration of real-time motion control on a 10G-EPON edge computing platform with SDN enabled broadband access

Edge computing is more useful for real-time remote motion control of Internet of Things devices than cloud computing because of its superior low latency performance. The access system is attracting attention as a place to perform edge computing. By using the network devices of the access system as an edge computing resource, it becomes possible to realize more precise control. This paper is the first, to our knowledge, to demonstrate real-time motion control by implementing edge computing on a 10-gigabit Ethernet passive optical network based on software-defined network enabled broadband access (SEBA), which is a virtualization platform for access systems. The proposed method analyzes the effectiveness of motion control and sets the optimal network settings automatically by using SEBA to take full advantage of edge computing benefits. The proposed method can provide an optimal network for motion control without making the user aware of the network settings. We construct a general motor-based experimental system and verify the effectiveness of the proposed system. The experiment shows that it properly reflects the optimum network settings to SEBA. Also, we verify that the proposed method changed the network settings to satisfy the reference settling time of 3 s. The optimal dynamic bandwidth allocation (DBA) cycle for motion control is determined after five trials, and the settling time was reduced by 53% compared with the case where the DBA cycle was set to 20 ms and no optimization was performed.

Development of a new high-speed data acquisition system prototype for SOI pixel detector using SiTCP-XG, a 10-gigabit Ethernet network processor

We are developing a new readout board with a newer generation field-programmable gate array (FPGA) and the 10-gigabit ethernet to improve the performance and usability of the current readout board based on the 1-gigabit ethernet. In this new readout board, the SiTCP-XG network processor supporting 10 Gigabit Ethernet was implemented. SiTCP is a network processor circuit running on FPGA, and SiTCP-XG is the newly developed version of the SiTCP that supports 10-gigabit ethernet. Before developing the new board, we constructed a prototype system using the Xilinx FPGA evaluation board KC705 to evaluate the SiTCP-XG. This prototype system was tested with the SOI pixel detector, which has 425,984 (column 832 × row 512 matrix) pixels and a pixel size of 17 × 17 μm2 at the synchrotron beamlines of the PhotonFactory (KEK). This was the first test of the X-ray imaging for this system. The results showed that this system worked stably with a transfer rate of 682 Mbps (equivalent to a frame rate of 100 fps, limited by detector operation parameters), and also worked stably with a transfer rate of 2.4 Gbps (equivalent to 350 fps, the maximum rate limited by the detector performance). These results suggest that the SiTCP-XG system has sufficient transfer performance to cover the SOIPIX detector performance.

High resolution filtering and digitization system for cryogenic bolometric detectors

BiDAQ is a custom filtering and data acquisition system designed for next-gen bolometric experiments dedicated to the search of neutrinoless double beta decay. The system is composed of 12-channel analog-to-digital boards interfaced with FPGA SoC modules that collect and transmit the 24-bit data to the storage computers with a sampling rate up to 25 kHz. Low noise, low power, high modularity and configurability, and an easy interface with Gigabit Ethernet are the main characteristics of the BiDAQ system.

Modular DAS demodulation system based on ultra-weak fibre Bragg grating

Aiming at the requirements of low power consumption, miniaturization, and massive data processing, a modular distributed optical fibre acoustic sensing (DAS) demodulation system based on ultra-weak fibre Bragg grating (UW-FBG) is proposed. A highly integrated circuit and embedded system is used for the time-domain positioning and data acquisition of the gratings. Field programmable gate array (FPGA) demodulates the phase changes of each sensing section in real time. The demodulation outputs are uploaded through a Gigabit Ethernet connection. Through innovative software and hardware design, the demodulation system power consumption is less than 20 W, and the device volume is 250 mm× 180 mm× 45 mm, and the output data size is about 2.6% of the conventional methods. All the outputs are then tested on a piezoelectric transducer (PZT) platform. Results show that the background noise within 5 Hz–1280 Hz range is 2.16 pε/√(Hz), and the strain sensitivity reaches 484 pε/√(Hz)@200 Hz. The correlation coefficient of voltage and phase is 0.9991, which shows good linearity. Combined with a common commercial laptop to demodulate the micro-vibration signals, this system could provide a cost-effective scheme for acquiring acoustic-level micro-vibration signals and on-line field monitoring.

Design of a passive optical network test scenario

Passive optical networks with gigabit ethernet speeds aim to bring internet and communications technologies using fiber optics to the end user. A test scenario for passive optical networks with gigabit ethernet speeds has been implemented. In this test scenario, practices are carried out from the installation of a manager for the administration, operation and maintenance of the active equipment, to the configuration of different types of services over this technology. Unicast and multicast traffic transport tests have been carried out. This test scenario of passive optical networks with low-cost gigabit ethernet speeds allowed simulations with different topologies and network configurations to be carried out and then transferred to real metropolitan networks. The design of the test scenario has been used to simulate the implementation of new technologies on this type of networks before they are implemented in the commercial networks of an Internet service provider. This test scenario has also been used for training in the design and implementation of passive optical networks with gigabit ethernet capabilities.

Focus on software, data acquisition, and instrumentation

Focus on software, data acquisition, and instrumentation

Experimental real-time GbE MIMO FSO under fog conditions with software defined GNU Radio platform-based adaptive switching

In this paper, we demonstrate the first, to our knowledge, experimental implementation of a gigabit Ethernet multiple input single output free space optical (FSO) communications link using adaptive switching implemented in the software defined open-source software, GNU Radio, and analyze its performance. A fully functional FSO link with a feedback path is implemented using cost effective off-the-shelf components, i.e., media converters and small form-factor pluggable modules. We propose a switching mechanism at the transmitter to improve the link performance under different fog conditions and provide results for the proposed FSO system compared with a single FSO link. The real-time channel estimation is demonstrated and, based on the channel state information, adaptive switching is carried out in GNU Radio. We show that the proposed system under the heavy fog condition offers almost the same packet error rate under the clear channel but with a reduced data rate by about 100 Mbps (i.e., 600 Mbps).

Understanding I/O Direct Cache Access Performance for End Host Networking

Direct Cache Access (DCA) enables a network interface card (NIC) to load and store data directly on the processor cache, as conventional Direct Memory Access (DMA) is no longer suitable as the bridge between NIC and CPU in the era of 100 Gigabit Ethernet. As numerous I/O devices and cores compete for scarce cache resources, making the most of DCA for networking applications with varied objectives and constraints is a challenge, especially given the increasing complexity of modern cache hardware and I/O stacks. In this paper, we reverse engineer details of one commercial implementation of DCA, Intel's Data Direct I/O (DDIO), to explicate the importance of hardware-level investigation into DCA. Based on the learned knowledge of DCA and network I/O stacks, we (1) develop an analytical framework to predict the effectiveness of DCA (i.e., its hit rate) under certain hardware specifications, system configurations, and application properties; (2) measure penalties of the ineffective use of DCA (i.e., its miss penalty) to characterize its benefits; and (3) show that our reverse engineering, measurement, and model contribute to a deeper understanding of DCA, which in turn helps diagnose, optimize, and design end-host networking.

A precision time of flight readout system for the TORCH prototype detector

The TORCH detector provides low-momentum particle identification, combining Time of Flight (TOF) and Cherenkov techniques to achieve charged particle pi/K/p separation between 2–20 GeV/c over a flight distance of 10 m. The measurement requires a timing resolution of 70 ps for single Cherenkov photons. For precision photon detection, customised Micro-Channel Plate Photomultiplier Tubes (MCP-PMTs) with high precision TOF measurement electronics have been developed. The electronics measures time-over-threshold from the MCP-PMT and features a 10-Gigabit Ethernet readout. This paper reports the design and performance of a 5120-channel system which currently instruments a pair of MCP-PMTs, but has the capacity to read out ten customised MCP-PMT devices in the future.

High-Level Synthesis Implementation of an Embedded Real-Time HEVC Intra Encoder on FPGA for Media Applications

High Efficiency Video Coding (HEVC) is the key enabling technology for numerous modern media applications. Overcoming its computational complexity and customizing its rich features for real-time HEVC encoder implementations, calls for automated design methodologies. This article introduces the first complete High-Level Synthesis (HLS) implementation for HEVC intra encoder on FPGA. The C source code of our open-source Kvazaar HEVC encoder is used as a design entry point for HLS that is applied throughout the whole encoder design process, from data-intensive coding tools like intra prediction and discrete transforms to more control-oriented tools such as context-adaptive binary arithmetic coding (CABAC). Our prototype is run on Nokia AirFrame Cloud Server equipped with 2.4 GHz dual 14-core Intel Xeon processors and two Intel Arria 10 PCIe FPGA accelerator cards with 40 Gigabit Ethernet. This proof-of-concept system is designed for hardware-accelerated HEVC encoding and it achieves real-time 4K coding speed up to 120 fps. The coding performance can be easily scaled up by adding practically any number of network-connected FPGA cards to the system. These results indicate that our HLS proposal not only boosts development time, but also provides previously unseen design scalability with competitive performance over the existing FPGA and ASIC encoder implementations.

Providing quality of service in omni-path networks

New hierarchical crossbar switch architectures, such as Omni-Path (OPA) and Cray X2, have appeared to improve packet latency, reduce overall cost and increase fault tolerance of the high-performance interconnection networks in supercomputing and data center systems. These and other interconnect technologies (Infiniband or 40/100 Gigabit Ethernet) include support to provide quality of service (QoS) to the applications. In this paper, we show how this QoS support can be enabled to achieve bandwidth and/or latency differentiation in Omni-Path interconnection networks, as a representative case of hierarchical switches. To do that, three different table-based schedulers are used. We include the description of these schedulers and a comparative study by using the results obtained when we evaluate them with Hiperion, a simulation tool that implements an OPA model.