Gated-diode Technique Research Articles

Electrical characterization of CeO2∕Si interface properties of metal-oxide-semiconductor field-effect transistors with CeO2 gate dielectric

Metal-oxide-semiconductor field-effect transistors with CeO2 gate dielectrics were fabricated. The lowest interface trap density (Dit) of CeO2∕Si interface in comparison with other high-κ gated diodes is 1.47×1012cm−2eV−1 due to the very low lattice mismatch of CeO2∕Si. The interfacial properties were characterized by gated-diode measurements. The surface recombination velocity (s0) and the minority carrier lifetime in the field-induced depletion region (τ0,FIJ) measured from the gated diodes are about 1.03×104cm∕s and 2.73×10−8s, respectively. The effective capture cross section of surface state (σs) extracted using the gated diode technique and the subthreshold swing measurement is about 8.68×10−15cm2.

Locating hot carrier degradation in asymmetric nDeMOS transistors by gated diode technique

In this paper, hot carrier degradation in asymmetric nDeMOS transistors is investigated. For the first time, we found that the worst hot carrier stress condition is at Ig,max, and not at Ib,max and HE stress conditions. The damage regions in transistors upon various hot carrier stress modes are located by using gated diode technique. It is found that the interface traps generation in the gate/n-type graded drain (NGRD) overlap and spacer oxide regions is the dominant mechanism of hot carrier degradation in asymmetric nDeMOS transistors upon various hot carrier stress modes. Furthermore, the bulk silicon damages locating at the p-well and NGRD regions during hot carrier stress must be taken into account, because they lead to a series of issues, such as the increase in Ioff current, the off-state breakdown voltage decrease, and so on.

An investigation of surface state capture cross-sections for metal–oxide–semiconductor field-effect transistors using HfO 2 gate dielectrics

MOSFETs and MOSCs incorporating HfO 2 gate dielectrics were fabricated. The I DS– V DS, I DS– V GS, gated-diode and C– V characteristics were investigated. The subthreshold swing and the interface trap density were obtained. The surface recombination velocity and the minority carrier lifetime in the field-induced depletion region measured from the gated diodes were about 2.73 × 10 3 cm/s and 1.63 × 10 −6 s, respectively. The effective capture cross section of surface state was determined to be 1.6 × 10 −15 cm 2 using the gated-diode technique in comparison with the subthreshold swing measurement. A comparison with conventional MOSFETs using SiO 2 gate oxide was also made.

Electrical Characterization of $\hbox{ZrO}_{2}/\hbox{Si}$ Interface Properties in MOSFETs With $\hbox{ZrO}_{2}$ Gate Dielectrics

MOSFETs incorporating ZrO2 gate dielectrics were fabricated. The IDS-VDS, IDS-VGS , and gated diode characteristics were analyzed to investigate the ZrO2/Si interface properties. The interface trap density (D it) was determined to be about 7.4times1012 cm -2middoteV-1 using subthreshold swing measurement. The surface-recombination velocity (s0) and the minority carrier lifetime in the field-induced depletion region (tau 0,FIJ) measured from the gated diodes were about 3.5times10 3 cm/s and 2.6times10-6 s, respectively. The effective capture cross section of surface state (sigmas) was determined to be about 5.8times10-16 cm2 using the gated diode technique and the subthreshold swing measurement. A comparison with conventional MOSFETs using SiO2 gate oxides was also made

A revised reverse gated-diode technique for determining generation parameters in thin-film silicon-on-insulator devices and its application at high temperatures

In this paper the reverse gated-diode technique is examined for determining the carrier generation lifetime and surface generation velocities in thin-film silicon-on-insulator (SOI) devices. Using the modeling of the gate-controlled volume and surface generation components, SOI-specific aspects of the technique are highlighted. A reliable approach for extracting generation parameters in thin-film SOI devices from reverse gated-diode measurements is proposed and validated for high temperatures. The technique is demonstrated on the devices fabricated on two different SOI materials (zone-melt recrystallized and Unibond®), as examples of volume- and surface-dominated generation current behaviors. Finally, the technique is applied to characterize Unibond® SOI devices operating in the temperature range 100–300 °C to demonstrate the model and technique applicability at high temperatures.

Determination of film and surface recombination in thin-film SOI devices using gated-diode technique

In this paper, the forward-biased gated-diode technique is proposed as a simple and reliable method for the determination of the recombination parameters in thin-film, fully depleted SOI MOS devices. Using modeling of gated-controlled volume and surface recombination components the behavior of the recombination current in a thin-film SOI gated-diode is analyzed. Measurement conditions simplifying the extraction of the recombination parameters and enabling discrimination between volume and surface contributions are described. The method has been applied to study recombination processes in the devices made on different SOI materials (UNIBOND, SIMOX, ZMR).

Gated-diode characterization of the back-channel interface on irradiated SOI wafers

A silicon-on-insulator (SOI) MOSFET-based technique has been applied to study the Si-film/buried-oxide interface of devices that were fabricated on a SIMOX wafer. Since the gated-diode technique is sensitive to recombination current caused by the presence of interface states, the samples were exposed to 10 keV X-ray irradiation to enhance the development of SOI back-channel interface states. The measured peak in the gated-diode current curve was observed to increase in magnitude and move in voltage as a function of exposure to radiation in a manner consistent with increasing interface states and increasing trapped oxide charge. Using a two-dimensional numerical simulator, with a single acceptor interface trap at 0.7 eV, the gated-diode current was modeled as a function of 10 keV X-ray exposure.

Extraction of the lateral distribution of interface traps in MOSFETs by a novel combined gated-diode technique

A novel combined gated-diode technique for qualitatively extracting the lateral distribution of interface traps in N-MOSFETs is presented in this paper. The key of this technique lies in the recombination–generation current peak originating from the interface trap recombination is being modulated by the drain voltage of the combined forward gated-diode architecture. The extraction principle is introduced in detail and the extraction procedure is also erected. The experimental results qualitatively show that the induced interface traps gradually decrease from the drain and source edges to the channel region while showing the highest value near both edges in N-MOSFETs.

A novel experimental technique: combined gated-diode method for extracting lateral distribution of interface traps in SOI NMOSFETs

A novel method namely combined gated-diode technique for extracting lateral spatial distribution of interface traps induced by the electrically stressing is presented in this paper. This technique is based on the measurement of recombination–generation current characteristics via the modulation of the drain bias voltage of the forward gated-diode. The extracted results on the interface trap profile demonstrate that the induced interface trap density gradually decreases from the drain edge to channel region and shows the highest value near the drain edge.