Gate Tunneling Leakage Research Articles

A self-control leakage-suppression block for low-power high-efficient static logic circuit design in 22 nm CMOS process

To maintain performance increase and reliability, power supply and threshold voltages will have to continually scale, in CMOS technology. With threshold voltage scaling and thinner gate-oxide thickness, sub-threshold and gate tunneling leakage powers are expected to become a significant portion of the total power in CMOS VLSI systems. A self-control leakage-suppression block (SCLSB) for leakage power reduction of static CMOS gates is proposed in this paper. The proposed SCLSB consists of two PMOS and two NMOS transistors that are located between pull-down network (PDN) and pull-up network (PUN). In any combination of input signals, one PMOS and one NMOS transistor of SCLSB turn on and the rest turn off, hence the resistance between the power supply voltage rail to the ground rail increased and leakage currents greatly reduced. The basic static CMOS gates such as inverter, NAND, NOR, and XOR circuits are designed based on SCLSB and their performance is evaluated using SPICE simulations in 22 nm CMOS BSIM4 process. Evaluation outcomes with VDD = 0.9 V depict that power-delay product (PDP) is diminished by 9%, 12.8%, 6%, and 15.25% for inverter, NAND, NOR, and XOR compared to the best counterpart (LECTOR) and by 9%, 35%, 21.5% and 33.8% compared to the conventional CMOS gates. The mentioned features of the proposed static-CMOS circuits are achieved while sustaining the full-swing behavior. To ensure the stability and robustness of the circuits in the presence of the process, voltage, and temperature (PVT) variations, Monte Carlo analysis is also performed.

Modeling and Characterization of Inconsistent Behavior of Gate Leakage Current with Threshold Voltage for Nano MOSFETs

A strange relationship of gate leakage current and threshold voltage variation for nano MOSFETs is analyzed using factual strategy and subsequently a physical model is proffered. The gate leakage current increments with the threshold voltage before it diminishes at higher threshold voltage in nanoscale devices. This inconsistent behavior of gate leakage current with threshold voltage variations is precisely clarified in the manuscript through the concept of accord between two contrary operations: threshold voltage roll-off impact and gate leakage current reliance on surface potential. The tunneling gate leakage current density diminishes with threshold voltage over surface potential. However, the threshold voltage roll-off impact causes higher threshold voltage for larger channel length devices. The net gate leakage current is adjusted by these two contrary functions of threshold voltage. In addition, the rate of accretion of the gate leakage current with threshold voltage variation is also analyzed. The impact of the increase in the power supply voltage on the rate of accretion of the gate leakage current vs. threshold voltage curve is also explored. Thorough methodical TCAD simulations are accomplished to validate the proffered models. Both the experimental outcomes, TCAD simulations and physics based models are implemented to uncover and clarify the threshold voltage gate leakage relationship, particularly for nano MOSFETs. The proposed notion is not currently captured in conventional gate leakage nano device models, hence the proffered physical models may be utilized in progression of reliable and trustworthy TCAD simulation tools for nano devices.

Variability aware transistor stack based regression surrogate models for accurate and efficient statistical leakage estimation

In this paper, we present highly accurate and very efficient stack based surrogate models for standby (idle-time) statistical leakage estimation of CMOS circuits using sampling based methods. Our aim is to replace SPICE simulation with our proposed surrogate models, which can be used to evaluate samples generated by sampling methods in variation space. Our methodology initiates by first characterizing the leakage of basic transistor stacks and then provides estimate of the leakage of basic gates based on these stacks. Transistor stacks are extracted across various standard cells, which are used to estimate leakage of CMOS gates with different input vector combinations. We develop Support Vector Machine (SVM) regression surrogate models and characterize the transistor stacks of CMOS gates, while accounting the combined effect of process variations in transistor length (L), threshold voltage (Vth), oxide thickness (Tox), supply voltage (0.6V−1.2V), temperature (0°C−100°C) and width (28nm−200nm), all scalable at the same time. For gates containing parallel transistor stacks, we merge the parallel transistors having identical inputs, which in turn allows us to use precharacterized basic stacks for leakage calculation, thus avoiding generation of new models. Our experiments illustrate that we only require 30 and 26 stack models to predict the subthreshold and gate tunneling leakage of 20 different gates across 176 input combinations, instead of characterizing leakage model for each input vector separately. SVM regression models generated in our approach have the ability to predict the leakage with maximum average error of 2.7% in mean (μ) and maximum average error of 3.1% in standard deviation (σ), both for OAI22 gate. Our results establish that there is on an average 10× improvement in runtime while estimating the μ and σ of leakage of a gate within 10000 Monte Carlo simulation loop. Our approaches also result into a maximum of 221× runtime improvement for C6288 ISCAS'85 benchmark circuit. We further develop Sparse SVM models using Support Vector spectrum pruning method, which reduces the runtime of the regression models with negligible increase in the error. Runtime efficiency of 17× and 323× is achieved on standard cell library and C6288 benchmark circuit respectively using Sparse SVM models. Our models outperform previous models based on analytical equations and Artificial Neural Network in terms of accuracy.

(Invited) Past, Present, and Future of High-k/Metal Gate Technologies

The SiO2 based gate insulator and poly Si gate electrode had been used almost 4o years for (C)MOS integrated circuits from 1970 to 2010 because of their extraordinary good properties of both the interfaces at the substrate and gate electrode. Thus, most of the people had not believed the replacement of SiO2/poly Si gate stack by that of high-k/metal in the products would be impossible, although the demand to introduce the high-k gate oxide became stronger due to the high tunneling gate leakage current when decreasing the gate oxide thickness with the scaling. However, the operation of high k/metal gate stack MOSFETs were demonstrated by several different organizations at the same time at IEDM 1999. Since then, many R & D organizations seriously participated to the research and development of high-k/metal gate stack for MOSFETs. It was in 2001, when Prof. Samares Kar proposed to create an ECS symposium on “Physics and Technology of High-k Gate Dielectrics”. Then, the 1st symposium was held in Salt Lake City, Utah, U.S.A. on October 20-14, 2002. At that time total number of the presentations at the symposium was 34. The, number increased to 56 in the 2nd symposium in Cancun, Mexico, 2003, and 75, in the 3rd symposium in Los Angeles, in 2006, and so on. In 2007, Intel introduces HfO2 based high-kmaterial for the 1st time into their product. Later, the symposium was renamed with Semiconductors, dielectrics and metals for Nanoelectronics and still continues and contributed to give opportunities to the researchers and engineers for the paper presentation and discussion. Prof. Samares Kar has been the leading organizer of the symposium, maintaining rigorous standards to make the symposium one of the most successful in ECS. However, it was very sad that Prof. Samares Kar passed away on January 13, 2017 at his home in Kolkata, India. We would like to express our sincere appreciation for the hard work and rigorous drive towards the advancement of the symposium by giving presentations for the past, present and future of high-k stack technologies.

Performance Analysis of InAs/AlSb MOS-HEMT by Self-Consistent Capacitance-Voltage Characterization and Direct Tunneling Gate Leakage Current

In this paper, Capacitance-Voltage (CV) characteristics and direct tunneling gate leakage performance of InAs/AlSb Metal Oxide Semiconductor High Electron Mobility Transistor (MOS-HEMT) are investigated. 1-D coupled Schrӧdinger-Poisson equations are solved for electrostatic characterization of InAs/AlSb MOS-HEMT considering wave function penetration and strain effects. Using modified Wentzel–Kramers–Brillouin (WKB) method for transmission probability, direct tunneling gate leakage current is also calculated for the MOS-HEMT structure. Dependence of CV characteristics and direct tunneling gate leakage current on some important process and physical parameters such as oxide thickness, channel thickness, capping layer composition, gate dielectric material, doping concentration of delta layer and temperature are studied in this work. Our simulation results agree the pattern of variation with the experimental results reported by H. K. Lin et al.

Performance Analysis of InAs/AlSb MOS-HEMT by Self-Consistent Capacitance-Voltage Characterization and Direct Tunneling Gate Leakage Current

Recently, III-V materials have attracted great interest among researchers in exploring the substitution of the Si channel in scaled logic field-effect transistors [1]. To enhance mobility and speed, High Electron Mobility Transistors (HEMTs) are being experimented with III-V materials. As a result, different material systems for HEMTs are appearing. InAs/AlSb HEMTs have appeared as a promising device as it has electron mobility as high as 30000 cm2/Vs, fT and fMAX exceeding 230 GHz [2]. However, technological limitations are the low breakdown voltage associated with the narrow bandgap of the InAs channel and additional gate leakage current due to staggered band alignment at the InAs/AlSb heterojunction. Recently high breakdown field of 5MV/cm and reduced gate leakage current of e-beam evaporated Al2O3on top of conventional InAs/AlSb HEMT structure has been reported experimentally by H. K. Lin et al [3]. But a complete self-consistent study and gate leakage current analysis of this device are yet to be done. In this work, we have performed a complete study of Capacitance-Voltage (CV) characteristics and Direct Tunneling (DT) gate leakage current using self-consistent Schrӧdinger-Poisson method in InAs/AlSb Metal-Oxide-Semiconductor HEMT (MOS-HEMT) by varying different process parameters as well as physical parameters like oxide thickness, channel thickness, capping layer composition, dielectric variation, delta doping concentration and temperature. We have investigated CV characteristics and DT gate leakage performance of the structure shown in figure 1 [3] by self-consistent simulation of 1-D coupled Schrӧdinger and Poisson equation [4]. We have used finite difference method for solving Poisson equation [5] and hamiltonian matrix formalism [6] for solving Schrӧdinger equation numerically. Strain effect is also incorporated in this simulator [7]. DT gate leakage current is obtained using the method where transmission probability is calculated using modified Wentzel–Kramers–Brillouin (WKB) method [8]. In our work, we have calculated transmission probability using transmission line analogy [9]. The conduction band diagram and carrier profile of the device obtained from the simulation are illustrated in figure 2. Figure 3 shows the CV characteristics for different channel thicknesses. There are two cross-over points in the curve which can be justified by the change of slope of sheet carried density with respect to the gate voltage. The gate leakage current decreases with channel thicknesses and this variation is shown in figure 4. This behavior can be explained by the upshift of eigen energies in the well as channel thickness is decreased which further causes reduction of transmission probability. CV characteristics are not affected by the change in dielectric material having same Equivalent Oxide Thickness (EOT) as shown in figure 5. However, gate leakage current is significantly reduced with the replacement of high-k HfO2 in place of Al2O3shown in figure 6. This can be justified by the fact that channel sheet carrier density remains same with the variation whereas gate leakage reduces due the reduction in transmission probability with the replacement of high-k dielectric. We have investigated CV characteristics and DT gate leakage current with self-consistent method for InAs/AlSb MOS-HEMT. We have observed that gate leakage current can be significantly reduced by using high-k dielectrics or thick channel layer. Our simulation work provides consistent trends of variations with the experiments [3] and shows how the performance of InAs/AlSb MOS-HEMT can be improved by varying appropriate physical/process parameters.

Impact of gate leakage considerations in tunnel field effect transistor design

In this paper, we have presented the impact of the gate leakage through thin gate dielectrics (SiO2 and high-κ gate dielectric) on the subthreshold characteristics of the tunnel field effect transistors (TFET) for a low operating voltage of 0.5 V. Using calibrated two-dimensional simulations it is shown that even for such a low operating voltage, the gate leakage substantially degrades several subthreshold parameters of the TFET such as the off-state current, minimum subthreshold swing and average subthreshold swing. While the drain-offset as well as the short-gate are effective methods for reducing the gate leakage, we show that if the gate tunneling leakage is not considered, even for these two methods, the overall TFET off-state current will be significantly underestimated. Our results demonstrate the need to carefully account for the gate leakage in the design of TFETs just as it is done for the conventional nanoscale MOSFETs.

Automatic parameter extraction technique for gate leakage current modeling in double gate MOSFET

Direct Tunneling (DT) and Trap Assisted Tunneling (TAT) gate leakage current parameters have been extracted and verified considering automatic parameter extraction approach. The industry standard package IC-CAP is used to extract our leakage current model parameters. The model is coded in Verilog-A and the comparison between the model and measured data allows to obtain the model parameter values and parameters correlations/relations. The model and parameter extraction techniques have been used to study the impact of parameters in the gate leakage current based on the extracted parameter values. It is shown that the gate leakage current depends on the interfacial barrier height more strongly than the barrier height of the dielectric layer. There is almost the same scenario with respect to the carrier effective masses into the interfacial layer and the dielectric layer. The comparison between the simulated results and available measured gate leakage current transistor characteristics of Trigate MOSFETs shows good agreement.

Temperature dependent compact modeling of gate tunneling leakage current in double gate MOSFETs

The temperature dependence of the gate leakage current has been developed for Double Gate (DG) MOSFETs. This model is compared with experimental data measured in Trigate MOSFETs at various temperatures with SiON as a dielectric material and SiO2 as an interfacial layer. The gate leakage current measurements at different temperatures show two different transport mechanisms, direct tunneling (DT) gate leakage and Trap-Assisted-Tunneling (TAT) current. Our analysis based on leakage current measurements in the above threshold regime for different temperatures shows that the DT current is clearly dominant over the TAT, while the opposite happens below threshold. Our model is able to explain the gate tunneling current in terms of gate voltage for different temperatures. The results of the DT current in the strong inversion regime and TAT in the subthreshold regime show good agreement with temperature dependent measurements.

Gate leakage current partitioning in nanoscale double gate MOSFETs, using compact analytical model

This paper presents a compact gate leakage current partitioning model for nanoscale Double Gate (DG) MOSFETs, using analytical models of the direct tunneling gate leakage current. Gate leakage current becomes important and an essential aspect of MOSFET modeling as the gate oxide thickness is scaled down to 1nm and below in advanced CMOS processes. We considered an ideal interface (ideal case without an interfacial layer) and two layers high k dielectric materials as gate insulators. In the case of two layers, a thin layer of SiO2 as an interfacial layer is considered. The results of the gate current partitioning components into drain and source show good agreement with 2D TCAD numerical device simulation (Silvaco Atlas).

Evidence for a Very Small Tunneling Effective Mass (0.03 $m_{0}$) in MOSFET High-$k$ (HfSiON) Gate Dielectrics

We have recently conducted experimental and modeling tasks on TaC/HfSiON/SiON n-type MOSFETs, leading to an effective mass of 0.03m0 for 2-D electrons tunneling in high-k HfSiON dielectrics. In this letter, we present extra evidence obtained from complementary MOSFETs undergoing the same TaC/HfSiON/SiON processing, which shows that such a very small tunneling effective mass is existent not only for 3-D electrons but also for 2-D holes. This new finding is very important because it can substantially enhance the current understanding of gate tunneling leakage suppression in metal-gate high-k MOSFETs.

Design and analysis of 45 nm low power 32 kb embedded static random access memory (SRAM) cell

In sub-100 nm generation, gate-tunneling leakage current increases and dominates the total standby leakage current of LSIs based on decreasing gate-oxide thickness. Showing that the gate leakage current is effectively reduced by lowering the gate voltage, we propose a local DC level control (LDLC) for static random access memory (SRAM) cell arrays and an automatic gate leakage suppression driver (AGLSD) for peripheral circuits. We designed and analyzed a 32 kb 1-port SRAM using 45 nm CMOS technology. The six-transistor SRAM cell size is 1.25 µm2. Evaluation shows that the standby current of 32 kb SRAM is 1.2 µA at 1.2 V and room temperature. It was reduced to 7.5% of the conventional SRAM. Key words: Embedded static random access memory (SRAM), gate leakage, low power, standby current, random access memory (RAM).

Minimal Leakage Pattern Generator

This paper proposes a new input pattern generator for minimal leakage power in the nanometer CMOS technology considering all the leakage current components (sub-threshold leakage, gate tunneling leakage, band-to-band tunneling leakage). Using the accurate macro-model, a heuristic algorithm is developed to generate a input pattern for the minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The simulation result shows that our methods accuracy is within a 5% difference of the Hspice simulation results. In addition, the simulation time of our method is far faster than that of the Hspice simulation.

MODELING GATE CURRENT FOR NANO SCALE MOSFET WITH DIFFERENT GATE SPACER

Dimensions of metal–oxide–semiconductor field effect transistor (MOSFET) have been scaled down for decades to maintain the performance. So, as a result of aggressive scaling, gate oxide thickness approaches its manufacturing and physically limiting value of less than 2 nm in nano regime. Under such circumstances, gate leakage (tunneling) current has become a critical problem in nano domain as compared to subthreshold leakage current. Consequently, accurate quantitative understanding of gate tunneling leakage current is very important especially in context of low power VLSI application. In this work, gate tunneling currents have been modeled including the inevitable nano scale effects for a MOSFET having different high-k dielectric spacer such as SiO2 , Si3N4 , Al2O3 , HfO2 . The gate current model is compared and contrasted with santaurus simulation results and reported experimental result to verify the accuracy of the model. The agreement found was good, thus validating the developed analytical model. It is observed that neglecting nano scale effects may lead to large error in the calculated gate current. It is found in the results that gate leakage current decreases with the increase of dielectric constant of the gate spacer. Further, it is also reported that the spacer materials impact the threshold voltage, on current, off current, drain induced barrier lowering, and subthreshold slope of the device.

Study of potential high-k dielectric for UTB SOI MOSFETs using analytical modeling of the gate tunneling leakage

In this paper, we use analytical models of the direct tunneling gate leakage current to determine the high-k dielectric suitable for the nanoscale ultra-thin body SOI MOSFET structure with the predicted equivalent oxide thickness (EOT) and the maximum value of gate leakage current according to the requirements of the latest ITRS roadmap for three technological nodes. The most important criteria for selecting alternative dielectrics (maximum gate leakage current, EOT, electron effective mass, dielectric constant k-value, barrier height and SiO2 thickness as an interfacial layer) were taken into account to determine the suitability of the gate oxide materials. In the ideal case without an interfacial layer, HfO2 and Lu2O3 were found to be the best gate oxide materials for the 17, 15 and 14 nm technological node requirements.

Gate Leakage Impact on Full Open Defects in Interconnect Lines

An Interconnect full open defect breaks the connection between the driver and the gate terminals of downstream transistors, generating a floating line. The behavior of floating lines is known to depend on several factors, namely parasitic capacitances to neighboring structures, transistor capacitances of downstream gate(s) and trapped charges. For nanometer CMOS technologies, the reduction of oxide thickness leads to a significant increase in gate tunneling leakage. This new phenomenon influences the behavior of circuits with interconnect full open defects. Floating lines can no longer be considered electrically isolated and are subjected to transient evolutions, reaching a steady state determined by the technology, downstream interconnect and gate(s) topology. The occurrence of such defects and the impact of gate tunneling leakage are expected to increase in the future. In this work, interconnect full open defects affecting nanometer CMOS technologies are analyzed and the defective logic response of downstream gates after reaching the steady state is predicted. Experimental evidence of this behavior is presented for circuits belonging to a 180 nm and a 65 nm CMOS technologies. Technology trends show that the impact of gate leakage currents is expected to increase in future technologies.

Impact of Twofold Coordinated Nitrogen on the Generation of Deep-Level Hole Traps under Negative-Bias Temperature Stressing

In this paper, we discuss the generation of deep-level hole traps (DLHTs) during negative-bias temperature stressing. Because of their ability to trap positive charges for a long time, it is imperative to gain a sound understanding on the nature of the DLHT, especially in relation to nitrogen, which has been incorporated in increasing dose into the SiO2 gate oxide to solve boron penetration and gate tunneling leakage issues. Experimental evidence showing a correlation between the generation of DLHTs and nitrogen is first presented. This is followed by a discussion on the role nitrogen plays in influencing the generation of DLHT via first-principles simulation. We focus on the impact of a neighboring nitrogen atom on the structural and electronic properties of the oxygen-vacancy defect (VO), which is a major precursor for hole traps in the SiO2. Finally the charge transition levels (CTL) are discussed, which give us a more comprehensive understanding of DLHT.

Modeling and Simulation of High-κ Gate GaSb Nanowire Field Effect Transistor for Ultra High Speed and Low Power Applications

In this work, we have presented a numerical model for calculating drain current, gate capacitance, gate leakage current and several other important metrics of GaSb nanowire field effect transistor (NWFET). A 2-D simulator is used to calculate gate capacitance, surface potential, charge profile and direct tunneling gate leakage current under different gate biases. Drain current is simulated using a 3-D simulator based on mode-space approach. Dependence of drain current on several device parameters like film thickness, gate length and source/drain Fermi level is also investigated. Gate delay, power-delay and energy-delay products are calculated to show these devices' applicability in ultra high speed and low power applications. To investigate the effects of using ternary alloys of GaSb and InSb, the same metrics are also calculated for GaxIn1-xSb NWFET.

Physics-Based Compact Model for III–V Digital Logic FETs Including Gate Tunneling Leakage and Parasitic Capacitance

A physics-based compact model is developed for III-V field-effect transistors for digital logic applications. Quasi-ballistic ratios, trapezoidal quantum-well subband energy levels, and 2-D source/drain influence on both electrostatics and capacitance are considered. Furthermore, gate tunneling leakage current and parasitic capacitance models are included. These latter effects are important in future technology logic applications, particularly in circuits such as high-density cache arrays. In this paper, we describe the III-V compact model including the gate leakage current and parasitic capacitance analytical models. The efficacy of the compact model in a practical circuit environment is demonstrated using transient simulations of a 6T-static random access memory cell. In addition, we provide design guidelines for optimization of the intrinsic and the extrinsic structure with regard to the parasitic effects.

Analytical modeling of direct tunneling current through gate stacks for the determination of suitable high-k dielectrics for nanoscale double-gate MOSFETs

Gate-leakage current reduction is the key motivation for the replacement of traditional SiO2 gate insulator with alternative gate dielectrics. In this work, a guideline for the determination of the suitable high-k candidate was reported in the case of a SiO2/high-k gate stack in a nanoscale double-gate (DG) MOSFET. Analytical models of direct tunneling gate leakage current with SiO2 as an interfacial layer have been considered. Using these models, the most promising high-k materials for different conditions were predicted, considering the effects of equivalent oxide thickness (EOT), gate leakage current, electron effective mass, dielectric constant-k value, barrier height and interfacial oxide thickness.