Gate Stress Research Articles

Electrical and Bias Temperature Instability Characteristics of n-Type Field-Effect Transistors Using HfOxNy Gate Dielectrics

The dielectric properties and n-type metal oxide semiconductor field-effect transistor (nMOSFET) positive bias temperature instability (PBTI) characteristics of in situ nitrogen-incorporated plasma-enhanced atomic layer deposited gate dielectrics were compared with those of the films. Although the physical thickness of the and films were almost identical , the capacitance equivalent oxide thickness of (1.43 nm) was much lower than that of (2.28 nm), suggesting that has a larger dielectric constant. However, showed a higher leakage current than due to a decrease in bandgap. showed a turnaround effect under a positive gate stress bias in nMOSFET. The threshold voltage shifted to the positive direction during the first second due to the trapping of electrons at pre-existing trap sites in Hf-based gate dielectrics. Subsequently, the shifted in the negative direction due to hole trapping, which originated from the generation of electron–hole pairs related to the surface plasmon. showed a higher initial interface trap density but a lower interface trap generation rate during n-type MOS PBTI stress than .

Voltage stress effect on class AB power amplifier and mixed-signal sample-hold circuit

Abstract The effects of gate and drain voltage stress and breakdown location on the class AB power amplifier and mixed-signal sample-hold circuit have been studied. The soft breakdown has minor effect on the performance of the power amplifier and sample-hold circuit, while the hard breakdown at the drain side reduces the power efficiency of the class AB power amplifier and degrades the signal to noise ratio of the sample-hold circuit significantly. Also, hot electron effect reduces the linearity of the class AB power amplifier.

The Bias Temperature Instability Characteristics of In Situ Nitrogen Incorporated ZrO[sub x]N[sub y] Gate Dielectrics

The dielectric properties and bias temperature instability characteristics of in situ nitrogen incorporated ZrO x N y gate dielectrics were compared with those of ZrO 2 , HfO 2 , and HfO x N y . ZrO x N y showed a much smaller capacitance equivalent oxide thickness (1.43 nm) than ZrO 2 (2.13 nm) and exhibited a turn-around effect under a positive gate stress bias in n-type metal oxide semiconductor field-effect transistor, which is consistent with HfO x N y . However, compared to HfO x N y , ZrO x N y showed a significantly lower initial V th shift under a positive gate stress bias due to the lower number of shallow bulk traps related to oxygen vacancies.

Contribution of Latent Defects Induced by High-Energy Heavy Ion Irradiation on the Gate Oxide Breakdown

From annealing and electrical stress experiments performed on irradiated MOS devices, swift energetic ions-induced morphological oxide defects are shown to act as a contributing part of the oxide breakdown occurring during post gate stress, without being possibly electrically detected before the onset of breakdown itself. A reduction of the charge to breakdown and an increase of the radiation-induced leakage current were first observed after irradiation. Then, leakage current has been shown to be fully removable using isochronal annealing while charge to breakdown was not increased back to its initial value.

Current collapse transient behavior and its mechanism in submicron-gate AlGaN∕GaN heterostructure transistors

The current collapse transient behavior of a practical submicron AlGaN∕GaN heterostructure field effect transistor (HFET) is investigated, and its mechanism is proposed. First, the steady-state and transient characteristics of the Schottky diode obtained by connecting the source and drain electrodes of the transistor have been investigated. The steady-state characteristics can be explained by the thin surface barrier model, indicating the presence of tunneling injection of electrons. Turn-on and turn-off transient characteristics of the reverse current of Schottky diode showed very slow nonexponential transients covering six orders of magnitude of time scale from milliseconds to thousands of seconds. They are very similar to those of a large planar Schottky diode studied recently by the authors. The HFET device showed a clear current collapse behavior after a gate stress beyond pinch off. Pulsed gate stress visualized drain current transients which again included very slow nonexponential transients covering six orders of magnitude of time scale. The whole experimental results are explained consistently by a model in which the current collapse is due to surface state charging near the source side and drain side of the gate edge where its rate limiting process is not the usual Shockley–Read–Hall capture-emission process but the dispersive electron transport through the surface states by time-continual hopping, which is triggered by the tunneling injection process at the gate edge.

Trapping characteristics of Al2O3/HfO2/SiO2 stack structure prepared by low temperature in situ oxidation in dc sputtering

In this work, a dielectric stack with Al2O3/HfO2/SiO2 (1.8 nm/1.6 nm/2.5 nm) trilayer structure prepared by low temperature in situ natural oxidation during dc sputtering is investigated. We study the electrical characteristics, including the dielectric leakage of 10−8 A/cm2 at Vg=−2 V, the current transport mechanism and trap distributions through the trilayer dielectric stack. The Fowler–Nordheim barrier height of the prepared Al2O3 (ϕFN,Al2O3) was extracted as 3.06±0.15 eV. The current variation ratios [ΔJg/Jg(0)] during constant voltage stressing were found to decrease with raising gate stress voltages for the trilayer stack in comparison with that [ΔJg/Jg(0)] increase with raising gate stress voltages for the two-layer HfO2/SiO2 stack. Shallow traps located in HfO2 were supposed to be major trapping centers within the trilayer stack. The proposed method of in situ oxidation during dc sputtering is of merit and low in process temperature. The trilayer dielectric stacks are an alternative option for nonvolatile memory application, especially under the consideration of low temperature limitation.

Experimental and Theoretical Analysis of Degradation in Ga2O3–In2O3–ZnO Thin-Film Transistors

Degradation of Ga2O3–In2O3–ZnO (GIZO) thin-film transistors (TFTs), which are promising for driving circuits of next-generation displays, was studied. We evaluated degradation caused by applying gate voltage and drain voltage stress. A parallel shift of the transfer curve was observed under gate voltage stress. The amount of threshold voltage shift when applying gate and drain voltage stress was smaller than that in the case of only gate voltage stress. Joule heating caused by the drain current was observed. We reproduced this degradation of transfer curve change by device simulation. When we assumed the trap level as the density of state (DOS) model and increased two kinds of trap density, we obtained properties that show the same trends as the experimental results. We concluded that two degradation mechanisms occur under gate and drain voltage stress conditions.

Hot-Carrier and Fowler–Nordheim (FN) Tunneling Stresses on RF Reliability of 40-nm PMOSFETs With and Without SiGe Source/Drain

In this brief, RF reliabilities of hot-carrier and Fowler-Nordheim (FN) tunneling stresses on 40-nm PMOSFETs with and without SiGe source/drain (S/D) are studied and compared in detail. The results show that even the strained device with SiGe S/D has a better RF performance; however, its RF reliabilities after both hot-carrier and FN tunneling stresses are deteriorated remarkably by strain-induced defects. In addition, because the SiGe S/D strain-induced defects are mostly located at the surface of the extension of S/D, but not at the channel, the degradation difference between the strained and nonstrained PMOSFETs becomes less as the stress changes from the hot carrier (gate stress voltage Vgstr = drain stress voltaged V dstr)to the vertical-only, i.e., the FN tunneling stress(V dstr = 0 but with some Vgstr).

Degradation under high-field stress and gate stress of AlGaN/GaN HEMTs

After subjecting to different high-field stress and gate stress，a recoverable degradation has been found，consisting of the decrease of saturation drain current IDsat and maximal transconductance gm，and the positive shift of threshold voltage VTH. AlGaN/GaN HEMTs were degradated more with the high-field strss voltage and the stress time increasing. Relatively，under gate pulse stress and on-state gate stress，the degradation was more obvious than under off-state gate stress. By analyzing the shift of primary parameters，we found that the hot carriers generated by impact ionization and trapped by traps in AlGaN barrier layer，and the emission of electrons from gate electrode filling in surface states at high gate-to-drian electric fileds, were the primary reasons causing device degradation after different stress. Off-state stress，on-state stress and pulse-state stress measurements reveal that the passivation treatment just changes short-time current collapse into long-time degradation，which dose not solve the reliability problem of AlGaN/GaN.

Electrical and thermal stress analysis of In2O3-Ga2O3-ZnO thin-film transistors

AbstractDegradation of In2O3-Ga2O3-ZnO (IGZO) thin-film transistors (TFTs)) was studied. We evaluated degradation caused by applying gate voltage and drain voltage stress. A parallel shift of the transfer curve was observed under gate voltage stress. Joule heating caused by the drain current was observed. We tried to reproduce this degradation of the transfer curve change by device simulation. When we assumed the trap level as the density of state (DOS) model and increased two kinds of trap density, we obtained properties that show the same trends as the experimental results. We concluded that two degradation mechanisms occur under gate and drain voltage stress conditions. And then, we tried to improve the TFT characteristics using high pressure water vapor (HPV) annealing. We also found that the cooling conditions after HPV annealing affect the IGZO TFT characteristics.

Study of Latent Damage in Power MOSFETs Caused by Heavy Ion Irradiation

The latent damages were investigated for power MOSFETs irradiated by high LET heavy ions. It was demonstrated that the post irradiation leakage current in damaged gate oxide was determined by the initial gate stress after the irradiation and the damage was stable even after a million of gate stress repetition.

Instability Behavior of Oxide-based Top-gate TFTs under Electrical and Optical Stress Test

We report instability behavior of oxide-based top-gate thin-film transistors under electrical and optical stresses. For electrical stress, transfer curve shifts to the right and left for positive and negative gate stress voltages, respectively, while sub-threshold slope (SS) barely changed for both cases. Although this behavior is consistent with the previously reported oxide-based TFT instability behavior explained by charge trapping mechanism, threshold voltage shift seemed to have power-law-time dependency unlike the previous results. We also tested optical stress behavior of the oxide-based TFTs with a blue power-LED. Under prolonged exposure of 3.5mW/cm2 blue light, both transfer curves under dark and illumination conditions shift to the left, but with significant change in sub-threshold slope for illumination condition. After the electrical and optical stress tests, stress effect was relaxed without any annealing process.

Polarity Change of Threshold Voltage Shifts for n-channel Polycrystalline Silicon Thin-Film Transistors Stressed by Negative Gate Bias

The negative bias instability on p-channel and n-channel polycrystalline silicon thin-film transistor is investigated. Negative threshold voltage shift is observed in p-channel TFTs and is attributed to the positively charged donor type interface traps. On the other hand, polarity change of threshold voltage shift is observed in n-channel TFTs, suggesting two competing mechanisms. Negatively charged acceptor type interface traps are the dominant factor for the positive threshold voltage shift. As the gate stress voltage increases, accumulated holes are trapped in the insulator via Fowler-Nordheim tunneling and are responsible for the negative threshold voltage shift. The stress-induced hump effect is attributed to higher electric filed at the edge transistors as compared to channel transistor along the channel width direction.

Temperature and Time Dependent Threshold Voltage Instability in 4H-SiC Power DMOSFET Devices

Threshold voltage (Vth) was measured on 4H-SiC power DMOSFET devices as a function of temperature, gate stress, and gate stress time. Vth varied linearly with gate stress and gate stress time and inversely with temperature. This instability is explained with the trapping rate of channel electrons at or near the SiO2-SiC interface. Since the measurement scale of Vth is large in this case (it takes approx. 20 s to measure Vth), it is assumed that fast interface traps, i.e., ones closer to the interface, are already filled and do not contribute to the shift in Vth. Comparison with theoretical calculations shows the rate of carrier detrapping becomes higher with temperature and as a result the measured value of Vth approaches the theoretical value.

Quasi-Static Capacitance-Voltage Characterizations of Mobile Ion Accumulation and Depletion Phenomena in Organic Thin-Film Transistors

By conducting C-V profile measurement, we analyzed the charge transport behavior in polycrystalline pentacene OTFTs. We found that carrier accumulation and depletion processes in the semiconductor channel layer is caused by a trap and de-trap mechanism. We apply such processes to explain C-V profiles at various gate voltages, ramp rates and sweep directions. At faster ramp rates, hysteresis can be observed from C-V profile. The phenomenon can be attributed to the asymmetry of the relaxation time of carrier trap and detrap mechanism. At the slower ramp rate, most carriers are able to interact with the gate stress, so the hysteresis disappears. And beyond this ramp rate, the corresponding threshold voltages are then kept at constant values, despite the existence of traps. Furthermore, low-mobility mobile ions or impurities participate in the charge accumulation and depletion when the ramp rate is much slower, which results in a skew of C-V profiles.

Stability of n-channel a-Si:H∕nc-Si:H bilayer thin-film transistors under dynamic stress

The stability of n-channel bottom-gated thin-film transistors (TFTs), fabricated using as channel material hydrogenated amorphous silicon∕nanocrystalline silicon bilayers, is investigated by applying on the gate pulses in the on-state and off-state regions of operation and dc bias on the drain electrode. Dynamic gate stress, with the source and drain electrodes grounded, were also performed to avoid the effect of dc stress during the dynamic stress. The degradation mechanisms are thoroughly studied for each type of stress conditions, including carrier injection in the SiNx gate insulator and generation of traps at the gate insulator∕channel interface and in the active channel material. The common features and the differences in the TFT degradation behavior under different bias stress conditions are discussed.

Effects of Hot Carriers on DC and RF Performances of Deep Submicron p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors with Various Oxide Layer Thicknesses

In this work, the effects of hot carriers on the DC and RF performances of 45 nm p-channel metal–oxide–semiconductor field-effect transistors (PMOSFETs) with various oxide layer thicknesses were investigated in detail by RF automatic measurements. It was found that a PMOSFET with a thinner oxide layer suffers more serious damage from hot carriers than that with a thicker oxide layer. Also, the greatest degradation occurs at the bias condition when gate stress voltage Vgstr is equal to drain stress voltage Vdstr, and it was found that the degradation of the cutoff frequency fT is dependent on transconductance gm only. This is different from conventional long-channel devices, in which the greatest degradation takes place at Vgstr = Vdstr/2 and when fT is dependent on both gm and the total gate capacitance Cgg (=Cgs+Cgd).

Ultra-Low Drift Voltage by Using Gate Voltage Control in Oxide-Based Gate ISFET

In this study, a simple and cheap way to solve the drift problem is presented which describes the relation of drift and gate voltage. Constant various gate voltages are biased in sensing layers with reference electrode. It obviously shows a strong relation of gate drifts and gate stress voltages. When the gate voltage is controlled as 0.5 V, the drift voltage of SiO2 gate ISFET will decrease from 56.12 to 2.94 mV in ten hours measurement. The improvement of drift voltage reaches 94.8%. When the gate voltage is controlled as -1 V, the drift voltage of ZrO2 gate ISFET will also decrease from -57.94 to 0.76 mV. The improvement of drift voltage reaches 98.7%. This may result from the gate electric field affecting the ions to diffusive into the gate insulator. By this way, we can commercialize the ISFET with a very low drift rate in a simple way.

Device Performance and Reliability Characterization of Interface and Bulk Effect in Amorphous Indium Gallium Zinc Oxide (a-IGZO) Thin Film Transistor

Abstracta-IGZO TFT is a promising candidate device for an alternative to poly-Si TFTs or a-Si TFTs, because they provide better uniformity in terms of their important device parameters, including the threshold voltage and mobility due to their amorphous phase, and a high mobility (>10 cm2/Vs) is attainable with these devices even in the amorphous phase. Recently, a-IGZO TFTs have been extensively studied by various groups. However, there is little report on interface and bulk effect on device performances and reliability as separately. For investigating the interface and bulk effect, we fabricated two a-IGZO thin film transistors with different channel deposition conditions, RF and DC magnetron sputtering. Specific conditions of RF and DC sputtering are described as follows; magnetron power density of 1.4 W/cm2/2.0 W/cm2 in Ar/O2 gas ratio of (65/35)/(72/28), and the entire gas pressure was 5.0 mTorr and 3.4 mTorr, respectively.In order to characterize the channel quality, C-V curve was measured with various frequencies of (10KHz˜1MHz). RF sputtered channel has higher frequency dependency compared to DC sputtered channel. It means that RF sputtered channel has higher bulk traps in channel compared to DC sputtered channel.Device performance was characterized through the ID-VG measurement. Electrical parameters of RF and DC sputtered devices are VT=3.5/2.7V, on-off ratio=105/08, SS=2/0.4 V/decade, and uFE= 5/11 cm2/V-s, respectively. It is thus clear that the device performance of DC sputtered device is more superior to RF sputtered device. Therefore, it can be said that the poor device performance of RF device is ascribed to insufficient channel quality, as mentioned in C-V curve.For reliability study, we measured PBTI and ID-VG hysteresis with normalized gate stress bias and high temperature hot chuck system. Through the unchanged field effect mobility during the stress and relaxation time, and nearly recovered VT and subthreshold slope (SS) after long relaxation time, we were able to know that pre-existed trap was main factor of reliability degradation. Moreover, SS degradation during stress time is more severe in RF device than DC device. It is also proving that RF channel characteristic is worse than DC channel. In high temperature, leakage current increments of RF device were more severe than DC device. This also indicates that bulk traps of RF device in channel region are larger than that of DC device. VT shift of DC sputtered device for PBT stress and hysteresis was higher than that of RF sputtered device. As well known, PBTI is closely related to insulator bulk traps, which shows that channel deposition conditions affect insulator trap characteristics. In summary, device performance of a-IGZO deposited by DC sputtering is better than RF sputtering, which is because DC sputtering improves channel quality of a-IGZO. However, VT shift of DC sputtered device are worse than RF sputtering, which may be related with high magnetron power density.

Quasi-static capacitance–voltage characterizations of carrier accumulation and depletion phenomena in pentacene thin film transistors

We analyze charge accumulation and depletion behaviors from C–V curves at various gate voltages, ramp rates and sweep directions in pentacene OTFTs. The polycrystalline property of the pentacene layer has lead to carrier charge and discharge processes in the channel layer by a trap-controlled transport mechanism. We apply such processes to describe C–V profiles at various ramp rates. Hysteresis can be observed from C–V curves at faster ramp rates. The phenomenon can be attributed to the difference of the relaxation time of carrier trap and detrap processes. As the ramp rate becomes slower, hysteresis disappears since most carriers are able to interact with the gate stress. And beyond this ramp rate, the corresponding threshold voltages are then kept at constant values, despite the existence of traps. Furthermore, low-mobility carriers (mobile ions or impurities) participate in the charge accumulation and depletion when the ramp rate is even slower, which results in a skew of C–V profiles. Finally, we extend the C–V measurement to devices with different channel lengths.