Characteristics Of Gate Stacks Research Articles

The achievement of the super short channel control in the magnetic Ge n-FinFETs with the negative capacitance effect

Super short channel control (sub-threshold swing = 95 mV/dec) in Ge n-type Fin Field-Effect Transistors (n-FinFETs) is achieved through the promising gate stack characteristics of gate leakage (Jg)-equivalent-oxide-thickness (EOT) and ultra-high k-value (∼312) with the implement of the magnetic gate stack scheme. On the other hand, the negative capacitance effect is also observed in the magnetic Ge n-FinFETs by the extraction of the body factor (m = 0.47) at low temperature measurement. The proposed magnetic gate stack scheme (tetragonal-phase BaTiO3 as the dielectric layer and magnetic FePt film as the metal gate) in the Ge n-FinFETs has super Jg-EOT characteristics, negative capacitance phenomenon, and promising transistor performance. It provides the useful solution for the future low power mobile devices designed on the high mobility (Ge) material.

The demonstration of promising Ge n-type multi-gate-field-effect transistors with the magnetic FePt metal gate scheme

In this work, the tetragonal-phase BaTiO3 high dielectric (HK) layer and the magnetic FePt metal gate (MG) film are proposed to be the gate stack scheme on the Ge three dimensional (3D) n-type multi-gate-field-effect transistors (FETs). The ∼75% dielectric constant (κ-value) improvement, ∼100× gate leakage (Jg) reduction, and ∼70% on-state current (Ion) enhancement are achieved due to the colossal magneto-capacitance effect. The magnetic field from the magnetic FePt MG film couples and triggers more dipoles in the BaTiO3 HK layer and then results in the super gate stack characteristics. The promising transistor's performance (∼200 μA/μm on the device with the gate length Lch = 60 nm) on the high mobility (Ge) material in the 3D n-type multi-gate-FETs device structure demonstrated in this work provides the useful solution for the future advanced logic device design.

The demonstration of the magnetic Ge metal-oxide-semiconductor field-effect transistor

The promising magnetic Ge metal-oxide-semiconductor field-effect transistor (MOSFET) is demonstrated by the implement of the BaTiO3 as the gate dielectric layer and the magnetic FePt film as the metal gate (MG) on the Ge (100) substrate. The designed magnetic FePt MG with the intrinsic 0.2 Tesla magnetic field along the vertical direction leads to ∼0.75 nm equivalent-oxide-thickness (EOT) reduction, ∼100X gate leakage (Jg) reduction, and ∼50% on-current (Ion) enhancement in the Ge FET due to the demonstration of the colossal magneto-capacitance effect. The influence of the magnetic field along different directions such as the vertical and the lateral direction on the Ge FET is also investigated in this work. The designed magnetic gate stack scheme on the Ge FET with the better Jg-EOT gate stack characteristics, Ion, and the short channel control behavior (Sub-threshold swing-EOT) provides the useful solution for the future low power mobile device design.

The demonstration of colossal magneto-capacitance effect with the promising gate stack characteristics on Ge (100) by the magnetic gate stack design

The tetragonal-phase BaTiO3 as the high dielectric (HK) layer and the magnetic FePt film as the metal gate (MG) are proposed to be the gate stack scheme on the Ge (100) substrate. The ∼75% dielectric constant (κ-value) improvement, ∼100X gate leakage (Jg) reduction, and the promising Jg-equivalent-oxide-thickness (EOT) gate stack characteristics are achieved in this work with the colossal magneto-capacitance effect. The perpendicular magnetic field from the magnetic FePt MG film couples and triggers the more dipoles in the BaTiO3 HK layer and then results in the super gate capacitance (Cgate) and κ-value. Super Jg-EOT gate stack characteristics with the magnetic gate stack design on the high mobility (Ge) substrate demonstrated in this work provides the useful solution for the future low power mobile device design.

Explanation of the Charge-Trapping Properties of Silicon Nitride Storage Layers for NVM Devices Part I: Experimental Evidences From Physical and Electrical Characterizations

In part I of this paper, we study the physicochemical structure and the electrical properties of low-pressure-chemical-vapor-deposited silicon nitride (SiN) aimed to serve as storage layers for nonvolatile memory applications. An in-depth material analysis has been carried out together with a comprehensive electrical characterization on two samples fabricated with recipes yielding rather standard SiN and Si-rich SiN. The investigation points out the impact of SiN stoichiometry and hydrogen content on the electrical characteristics of gate stacks designed in view of channel hot-electron/hole-injection program/erase (P/E) operation and tunnel P/E operation. The extensive and detailed characterization establishes a sound experimental basis for the development of the physics-based trap models proposed in the companion paper.

TiN / HfO2 / SiO2 / Si Gate Stack Breakdown: Contribution of HfO2 and Interfacial SiO2 Layer

By studying systematically the breakdown mechanisms of and interfacial separately in this work, we have demonstrated that defect generation in the interfacial layer seems to be the leading breakdown mechanism in the metal/high-κ/interfacial layer/Si gate stack. The individual breakdown characteristics of , without any interfacial layer using a metal–insulator–metal capacitor, and an in situ steam-grown metal–oxide–semiconductor capacitor with identical thicknesses and growth conditions, were compared with the gate stack characteristics. The breakdown behavior and stress-induced leakage current measurements suggest that charge trapping and stress-induced trap formation in the interfacial layer continues to be the soft spot for gate stack breakdown.

N-Channel GaAs MOSFET with TaN ∕ HfAlO Gate Stack Formed Using In Situ Vacuum Anneal and Silane Passivation

A surface passivation technique for GaAs that comprises in situ vacuum anneal and silane treatment and that is compatible and can be easily integrated with a matured metallorganic chemical vapor deposition high- gate dielectric process module is demonstrated. Extensive investigation of the dependence of electrical characteristics of gate stacks on process conditions, including in situ vacuum anneal and treatment temperatures, postgate-dielectric deposition anneal, and forming gas anneal conditions, is reported. It is shown that excellent capacitance-voltage characteristics with low-frequency dispersion, small hysteresis, and low midgap interface state density of can be achieved with optimum processing conditions. The passivation technique reported here enables the fabrication of a self-aligned n–metal oxide semiconductor field-effect transistor, exhibiting good transfer characteristics with high peak carrier mobility of . The incorporation of and coimplantation for achievement of high dopant activation in deep source and drain (S/D) regions and complementary metal oxide semiconductor compatible gold-free–based PdGe S/D ohmic contacts were also demonstrated.

Comparison of Modeling Approaches for the Capacitance–Voltage and Current–Voltage Characteristics of Advanced Gate Stacks

In this paper, we compare the capacitance-voltage and current-voltage characteristics of gate stacks calculated with different simulation models developed by seven different research groups, including open and closed boundaries approaches to solve the Schroumldinger equation inside the stack. The comparison has been carried out on template device structures, including pure SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectrics and high-kappa stacks, forcing the use of the same physical parameters in all models. Although the models are based on different modeling assumptions, the discrepancies among results in terms of capacitance and leakage current are small. These discrepancies have been carefully investigated by analyzing the individual modeling parameters and the internal quantities (e.g., tunneling probabilities and subband energies) contributing to current and capacitance

Properties of Ru ∕ HfxSi1 − xOy ∕ Si Metal Oxide Semiconductor Gate Stack Structures Grown by Atomic Vapor Deposition

Capacitance-voltage characteristics of gate stacks with composition and were analyzed. The characteristics revealed a high density of negative fixed charges in the oxide film. We have observed that the value of the Ru work function remained constant after forming gas annealing at temperatures between 430 and , respectively, while fixed charges were reduced at temperatures above . We speculated that the decrease of negative fixed charges can be explained by the generation of positively charged centers in the oxide layer. The positively charged centers can account for a compensation of the negative fixed oxide charge. Rapid thermal annealing at temperatures up to in nitrogen did not influence the fixed oxide charges in the films.