Gate Recess Technique Research Articles

Monolithic β -Ga2O3 NMOS IC based on heteroepitaxial E-mode MOSFETs

In this Letter, we report on a monolithically integrated β-Ga2O3 NMOS inverter integrated circuit (IC) based on heteroepitaxial enhancement mode (E-mode) β-Ga2O3 metal-oxide-semiconductor field-effect transistors on low-cost sapphire substrates. A gate recess technique was employed to deplete the channel for E-mode operation. The E-mode devices showed an on-off ratio of ∼105 with a threshold voltage of 3 V. In comparison, control devices without the gate recess exhibited a depletion mode (D-mode) with a threshold voltage of −3.8 V. Furthermore, depletion-load NMOS inverter ICs were fabricated by monolithically integrating D- and E-mode transistors on the same substrate. These NMOS ICs demonstrated inverter logic operation with a voltage gain of 2.5 at VDD = 9 V, comparable with recent GaN and other wide-bandgap semiconductor-based inverters. This work lays the foundation for heteroepitaxial low-cost and scalable β-Ga2O3 ICs for monolithic integration with (ultra)wide bandgap Ga2O3 power devices.

Study on positive threshold voltage shift and DC characteristics of HEMTs using gate recess technique

In the present study, AlGaN/GaN high-electron-mobility transistors (HEMTs) were fabricated through metal–organic chemical vapor deposition. Gate recess etching, combined with inductively coupled plasma reactive ion etching, was adopted, and etching time was controlled to manipulate the threshold voltage [Formula: see text]. The DC characteristics of devices etched for 0–25 s were investigated. [Formula: see text] exhibited a 1.9-V positive shift in the device with the AlGaN layer etched for 25 s. The effect of an AlN buffer layer on the [Formula: see text] shift was also investigated. The [Formula: see text] of the HEMT etched for 25 s and without an AlN buffer layer exhibited a positive shift of 3.1 V.

Enhanced Sensitivity Pt/AlGaN/GaN Heterostructure NO₂ Sensor Using a Two-Step Gate Recess Technique

Based on our proposed precision two-step gate recess technique, a suspended gate-recessed Pt/AlGaN/GaN heterostructure gas sensor integrated with a micro-heater is fabricated and characterized. The controllable two-step gate recess etching method, which includes O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma oxidation of nitride and wet etching, improves gas sensing performance. The sensitivity and current change of the AlGaN/GaN heterostructure to 1-200 ppm NO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /air are increased up to about 20 and 12 times compared to conventional gate device, respectively. The response time is also reduced to only about 25 % of value for conventional device. The sensor has a suspended circular membrane structure and an integrated micro-hotplate for adjusting the optimum working temperature. The sensitivity (response time) increases from 0.75 % (1250 s) to 3.5 % (75 s) toward 40 ppm NO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /air when temperature increase from 60°C to 300°C. The repeatability and cross-sensitivity of the sensor are also demonstrated. These results support the practicability of a high accuracy and fast response gas sensor based on the suspended gate recessed AlGaN/GaN heterostructure with an integrated micro-heater.

GaN MIS-HEMT PA MMICs for 5G Mobile Devices

As the data transfer rates in various mobile systems increase, the needs for 5G wireless communication systems have also been correspondingly increased. For the enhancement of data transfer rates, 28 GHz, one of the high frequency bands proposed by Korea for global standards, was chosen for 5G systems. While GaN-based high-electron-mobility transistors (HEMTs) are very promising candidates for 5G network applications due to their usage in high output power amplifiers, typical GaN HEMTs only operate in a normally-on state. However, for successful operations of mobile handsets of 5G systems, a normally-off device operating under positive gate bias is required, which provides advantages of decreased circuit complexity and system cost, as well as potential for use in the domain of digital circuits. For positive gate bias operation, metal-insulator-semiconductor (MIS)-HEMT devices were fabricated by using the ETRI GaN MIS-HEMT process. We designed and fabricated MIS-HEMTs and characterized their performances. In addition to the adaptation of a gate recess technique, we employed an Al2O3 gate insulator to shift the threshold voltage in GaN MIS-HEMTs. The power amplifier (PA) monolithic microwave integrated circuit (MMIC) was designed and operated under a positive gate bias for 5G mobile handsets and exhibited a maximum output power of 29.5 dBm, a power gain of 11 dB, and a power added efficiency (PAE) of 11% at frequencies of 26 and 28 GHz.

Correlation between border traps and exposed surface properties in gate recessed normally-off Al2O3/GaN MOSFET

We report the effect of the gate recess process and the surface of as-etched GaN on the gate oxide quality and first reveal the correlation between border traps and exposed surface properties in normally-off Al2O3/GaN MOSFET. The inductively coupled plasma (ICP) dry etching gate recess with large damage presents a rough and active surface that is prone to form detrimental GaxO validated by atomic force microscopy and X-ray photoelectron spectroscopy. Lower drain current noise spectral density of the 1/f form and less dispersive ac transconductance are observed in GaN MOSFETs fabricated with oxygen assisted wet etching compared with devices based on ICP dry etching. One decade lower density of border traps is extracted in devices with wet etching according to the carrier number fluctuation model, which is consistent with the result from the ac transconductance method. Both methods show that the density of border traps is skewed towards the interface, indicating that GaxO is of higher trap density than the bulk gate oxide. GaxO located close to the interface is the major location of border traps. The damage-free oxidation assisted wet etching gate recess technique presents a relatively smooth and stable surface, resulting in lower border trap density, which would lead to better MOS channel quality and improved device reliability.

High-Temperature-Recessed Millimeter-Wave AlGaN/GaN HEMTs With 42.8% Power-Added-Efficiency at 35 GHz

In this letter, a high-temperature (HT) gate recess technique is implemented into the fabrication of high-performance millimeter-wave AlGaN/GaN highelectron-mobility transistors (HEMTs). By virtue of the low damage feature of the HT recess, a high extrinsic transconductance of 422 mS/mm, a three-terminal breakdown voltage of 134 V with a source-drain separation of 2.4 μm, and a remarkable low Schottky gate leakage current of 1.6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> A/mm at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> = -60 V are achieved, which is at least two orders of magnitude lower than the HEMTs with gate recessed at room temperature. By employing a 0.2-μm T-shaped gate technology, a current-gain cutoff frequency f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of 81 GHz and a unit-power-gain frequency fMAX of 194 GHz are realized. The current collapse in the HT-recessed AlGaN/GaN HEMTs is significantly suppressed, contributing to a record high power-addedefficiency of 42.8%, as well as high output power density of 5.1 W/mm at 35 GHz in a continuous-wave mode.

An “ohmic-first” self-terminating gate-recess technique for normally-off Al2O3/GaN MOSFET

In this article, an ohmic-first AlGaN/GaN self-terminating gate-recess etching technique was demonstrated where ohmic contact formation is ahead of gate-recess-etching/gate-dielectric-deposition (GRE/GDD) process. The ohmic contact exhibits few degradations after the self-terminating gate-recess process. Besides, when comparing with that using the conventional fabrication process, the fabricated device using the ohmic-first fabrication process shows a better gate dielectric quality in terms of more than 3 orders lower forward gate leakage current, more than twice higher reverse breakdown voltage as well as better stability. Based on this proposed technique, the normally-off Al2O3/GaN MOSFET exhibits a threshold voltage (Vth) of ∼1.8 V, a maximum drain current of ∼328 mA/mm, a forward gate leakage current of ∼10−6 A/mm and an off-state breakdown voltage of 218 V at room temperature. Meanwhile, high temperature characteristics of the device was also evaluated and small variations (∼7.6%) of the threshold voltage was confirmed up to 300 °C.

Normally-off Al2O3/GaN MOSFET: Role of border traps on the device transport characteristics

Based on the self-terminating gate recess technique, two different processes featuring gate-recess-first (GF) and ohmic-contact-first (OF) were proposed for E-mode Al2O3/GaN MOSFETs. Increased maximum drain current (Idmax) ∼30% (420 vs 325 mA/mm), field-effect mobility (μFEmax) ∼67% (150 vs 90 cm2/Vs) and reduced on-state resistance (Ron) ∼42% (9.7 vs 16.8 Ω·mm) were observed in the devices fabricated by GF process. Such significant performance difference of GF- and OF-devices resulted from the presence of border traps at Al2O3/GaN interface with a time constant ∼7 × 10−6 s. Experimental results indicated that: (1) the near interface border traps in Al2O3 dielectric significantly affect device channel mobility; (2) a high temperature post-deposition annealing process could effective suppress generation of border traps.

Characteristics of enhanced-mode AlGaN/GaN MIS HEMTs for millimeter wave applications

In this paper, an enhanced-mode (E-mode) AlGaN/GaN high electron mobility transistor (HEMT) was developed by using 4-inch GaN HEMT process. We designed and fabricated Emode HEMTs and characterized device performance. To estimate the possibility of application for millimeter wave applications, we focused on the high frequency performance and power characteristics. To shift the threshold voltage of HEMTs we applied the Al2O3 insulator to the gate structure and adopted the gate recess technique. To increase the frequency performance the e-beam lithography technique was used to define the 0.15 um gate length. To evaluate the dc and high frequency performance, electrical characterization was performed. The threshold voltage was measured to be positive value by linear extrapolation from the transfer curve. The device leakage current is comparable to that of the depletion mode device. The current gain cut-off frequency and the maximum oscillation frequency of the E-mode device with a total gate width of 150 um were 55 GHz and 168 GHz, respectively. To confirm the power performance for mm-wave applications the load-pull test was performed. The measured power density of 2.32 W/mm was achieved at frequencies of 28 and 30 GHz.

Integration of Gate Recessing and &lt;italic&gt;In Situ&lt;/italic&gt; Cl− Doped Al2O3 for Enhancement-Mode AlGaN/GaN MOSHEMTs Fabrication

This letter demonstrates an integration process of in situ Cl− doped Al2O3 and gate recess technique to fabricate the enhancement mode AlGaN/GaN MOSHEMTs. The Cl− doped Al2O3 thin film is deposited by the ultrasonic spray pyrolysis deposition and characterized by transmission electron microscopy and X-ray photoelectron spectroscopy. The relative permittivity of Cl− doped Al2O3 is higher than the pure Al2O3 and the output current is enhanced. The threshold voltage of the enhancement mode AlGaN/GaN MOSHEMT with the Cl− doped Al2O3 gate dielectric layer rose from 0.2 to 1.3 V. Furthermore, the breakdown voltage of present enhancement mode AlGaN/GaN MOSHEMT reached 650 V. It was also found that the MOSHEMT with Cl− doped Al2O3 has higher gate leakage than that with pure Al2O3. The thermal stability of threshold voltage and current collapse phenomenon is described in this letter.

Time-dependent threshold voltage drift induced by interface traps in normally-off GaN MOSFET with different gate recess technique

The time-dependent threshold voltage drift induced by fast interface traps in a fully gate-recessed normally-off GaN MOSFET is studied. It is found that the degree and time scale of the shift in threshold voltage are consistent with the density and time constant of interface traps at the MOS interface. The device based on wet etching delivers higher interface quality and threshold voltage stability than that based on dry etching. Nitrogen deficiency and high oxygen coverage are considered to be the origins of the high interface trap density in the MOSFET fabricated by dry etching.

Normally OFF GaN-on-Si MIS-HEMTs Fabricated With LPCVD-SiNx Passivation and High-Temperature Gate Recess

Low-current-collapse normally OFF GaN-on-Si MIS high-electron-mobility transistors (MIS-HEMTs) are fabricated with low-pressure chemical-vapor-deposited SiN x (LPCVD-SiN x ) passivation and high-temperature low-damage gate-recess technique. The high-thermal-stability LPCVD-SiN x enables a passivation-prior-to-ohmic process strategy and effectively suppresses deep states at the passivation/HEMT interface. The fabricated MIS-HEMTs feature a high $V_{\rm {TH}} $ of +0.85 V at the drain current of 1 $\mu $ A/mm and a remarkable ON/OFF current ratio of 1010 while reduced dynamic ON-resistance as compared to plasma-enhanced chemical-vapor-deposited SiO2 passivation. High field-effect channel mobility of 180 cm $^{2}/ \text{V} \cdot \text{s} $ is achieved, leading to a high maximum drain current density of 663 mA/mm.

High RF Performance Enhancement-Mode Al&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;3&lt;/sub&gt;/AlGaN/GaN MIS-HEMTs Fabricated With High-Temperature Gate-Recess Technique

In this letter, we report high-performance enhancement-mode (E-mode) Al2O3/AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) fabricated with high-temperature low-damage gate recess technique. The high-temperature gate recess is implemented by increasing the substrate temperature to 180 °C to enhance the desorption of chlorine-based etching residues during the dry etching of AlGaN barrier. High-crystal-quality Al2O3 gate dielectric was grown by atomic-layer deposition using O3 as the oxygen source to suppress hydrogen-induced weak bonds. The fabricated E-mode MIS-HEMTs exhibit a threshold voltage of 1.6 V, a pulsed drive current of 1.13 A/mm, and very low OFF-state standby power of $6.8 \times 10^{\mathrm {-8}}$ W/mm at $V_{\mathrm {GS}} =0$ V and $V_{\mathrm {DS}} =30$ V. At 4 GHz and in pulse-mode operation, the output power density and power-added efficiency were measured to be 5.76 W/mm and 57%, both of which are the highest for GaN-based E-mode MIS-HEMTs reported to date.

O3-sourced atomic layer deposition of high quality Al2O3 gate dielectric for normally-off GaN metal-insulator-semiconductor high-electron-mobility transistors

High quality Al2O3 film grown by atomic layer deposition (ALD), with ozone (O3) as oxygen source, is demonstrated for fabrication of normally-off AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs). Significant suppression of Al–O–H and Al–Al bonds in ALD-Al2O3 has been realized by substituting conventional H2O source with O3. A high dielectric breakdown E-field of 8.5 MV/cm and good TDDB behavior are achieved in a gate dielectric stack consisting of 13-nm O3-Al2O3 and 2-nm H2O-Al2O3 interfacial layer on recessed GaN. By using this 15-nm gate dielectric and a high-temperature gate-recess technique, the density of positive bulk/interface charges in normally-off AlGaN/GaN MIS-HEMTs is remarkably suppressed to as low as 0.9 × 1012 cm−2, contributing to the realization of normally-off operation with a high threshold voltage of +1.6 V and a low specific ON-resistance RON,sp of 0.49 mΩ cm2.

Normally-off GaN recessed-gate MOSFET fabricated by selective area growth technique

In this letter, a normally-off GaN recessed-gate MOSFET is demonstrated using a nonplasma gate recess technique, in which the access region with AlGaN/GaN heterostructure was selectively grown on a semi-insulating GaN/Si template to naturally form a recessed gate. The normally-off recessed-gate Al2O3/GaN MOSFET presents a high threshold voltage of 3.5 V and a maximum drain current density of 550 mA/mm (at a positive gate bias of 12 V). A maximum field-effect mobility of 170 cm2 V−1 s−1 and a large on/off current ratio of more than 107 was obtained, which indicates the high quality of the Al2O3/GaN interface.

Electrical, optical and surface properties of P 2S 5/(NH 4) 2S x+ Se-treated doped-channel field-effect transistors with double etch-stop layers

This work describes doped-channel field-effect transistors (DCFETs), featuring both low–high doped-channels and double AlAs etch-stop layers used in a selective etch recessed-gate process. A developed highly selective wet etching process is applied as a gate-recess technique to fabricate DCFETs. Selective wet etching using citric acid/H 2O 2/NH 4OH/H 2O solutions in conjunction with double thin AlAs etch-stop layers is a reasonably simple, safe, and reliable process for gate recessing in the fabrication of the DCFETs herein. Surface passivation using P 2S 5/(NH 4) 2S x+ Se on GaAs Schottky barrier diodes, formed by Pt/Au contacts, is examined for the first time and the results are compared with those of unpassivated devices. For the passivated Pt/Au gate device, the two-terminal gate-drain breakdown (source floating) at − 1 mA/mm is 17 V, and the device provides an excellent combination of transconductance and output current. The X-ray photoelectron spectroscopy, secondary ion mass spectrometry, and photoluminescence results are highly consistent with the Schottky barrier measurements and the device performance.

Gate‐recessed normally‐off GaN‐on‐ Si HEMT using a new O2‐BCl3 digital etching technique

AbstractA new, semi‐self‐limiting, digital etch process using separate oxygen (O2) and boron trichloride (BCl3) plasmas to sequentially remove layers of material from AlGaN/GaN high electron mobility transistors (HEMTs) on the order of a few angstroms per cycle is presented. This novel digital or atomic layer etching (ALE) technique was used for the conversion of AlGaN/GaN HEMT devices from depletion mode (normally‐on operation) to enhancement mode (normally‐off operation). For a fixed BCl3 time of 60 sec per cycle, the etch rate per cycle was increased from 1.4 nm/cycle to 2.5 nm/cycle by increasing the O2 time per cycle from zero to 15 seconds, and remained fairly constant with higher O2 time per cycle for a self‐limiting etch process. Two GaN‐on‐Si wafers from the same CVD growth were processed side‐by‐side using the device layout and process steps, except for the depletion‐to‐enhancement conversion step, to compare ALE and fluorine treatment. The ALE‐processed had a peak gm of 250 mS/mm, 67% higher than the fluorine‐treatment process. The ALE process resulted in a threshold voltage variation of +/‐ 150 mV across the 3 inch wafer (σ = 63 mV), which was less than half of that of the fluorine‐treatment wafer. The three‐terminal breakdown voltage of the ALE‐processed wafer exceeded 1100 V, which is the first demonstration of such a high voltage device using GaN‐on‐Si and a gate recess technique, and the drain leakage current was in the μA/mm range at 1100 V. (© 2010 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

An over 100 W AlGaN/GaN enhancement‐mode HEMT power amplifier with piezoelectric‐induced cap structure

AbstractA novel piezoelectric‐induced cap structure in an AlGaN/GaN high electron mobility transistor (HEMT) was developed for enhancement‐mode (E‐mode) operation with high maximum drain current density (Idmax), high breakdown voltage (BVgd) and small current collapse. Our developed cap structure consists of a thin GaN/AlN/ GaN triple‐layer, which reduces the sheet resistance (Rsh) due to conduction band bending. The threshold voltage (Vth) is +0.25 V with a high Idmax of 520 mA/mm, a high BVgd of 336 V and small current collapse by using the developed cap structure and a gate recess technique. The single‐chip AlGaN/GaN E‐mode HEMT amplifier achieved a high output power of 126 W at 2.5 GHz with improved distortion characteristics. This is the first report of an AlGaN/GaN E‐mode HEMT with an output power of over 100 W. (© 2009 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

SiC MESFET with a Double Gate Recess

In order to increase the output power and drain efficiency, MESFETs in SiC have been made with a double gate recess technique. Typical device characteristics of the MESFETs are drain currents of 380mA/mm, breakdown voltages of 80V and ft/fmax of 10/25 GHz respectively. These transistors exhibit power densities of 3W/mm@3GHz in class AB operation and drain efficiencies of 60%. Packaged devices with 3 mm gate periphery of this type, with via-hole grounding, gave power densities of 1.2 W/mm@6GHz at 50 V drain bias.

Novel high uniformity highly reproducible non-selective wet digital gate recess etch process for InP HEMTs

A new non-selective wet digital etching technique has been developed to etch In 0.53Ga 0.47As/In 0.52Al 0.48As structure for the gate recess of InP High Electron Mobility Transistors (HEMTs). Both precise etch depth and well-controlled undercut width were achieved. A very smooth etched surface was also demonstrated by this new etching technique. 120 nm gate length InP HEMTs were fabricated using this new gate recess process. A maximum transconductance, g m, of 600 mS/mm and current cut-off frequency, f T, of 175 GHz were achieved. Those devices performances are comparable to the best results we have achieved by using other gate recess technique. Finally, this new recess etching process is highly uniform and reproducible.