Gate Pulse Research Articles

Performance of Single Phase Soft Switching Inverter using Artificial Neural Network

Advanced teaching method for Single Phase Soft Switching, Inverter using Artificial Neural Network based on simulations and hardware experiment been described in this paper. In this proposed inverter used one extra auxiliary switch. The auxiliary and main switches to achieve zero voltage switching through proper PWM gate pulse with suitable delays. All the switches were working under ZVS condition. The performance of the planned soft switching inverter with Artificial Neural Network (ANN) controller has been analyzed and compared with Fuzzy and PI controller with complete simulation circuit developed using MATLAB/Simulink toolbox. Experimental setup Input voltage: 220Vdc, Output voltage: 120Vrms, Switching frequency: 50kHz hardware model is presented. Controllers are compared based on the time response specifications. Simulation and hardware results were obtained and presented to validate the proposed controller's overall operation under practical operating environment. The proposed method used to students learning the switching losses analysis in the inverter and focus the research in the field of power electronics switches.

Simulation and experimental validation of hysteresis current control technique for speed control of brushless DC motor

Brushless DC Motors (BLDC) are finding wide applications in household appliances and electrical vehicles. Microcontroller are widely used for controlling the BLDC motors however the realization of BLDC drive requires expertise in microcontroller programming. In this paper modelling, simulation and easy hardware implementation of BLDC motor having shaft encoder using STM32F4 series ARM Cortex-M4 microcontroller is demonstrated. A simple method of controlling the BLDC motor in closed loop, using a hysteresis current controller is implemented. The hall sensors are used to find the exact rotor position for the electronic commutation and the encoder is used to measure actual motor speed. The closed loop operation consists of an inner loop which is hysteresis current controller. The gate pulses for the three phase inverter bridge are produced by comparing the actual currents with the reference currents. The outer speed loop consists of a PI controller which compares the actual speed with the reference speed to obtain smooth speed control under varied load condition. The complete hardware circuits and MATLAB/Simulink environment blocks for programming are discussed in detail. The hardware results demonstrate the easy and accurate realisation of closed loop speed control of BLDC Motor.

Solar Powered Battery Charging System Using Optimized PI Controller for Buck Boost converter

The basic framework for tuning Genetic Algorithm (GA) is to bring the system to stable condition with proportional Integral controller for DC-DC converter (Buck -Boost Converter) which is applied to PV source. Due to its non-linear characteristics, the performance of the controller needs to be improved in order to improve its efficiency. The gating pulses of the converter uses Pulse Width Modulation (PWM) technique in order to reduce its THD level. The main purpose of PI controller is to bring down the large values of instabilities in the system response and to reduce steady state error which in turns improves the gain and accuracy. Genetic Algorithm (GA) is a search algorithm to solve optimization problems. The controller parameters are optimized to produce reasonable transient response without affecting the stable operation. Output voltage magnitude of DC–DC converter is either greater than or lesser than the input voltage magnitude. Variable DC voltage from PV panel is applied to DC – DC converter to get constant DC output voltage. The modelling of the Proposed system is modelled using MATLAB/SIMULINK and its results are verified.

Fractional-Order Notch Filter for Grid-Connected Solar PV System With Power Quality Improvement

In this article, we deal with the development of a fractional-order notch filter (FONF) for a grid-connected solar photovoltaic (PV) system. The developed FONF control approach is used to estimate fundamental active constituents from the distorted load currents, and hence, gating pulses for operating voltage source converter (VSC) are used in the PV system. This control approach for the grid-connected solar PV system is designed to achieve several purposes, such as feeding active power demand of the load/grid and countercurrent-related power quality issues at the common connecting point. The power quality issues taken into consideration are harmonics distortion, reactive power burden on the system, and unbalancing of connected loads. The FONF-based control proposes a modified structure of an integer-order notch filter. The integer-order filters have a limitation due to the fixed integrator and differentiator terms. In FONF, the power of integrator used in a notch filter can be modified according to the application required for obtaining the accurate response of the system. A prototype of the grid-connected solar PV system is developed in the laboratory using IGBTs based VSC and dSPACE MicroLabBox (DS-1202) to demonstrate the behavior of the FONF-based control. Simulation and experimental results are obtained for steady-state and unbalanced loads with variation in the solar irradiance. The harmonic distortions in the system are observed as per the IEEE-519 standard.

Analysis of Distribution Grid, Power Loss Reduction and Fault Detection in 33 Bus System using Optimization

We have to design a system model in MATLAB 2015A software. In this analysis micro-grid 33 bus system data Power generation source are used PV these are provide constant DC outcome then these outcome improving to dc level, used dc to dc convertor. DC/DC convertor output to connect three phase invertor system. In this invertor gate pulse control using FACT- VSC device with fuzzy logic, VSC provide fixed pulse with constant duty cycle. Our proposed system optimization of 33 bus system data power loss, faulty bus and DG placement in term of stability index.

Control of three wire DSTATCOM using cascaded delayed signal cancellation effect

ABSTRACT In this paper demonstration of three-wire distributed static compensator (DSTATCOM) for compensating disturbed ac main currents with a Frequency Locked Loop (FLL). An improvement with delayed signal cancellation (DSC) technique to a standard FLL is used. An improvement has been observed in the quality of grid current waveform in terms of distortion to 2.2% from load current distortion of 23.4% by applying DSC in cascaded mode. The standard FLL capability to extract fundamental from disturbed load current has increased with cascaded DSC operators. In order to provide fast, accurate, and precise fundamental extraction with a satisfactory dynamic response without any stability struggle, delay factors of 4 and 24 are cascaded and unified with the FLL in the recognized cascaded αβ delayed signal cancellation (Cαβ-DSCFLL).The dynamic response of the Cαβ-DSCFLL is taking three fundamental cycles to settle the system and it shows satisfactory harmonic rejection capability. A small signal model is provided for the FLL structure through which gain estimation and stability analysis is made. An optimization algorithm named JAYA algorithm which is an algorithm designed to perform a specific task, parameterless optimization framework is used for estimating the PI controller gains in modes for correcting of power factor and regulating zero voltage. An optimization problem is formulated with errors by DC as well as AC bus voltages. JAYA optimization algorithm is used for estimating gains. The disturbance removal capability of the recognized Cαβ-DSCFLL is better when compared with the other conventional ones. The efficacy of the recognized FLL has been demonstrated with experimental results on the laboratory proto type. Reactive power mitigation and removal of grid current harmonics in both modes of DSTATCOM with nonlinear load are achieved with recognized FLL and optimized gains. In realizing the recognized control algorithm, the dSPACE-1104 controller is used to generate gate pulses for DSTATCOM.

ANALYSIS AND CHARGE CONTROL OF LITHIUM ION BATTERY WITH APPLICATION FOR OFF-GRID PV SYSTEM

For the implementation of the PV micro grid, initially we designed the PV module. Once the PV module is designed we then decided to use P&O technique as an MPPT technique. The output pulse of the MPPT technique is then fed to the boost converter as gate pulse. The output of PV with dc to dc converter is then fed to DC grid from where the 3-phase Inverter with LC filter which converts the DC to 3-phase AC system and then is fed to load. Also the battery system with bidirectional controller is followed by a charge controller is also connected to DC micro grid so that the battery can charge or discharge as per the application.

Low power pulsed flip-flop with clock gating and conditional pulse enhancement

A clock system consumes above 25% of the total system power. Flip-flops (FFs) are widely used as the basic storage element in all kinds of digital structures. The use of pulse-triggered flip-flops (P-FFs) in digital design provides better performance than conventional flip-flop designs. This paper presents the design of a new power-efficient implicit pulse-triggered flip-flop suitable for low power applications. Two important features are embedded in this flip-flop architecture. Firstly, the enhancement in width and height of trigger pulses during specific conditions gives a solution for the longest discharging path problem in existing P-FFs. Secondly, the clock gating concept reduces unwanted switching activities at sleep/idle mode of operation and thereby reducing dynamic power consumption. The post-layout simulation results in cadence software based on CMOS 90 nm technology shows that the proposed design features less power dissipation and better power delay performance (PDP) when compared with conventional P-FFs. This paper also presents a comparative study on the performance of implicit and explicit pulse flip-flop designs. The maximum power saving of proposed design against conventional implicit and explicit design is up to 18.45% and 58.49%, respectively.

A New Transformer-Less Common Grounded Three-Level Grid-Tied Inverter With Voltage Boosting Capability

A new transformer-less three-level grid-tied inverter is proposed in this article. By employing the switched-capacitor (SC) modules, a new topology is derived. The proposed topology has some features which are high efficiency, the capability of voltage boosting without utilization of any additional boost stage, and suppressing the leakage current by using common grounded strategy. In this article, a peak current control is employed to generate the gate pulses of power semiconductor switches and adjustment of both active and reactive powers. By doing so, the grid injected current is controlled and adjusted to have a proper quality. The operation modes, design consideration, and a comparison with some recently proposed grid-connected topologies are done through this paper. Finally, the performance and feasibility of the proposed inverter are confirmed with a 500 W experimental prototype.

The Impact of Interfacial Charge Trapping on the Reproducibility of Measurements of Silicon Carbide MOSFET Device Parameters

Silicon carbide is an emerging material in the field of wide band gap semiconductor devices. Due to its high critical breakdown field and high thermal conductance, silicon carbide MOSFET devices are predestined for high-power applications. The concentration of defects with short capture and emission time constants is higher than in silicon technologies by orders of magnitude which introduces threshold voltage dynamics in the volt regime even on very short time scales. Measurements are heavily affected by timing of readouts and the applied gate voltage before and during the measurement. As a consequence, device parameter determination is not as reproducible as in the case of silicon technologies. Consequent challenges for engineers and researchers to measure device parameters have to be evaluated. In this study, we show how the threshold voltage of planar and trench silicon carbide MOSFET devices of several manufacturers react on short gate pulses of different lengths and voltages and how they influence the outcome of application-relevant pulsed current-voltage characteristics. Measurements are performed via a feedback loop allowing in-situ tracking of the threshold voltage with a measurement delay time of only 1 μs. Device preconditioning, recently suggested to enable reproducible BTI measurements, is investigated in the context of device parameter determination by varying the voltage and the length of the preconditioning pulse.

Temporal filtering characteristics of gated InGaAs/InP single-photon detectors for coincidence measurement

Semiconductor single-photon avalanche detectors (SPADs) have played an important role in practical quantum communication technology due to their advantages of small size, low cost and easy operation. Among them, InGaAs/InP SPADs have been widely used in fiber-optic quantum key distribution systems due to their response wavelength range in a near-infrared optical communication band. In order to avoid the influence of dark count and afterpulsing on single photon detection, the gated quenching technologies are widely applied to the InGaAs/InP SPADs. Typically, the duration of gate pulse is set to be as short as a few nanoseconds or even less. As the detection of the arrival of single photons depends on the coincidence between the arrival time of gate pulse and the arrival time of photon, the gate pulse duration of the InGaAs/InP SPADs inevitably affects the effective detection of the single photons. Without the influence of dispersion, the temporal width of the transmitted photons is usually on the order of picoseconds or even less, which is much shorter than the gate width of the InGaAs/InP SPAD. Therefore, the gate width normally has no influence on the temporal measurement of the detected photons. However, in quantum systems involving large dispersion, such as the long-distance fiber-optic quantum communication system, the temporal width of the transmitted photons is significantly broadened by the experienced dispersion so that it may approach to or even exceed the gate width of the single-photon detector. As a result, the effect of the gate width on the recording of the arrival time of the dispersed photons should be taken into account. In this paper, the influence of the gate width coupled to the InGaAs/InP single photon detectors on the measurement of the two-photon coincidence time width is studied both theoretically and experimentally. The theoretical analysis and experimental results are in good agreement with each other, showing that the finally measured coincidence time width of the two-photon state after dispersion is not more than half of the effective gate pulses width. The maximum observable coincidence time width based on the gated single photon detector is fundamentally limited by the gate width, which restricts its applications in quantum information processing based on the two-photon temporal correlation measurement.

Low power pulsed flip-flop with clock gating and conditional pulse enhancement

A clock system consumes above 25% of the total system power. Flip-flops (FFs) are widely used as the basic storage element in all kinds of digital structures. The use of pulse-triggered flip-flops (P-FFs) in digital design provides better performance than conventional flip-flop designs. This paper presents the design of a new power-efficient implicit pulse-triggered flip-flop suitable for low power applications. Two important features are embedded in this flip-flop architecture. Firstly, the enhancement in width and height of trigger pulses during specific conditions gives a solution for the longest discharging path problem in existing P-FFs. Secondly, the clock gating concept reduces unwanted switching activities at sleep/idle mode of operation and thereby reducing dynamic power consumption. The post-layout simulation results in cadence software based on CMOS 90 nm technology shows that the proposed design features less power dissipation and better power delay performance (PDP) when compared with conventional P-FFs. This paper also presents a comparative study on the performance of implicit and explicit pulse flip-flop designs. The maximum power saving of proposed design against conventional implicit and explicit design is up to 18.45% and 58.49%, respectively.

Modulating Magnetism in Ferroelectric Polymer-Gated Perovskite Manganite Films with Moderate Gate Pulse Chains.

Most previous attempts on achieving electric-field manipulation of ferromagnetism in complex oxides, such as La0.66Sr0.33MnO3 (LSMO), are based on electrostatically induced charge carrier changes through high-k dielectrics or ferroelectrics. Here, the use of a ferroelectric copolymer, polyvinylidene fluoride with trifluoroethylene [P(VDF-TrFE)], as a gate dielectric to successfully modulate the ferromagnetism of the LSMO thin film in a field-effect device geometry is demonstrated. Specifically, through the application of low-voltage pulse chains inadequate to switch the electric dipoles of the copolymer, enhanced tunability of the oxide magnetic response is obtained, compared to that induced by ferroelectric polarization. Such observations have been attributed to electric field-induced oxygen vacancy accumulation/depletion in the LSMO layer upon the application of pulse chains, which is supported by surface-sensitive-characterization techniques, including X-ray photoelectron spectroscopy and X-ray magnetic circular dichroism. These techniques not only unveil the electrochemical nature of the mechanism but also establish a direct correlation between the oxygen vacancies created and subsequent changes to the valence states of Mn ions in LSMO. These demonstrations based on the pulsing strategy can be a viable route equally applicable to other functional oxides for the construction of electric field-controlled magnetic devices.

Modulation index effect on inverter based induction motor drive

Due to a substantial increase in the use of inverter for numerous electrical appliances starting from domestics to industrial drives, an inverter may be directly connected to the power grid system. The dependency on an inverter has been increased over the years. Hence, the proper and efficient design of the inverter will lead to higher efficiency. One of the major challenges is the generation of suitable gate pulses for power switching devices, which in turn depends on the modulation index. The selection of proper modulation index will help in the production of the rated voltage. If the modulation index is less, the duration of on-time pulses will be less and hence, the device's conduction time is also less, thereby the output voltage of the inverter is reduced. A reduced voltage, when applied to an induction motor will have lower speed and even its performance will be sluggish. The speed of the motor improves when it is operated in a closed-loop for the same modulation index. This research paper tries to bring out the effect of modulation index on speed control of an induction motor based on an inverter for both open as well as closed-loop operation. The simulated results indicate that the modulation index in the vicinity to unity will provide rated voltage for the smooth operation of the motor.

Single‐phase hybrid multilevel inverter topology with low switching frequency modulation techniques for lower order harmonic elimination

A new single-phase asymmetrical multilevel inverter (MLI) is presented in this study. The proposed topology generates a staircase output voltage waveform with a maximum number of levels using less number of components compared to several existing and recent topologies. The basic module consists of a combination of two isolated DC sources with ten switches that produce all the possible number of levels. Other advantages of the proposed MLI include improved output voltage performance and a low blocking voltage of the switches. The low switching frequency pulse width modulation (LSF-PWM) technique has been used for the generation of gate pulses. In the LSF technique, selective harmonic elimination (SHE) and fundamental switching frequency PWM techniques have been discussed for the better output voltage waveform. The optimised switching angles with SHEPWM has been calculated using particle swarm optimisation considering the different combination of the elimination of lower order harmonics. Simulation work was carried out using MATLAB/SIMULINK, and a prototype was implemented to validate the proposed MLI module. Simulation and experimental results have been provided in the study to show the performance of the proposed topology with these modulation techniques.

An enhanced 17-level hybridized multilevel inverter with stair case modulation

This paper proposes a Hybridized Symmetric Cascaded Multilevel Inverter for voltage levels ranging from 5 levels to 17 levels. The proposed Multi Level Inverter (MLI) topology is built using a modified H-bridge inverter that results in an increased output voltage levels with a smaller number of solid-state switches. This technique enhances the h-bridge configuration from three level to five level by means of a bi-directional switch at source. Gating pulses of hybridized symmetric MLI are generated through staircase modulation. The operation and performance of the proposed topology is tested for different output voltage levels, simulation results prove that the proposed technique results in less THD at all levels with lesser power consumption and are easily applicable for renewable energy applications.

Pixellated Perovskite Photodiode on IGZO Thin Film Transistor Backplane for Low Dose Indirect X-Ray Detection

The integration of perovskite photodetectors with thin-film transistor (TFT) backplane or complementary metal-oxide-semiconductor CMOS circuit is a key step towards prototyping perovskite-based image sensors. Here, we demonstrate a pixel configuration for indirect X-ray detection comprising of IGZO TFTs and perovskite photodiodes (PDs). The perovskite photodiode is patterned by a two-step deposition method. Our integrated TFT/PD pixel shows a weak light detection capability down to 4 nW cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−2</sup> and a fast-transient response to the pulse light and gate switching. Combining with a CsI scintillator, the integrated pixel achieves a specific X-ray sensitivity of 8.2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8.2 \times 10^{2} \mu \mathrm{C} \mathrm{mGy}_{\text {air }}^{-1} \mathrm{~cm}^{-3}$ </tex-math></inline-formula> . Theoretically, with a state-of-the-art scintillator, the new pixel can provide a detectable signal for X-ray imaging at a dose rate as low as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10 \mu \mathrm{Gy}_{\text {air }} \mathrm{s}^{-1}$ </tex-math></inline-formula> . This work provides an advanced pixel design for high resolution, high sensitivity, and high frame-rate flat-panel imager.

Neuro-Transistor Based on UV-Treated Charge Trapping in MoTe2 for Artificial Synaptic Features.

The diversity of brain functions depend on the release of neurotransmitters in chemical synapses. The back gated three terminal field effect transistors (FETs) are auspicious candidates for the emulation of biological functions to recognize the proficient neuromorphic computing systems. In order to encourage the hysteresis loops, we treated the bottom side of MoTe2 flake with deep ultraviolet light in ambient conditions. Here, we modulate the short-term and long-term memory effects due to the trapping and de-trapping of electron events in few layers of a MoTe2 transistor. However, MoTe2 FETs are investigated to reveal the time constants of electron trapping/de-trapping while applying the gate-voltage pulses. Our devices exploit the hysteresis effect in the transfer curves of MoTe2 FETs to explore the excitatory/inhibitory post-synaptic currents (EPSC/IPSC), long-term potentiation (LTP), long-term depression (LTD), spike timing/amplitude-dependent plasticity (STDP/SADP), and paired pulse facilitation (PPF). Further, the time constants for potentiation and depression is found to be 0.6 and 0.9 s, respectively which seems plausible for biological synapses. In addition, the change of synaptic weight in MoTe2 conductance is found to be 41% at negative gate pulse and 38% for positive gate pulse, respectively. Our findings can provide an essential role in the advancement of smart neuromorphic electronics.

Implementation of XY entangling gates with a single calibrated pulse

Near-term applications of quantum information processors will rely on optimized circuit implementations to minimize gate depth and therefore mitigate the impact of gate errors in noisy intermediate-scale quantum (NISQ) computers. More expressive gate sets can significantly reduce the gate depth of generic circuits. Similarly, structured algorithms can benefit from a gate set that more directly matches the symmetries of the problem. The XY interaction generates a family of gates that provides expressiveness well tailored to quantum chemistry as well as to combinatorial optimization problems, while also offering reductions in circuit depth for more generic circuits. Here we implement the full family of XY entangling gates in a transmon-based superconducting qubit architecture. We use a composite pulse scheme that requires calibration of only a single gate pulse and maintains constant gate time for all members of the family. This allows us to maintain a high fidelity implementation of the gate across all entangling angles. The average fidelity of gates sampled from this family ranges from $95.67 \pm 0.60\%$ to $99.01 \pm 0.15\%$, with a median fidelity of $97.35 \pm 0.17\%$, which approaches the coherence-limited gate fidelity of the qubit pair. We furthermore demonstrate the utility of XY in a quantum approximation optimization algorithm in enabling circuit depth reductions as compared to the CZ only case.

Multilevel Parallel Active Power Filter Based on ANFIS Controller for Harmonic Alleviation

This paper implements a parallel active power filter (APF) with a three-level inverter and an adaptive neuro-fuzzy inference system (ANFIS)-based controller for voltage regulation. The limitations with nonlinear industrial loads are that they have high power rating and conventional two-level parallel APF cannot be used for mitigating harmonics in such applications. Hence, here a multilevel inverter-based parallel APF that meets the requirement of high-voltage high-power application is proposed. A three-level hysteresis current regulator generates gating pulses for the switches in parallel APF. The modified version of instantaneous real and reactive power (p–q) theory is applied for obtaining reference current with ease. Simulations are done to verify the performance of ANFIS controller in MATLAB with dynamic load changes and distorted supply condition. The outcome of simulation with ANFIS controller is compared with that of fuzzy logic controller (FLC), and its performance is found to be relatively better than FLC with respect to reduction in total harmonic distortion and regulation of inverter DC side capacitor voltage.