Gate Periphery Research Articles

Efficiency of chip-level versus external power combining [microwave power amplifiers

In this paper, we compare two X-band high-efficiency switched-mode amplifiers designed around two commercially available packaged MESFET's, one having a four times larger gate periphery than the other. The amplifiers using the larger and smaller devices are designed to operate in classes E and F, respectively. The smaller device gives 685 mW output power with 7.4 dB gain and 64% overall efficiency. The larger device gives 1.70 W output power with 5.3 dB gain and 57% overall efficiency. This gives an internal (or chip-level) power-combining efficiency for the larger device of 89% in terms of overall efficiency. This is compared to the combining efficiency of circuit and spatial power combining using high-efficiency amplifiers, with the goal of assessing which architecture is the most efficient in terms of total dissipated power (DC and RF).

Oxide loss at the gate periphery during high density plasma etching

This article describes experimental measurements and computer calculations of the location of microtrenches in the gate oxide at the periphery of a complementary metal-oxide semiconductor gate resulting from a polysilicon gate etch with a low pressure, high density plasma, etch tool. When the oxide is removed at the periphery of a gate with the etch process, it is possible to damage the underlying silicon in the source and drain regions. This damage may not be observable in scanning electron microscope pictures but could still lead to device degradation or failure. To measure the integrity of the oxide at the gate periphery, a modified MOS (MMOS) capacitor test structure was used to measure the electric field breakdown strength of the oxide at the gate periphery. The breakdown voltage can be related to the amount of remaining oxide at the gate periphery. This article describes the use of the MMOS test structure to measure the location of the microtrenches relative to the gate edge in a low pressure, high density plasma, polysilicon gate etch tool.

An analysis of the kink phenomena in InAlAs/InGaAs HEMT's using two-dimensional device simulation

Kink phenomena in InAlAs/InGaAs HEMTs are investigated using a two-dimensional (2-D) device simulation that takes into account impact ionization, including nonlocal field effects, and the surface states in a side-etched region at the gate periphery. The simulation model enables us to represent the kink, and it is found that the accumulation of holes generated by the impact ionization has the channel electron density in the side-etched region increase at the bias point where kink appears. When the electron density in the side-etched region is small, the hole accumulation causes a significant increase in that electron density, resulting in a large kink. The simulation results suggest a model in which the kink is described in terms of the modification of the parasitic source resistance induced by the hole accumulation. This model implies a way to eliminate the kink, that is, keeping the electron density in the side-etched region high.

Device characteristics of scaled GaN/AlGaN MODFETs

GaN/AlGaN MODFETs with gate-widths varying from 0.2 to 1 mm have been successfully fabricated, and the device characteristics have been systematically investigated. The epitaxial layers were grown directly on sapphire substrates by RF-assisted MBE. Thick-airbridge technology was employed in the fabrication of large gate periphery devices. Very stable and reproducible device characteristics have been obtained for devices with a total gate width of up to 1 mm. These device results demonstrated the excellent potential of GaN-based FETs as power cells for practical microwave applications.

High power applications for GaN-based devices

The microwave performance potential of electronic devices fabricated from GaN-based semiconductors is described. The investigation makes use of theoretical simulations and the results are compared to experimental measurements. Excellent agreement between the simulated and measured data is obtained. It is demonstrated that devices fabricated from these semiconductors make possible microwave power amplifiers with superior RF power performance, particularly at elevated temperature, compared to comparable components fabricated from GaAs MESFET's. In particular, room temperature RF output power on the order of 4–5 W mm −1 of gate periphery with power-added efficiency approaching the ideal values for class A and B operation is available. These devices are likely to find application in power amplifiers for base stations transmitters for cellular telephone systems, HDTV transmitters, power modules for phased-array radars, and other applications. The devices are particularly attractive for applications that require high RF output power and operation at elevated temperature since cooling requirements can be minimized or eliminated.

Large signal design method of distributed power amplifiers applied to a 2–18-GHz GaAs chip exhibiting high power density performances

A suitable large signal design method of distributed power amplifiers, based on the optimum FET load requirement for high power operation, is proposed in this article. The gate and drain line characteristic admittances are determined, providing both the initial values and right directions for an optimum design. To validate the proposed design method, a FET amplifier demonstrator with a gate periphery of 1.2 mm has been manufactured at the Texas Instruments foundry. The MMIC distributed amplifier demonstrated an improved power density performance of 340 mW/mm over the 2-18-GHz frequency band associated with a minimum of 13% power-added efficiency and 24% drain efficiency at 1-dB compression in CW operation

Cascaded-transistor cell distributed amplifiers

In this article a novel distributed amplifier configuration consisting of cascaded-transistor cells is presented. For a given transistor and total gate periphery (number of transistors) in the amplifier, the new configuration gives higher gain-bandwidth product than conventional distributed amplifiers. This fact is demonstrated through computer-aided simulations as well as experimental results. © 1996 John Wiley & Sons, Inc.

A GaAs low-high doped MESFET MMIC power amplifier for CDMA/AMPS dual-mode cellular telephone

An MMIC power amplifier using low-high doped GaAs MESFETs (LH-MESFETs) has been developed for a CDMA/AMPS dual mode cellular telephone. It is fully integrated on one chip (2.5 × 2.9 mm2) including all matching circuits. For CDMA operation at frequency of 836.5 MHz, an efficiency of 25%, adjacent channel leakage power of –29 dBc at 885 kHz, and –48 dBc at 1980 kHz were obtamed with an output power of 27.25 dBm and Vdd = 4.7 V. In AMPS operation, 30.5 dBm output power was obtained with 27.5 dB gain and 47% efficiency. The experimental results show that the gate periphery of LH-MESFETs and size of MMIC are much smaller than in previously reported similar amplifiers using conventional MESFET technology. This MMIC power amplifier is suitable for dual mode cellular applications.

Gate oxide loss at the periphery of a metal–oxide–semiconductor field-effect transistor resulting from a polysilicon gate etch with a helicon etch tool

This article describes a study of gate oxide loss at the gate periphery of a metal–oxide–semiconductor field-effect transistor (MOSFET) resulting from a polysilicon gate etch with a commercially available low pressure, high density plasma helicon etch tool. When the oxide is removed at the periphery of a MOSFET with the gate etch process, it is possible to damage the underlying silicon in the source and drain regions leading to device degradation or failure. Conventional oxide thickness and scanning electron microscope measurements after the gate etch have been shown to be inadequate in detecting microtrenches and microholes in the oxide at the gate periphery. To measure the integrity of the oxide at the gate periphery, a modified MOS (MMOS) capacitor test structure has been developed to measure the electrical field breakdown strength of the oxide at the gate periphery. This article describes a MMOS study of the oxide loss and underlying etch mechanisms encountered in a low pressure, high plasma density helicon etch tool.

Highly efficient double-doped heterojunction FET's for battery-operated portable power applications

Microwave power performance of double-doped AlGaAs-InGaAs-AlGaAs heterojunction field-effect transistors (HJFET's) operated at a drain bias of 3 V is described. The fabricated 1.0 /spl mu/m gate-length HJFET exhibited a maximum drain current of 500 mA/mm, a transconductance of 300 mS/mm, and a gate-to-drain breakdown voltage of 10 V. Power performance for a 14 mm gate periphery device demonstrated a maximum output power of 1.7 W with a 66% power-added efficiency (PAE) at 900 MHz. When the device was tuned for a maximum PAE, it delivered a 71% PAE with an output power of 1.2 W. The results indicate that the developed HJFET has great potential for 3 V battery-operated portable power applications. >

Demonstrating the potential of 6-H silicon carbide for power devices

Discusses the first vertical UMOS power MOSFETs ever reported in SiC, shows the highest gain 6H-SiC BJTs (bipolar junction transistors) and thyristors ever reported, and demonstrate the high-temperature operation of these devices. Vertical power MOSFETs fabricated in 6H-SiC with a UMOS design have specific on-resistances as low as 38 m Omega -cm/sup 2/ at a gate bias of +12 V. These devices can have current densities as high as 190 A/cm/sup 2/ (0.32 A/cm of gate periphery) and can dissipate a maximum power density of 5.4 kW/cm/sup 2/. SiC BJTs have been demonstrated up to 400 degrees C. The device structure used a reactive ion etched emitter with sintered Ni contacts to both the emitter and collector, and Al/Ti alloy contacts to the base. Four-layer structures have also been demonstrated in 6H-SiC, with p-n-p-n thyristors showing 100 V operation.

A double-recessed Al/sub 0.24/GaAs/In/sub 0.16/GaAs pseudomorphic HEMT for Ka- and Q-band power applications

A double-recessed 0.2- mu m-gate-length pseudomorphic HEMT (PHEMT) has been demonstrated with 500 mW of output power (833 mW/mm of gate periphery), 6-dB gain, and 35% power-added efficiency (PAE) at 32 GHz. At 44 GHz, the device exhibited 494 mW of output power (823 mW/mm), 4.3-dB gain, and 30% PAE. This level of performance is attributed to excellent MBE material, optimized epitaxial layer design, and the use of individual source vias and of double recess with tight channel dimensions. Excellent 3-in-wafer uniformity was also observed: DC yield was greater than 95% and the interquartile range for all DC parameters was less than 20% of the median value (most are significantly lower). >

High-efficient class F GaAs FET amplifiers operating with very low bias voltages for use in mobile telephones at 1.75 GHz

High-efficiency class F GaAs power FET amplifiers working with a very low drain bias voltage of 3 V, for use in portable telephones, are reported. The transistor used has an optimized gate periphery of 2000 mm and a gate length of 0.7 mu m. Under class F operation with a drain voltage of 3 V, it has demonstrated an output power of 24.5 dBm with 71% of power-added efficiency at the operating frequency of 1.75 GHz. Output harmonic levels lower than -25 dBc have been measured. The results obtained present the state of the art as published for low-bias-voltage, low-power-consumption amplifiers for mobile telephone systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A D-band monolithic fundamental oscillator using InP-based HEMT's

The design, analysis and experimental characteristics of the first fundamental D-band monolithic high-electron-mobility transistor (HEMT) oscillator are reported. The circuit is based on a dual feedback topology and uses 0.1- mu m pseudomorphic double heterojunction InAlAs/In/sub 0.7/Ga/sub 0.3/As HEMTs. It includes on-chip bias circuitry and an integrated E-field probe for direct radiation into the waveguide. An oscillation frequency of 130.7 GHz was measured, and the output power level was -7.0 dBm using HEMTs of small gate periphery (90 mu m). This represents the highest frequency of fundamental signal generation out of monolithic chips using three-terminal devices. >

High-gain W band pseudomorphic InGaAs power HEMTs

The authors have fabricated 0.1- mu m T-gate pseudomorphic (PM) InGaAs power high-electron-mobility transistors (HEMTs) with record power and gain performance at 94 GHz. Devices with 40- mu m gate peripheries achieved 10.6-mW output power with 7.3-dB gain and 14.3% power-added efficiency (PAE). Devices with 160- mu m gate peripheries achieved 62.7-mW output power with 4.0-dB gain and 13.2% PAE. The authors believe the superior performance of these devices is due to the combination of a short 0.1- mu m T-gate, high-quality material, optimized device profile, and the reduction in source inductance due to source vias. >

Design and performance of octave S/C band MMIC T/R modules for multi-function phased arrays

A complex wideband transmit/receive module that achieves performance levels superior to any MMIC module is described. Peak performance within the octave 3.0 to 6.0 GHz band includes a power output of 21 W at S-band and 19 W at C-band, a noise figure of 3.9 to 5.0 dB, 30 to 38 dB of receive gain, 25 to 26 dBm output IP/sub 3/, 40 dB of gain control in 256 steps, dual receive channels with independent amplitude and phase control, and an 8-bit phase shifter with less than 1 degree calibrated RMS phase error. Total GaAs area is 146 mm/sup 2/ with 170 mm of total gate periphery. The module incorporates a compact digital interface, requires only three supply voltages, and utilizes advanced packaging techniques, resulting in a size compatible with a grating lobe free grid spacing. >

Selective Gate Recessing of GaAs/AIGaAs/lnGaAs Pseudomorphic HEMT Structures Using BCl3 Plasmas

ABSTRACTWet chemical gate recessing of GaAs based devices suffers from poor control and uniformity of the recess etch depth. Electrical variability can be particularly severe for heterojunction devices that contain thin highly doped layers. This problem can be addressed by the use of etch stop layers and the appropriate etch chemistry. In this paper, results on the selective plasma etching of GaAs from InGaAs and AIGaAs etch stop layers are presented. Using a BCl3 plasma, GaAs layers were removed from thin lnxGa(1-X)As (0.12&lt;x&lt;0.25) layers with selectivities &gt;1000 to 1 due to the poor volatility of indium chlorides. With the addition of SFe, the etch process becomes selective to AlxGa (1-X)As due to the formation of a non-volatile AlFX layer. By the judicious choice of etch conditions (high pressure and low power resulting in low DC bias and optimal BCl3/SF6 ratio), isotropie etch profiles with minimal substrate damage and GaAs to Al0.25Ga0.75As selectivities &gt;1000 to 1 have been achieved. Using these etch conditions, pseudomorphic HEMT wafers were selectively plasma gate recessed yielding saturated current uniformities across a 3 inch wafer of &lt;±1.0mA/100μm of gate periphery. Device characteristics and uniformities that are dependent upon the material structure and epitaxial layer thickness and dopant uniformities rather than upon the gate recess process are realized.

Design and performance of an octave band 11 watt power amplifier MMIC

The design and performance of a two-stage 3.0 to 6.0 GHz MMIC (monolithic microwave integrated circuit) power amplifier that has established a new standard for power output and bandwidth in MMIC form are reported. The amplifier produces 11 W+or-1 dB from 3.0 to 6.0 GHz, with maximum power outputs of 13.5 W and 10.5 W at S and C radar bands respectively, and a minimum power of 9 W. This benchmark eclipses the best power levels reported for both two-stage (8 W at S-band) and single-stage (10 W at C-band) narrowband MMIC power amplifiers with a continuous bandwidth coverage of 67%. The yield of this two-stage 40 mm gate periphery MMIC, based on 0.5 mu m gate length selective-implant MESFET technology, averaged 43%, with a 57% yield from the best wafer.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Power-bandwidth considerations in the design of MESFET distributed amplifiers

Quantitative procedures are given for the design of MESFET distributed amplifiers using series capacitors in the device gate circuits. It is shown that the choice of series capacitors allows the designer to trade gain for bandwidth while maintaining a given gain-bandwidth product. It is also shown that the input power capability can be increased by the use of series capacitors when the device pinch-off is the power-limiting factor. It is pointed out how the addition of series capacitors makes it possible to increase the gate periphery of an amplifier, which results in an increase in power-bandwidth product. >

Mobility profiling of GaAs power FET's by magnetotransconductance measurements

Mobility profiles of GaAs power MESFET's have been measured using the magnetotransconductance technique. Unlike devices with small gate widths, large periphery power devices exhibit significant parasitic resistance effects, and corrections have to be made. To obtain a realistic mobility profile of the channel, precise measurement of the magnetic field dependence of the transconductance and parasitic resistance is necessary. The technique for obtaining these accurate measurements is detailed. The FET's studied are standard microwave power devices for amplifier circuit applications. Devices having gate peripheries of up to 3.5 mm have been studied, and corrected mobility in the range of 3500-6000 cm2/V . s has been obtained.