Variations In Gate Oxide Thickness Research Articles

Design and investigation of triple metal gate engineering of charge plasma based TFET for biomolecule detection

The current manuscript introduces a dielectric regulated charge plasma based Triple metal Gate Tunnel Field Effect Transistor (CPB-TG-TFET) biological sensor. In which a nano-cavity is introduced below the gate and source electrode to detect the biological molecules like amino acids (AAs), protein, etc. The proposed P + and N + regions are contrived depending upon the electrode’s work function on the device’s silicon body. The effects of metal electrode work function modulation, gate electrode length variation and gate oxide thickness variation are analyzed for improving band-to-band tunneling efficiency at the source- channel transition. The proposed structure shows noticeable sensitivity results for neutral and charged biomolecules. The sensitivity of the neutral biomolecules having higher dielectric constant(Kp) is observed higher; the surface potential sensitivity of the Gelatin (Kp = 14) is estimated as 3.×1010 which is 13% and 35% higher than the sensitivity of Keratin (Kp = 10) and Bacteriophage T7 (Kp = 5) respectively at the cavity length of 30 nm.

Evaluation of statistical variability and parametric sensitivity of non-uniformly doped Junctionless FinFET

Below 22-nm technology node, the random variation has become serious issue during dimensional scaling of the device. In this work, the impact of random discrete dopant fluctuations (RDF), gate oxide thickness variations (OTV), and metal work function variations (WFV) in non-uniformly doped Junctionless FinFET structure has been investigated using three dimensional TCAD simulations on large statistical ensemble. Furthermore, this work explores the sensitivity of the device design parameters. The simulation results when contrasted with uniformly doped Junctionless FinFET structure highlight the advantages of non-uniformly doped channel design.

Investigation and statistical modeling of InAs-based double gate tunnel FETs for RF performance enhancement * * Project supported by the Department of Science and Technology, Government of India under SERB Scheme (No. SERB/F/2660).

In this paper, RF performance analysis of InAs-based double gate (DG) tunnel field effect transistors (TFETs) is investigated in both qualitative and quantitative fashion. This investigation is carried out by varying the geometrical and doping parameters of TFETs to extract various RF parameters, unity gain cut-off frequency (ft), maximum oscillation frequency (fmax), intrinsic gain and admittance (Y) parameters. An asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs. Higher ON-current (ION) of about 0.2 mA and less leakage current (IOFF) of 29 fA is achieved for DG TFET with gate-drain overlap. Due to increase in transconductance (gm), higher ft and intrinsic gain is attained for DG TFET with gate-drain overlap. Higher fmax of 985 GHz is obtained for drain doping of 5 × 1017 cm−3 because of the reduced gate-drain capacitance (Cgd) with DG TFET with gate-drain overlap. In terms of Y-parameters, gate oxide thickness variation offers better performance due to the reduced values of Cgd. A second order numerical polynomial model is generated for all the RF responses as a function of geometrical and doping parameters. The simulation results are compared with this numerical model where the predicted values match with the simulated values.

Analytical modeling of label free biosensor using charge plasma based gate underlap dielectric modulated MOSFET

In this paper charge plasma based dielectric modulated four gated MOSFET (CP-GUDM-MOSFET) has been proposed for the efficacy of label free electrical detection of the biomolecules. To achieve low thermal budgeting, charge-plasma concept is employed using appropriate metal work function electrodes. Extensive simulations have been done using the Sentaurus TCAD to validate the proposed architecture. An analytical modeling has also been done on surface potential and drain current to consolidate the feasibility of the structure. Significant improvements in the on current (ION) and threshold voltage have been observed in presence of the charged biomolecules. The performance of proposed structure is found to be sensitive to gate-oxide thickness variations. High sensitivity of the proposed CP-GUDM-MOSFET based biosensor with low thermal budgeting scheme; simple structure and its compatibility with the existing CMOS processes make it an exciting alternative to the conventional FET-based biosensors.

Charge-Modulated Underlap I-MOS Transistor as a Label-Free Biosensor: A Simulation Study

The possibility of fast label-free detection of biomolecules using electronic devices has resulted in an increased focus on developing such biosensing devices and optimizing their structure for enhanced performance. One of the main factors that determine biosensor's performance is its sensitivity. A high sensitivity in detecting biomolecules is achieved with FET-based biosensors by biasing the device in the subthreshold regime. Recent works have shown the possibility of significantly increased sensitivity in detecting biomolecules using emerging steep subthreshold slope FETs as label-free biosensors. A lower subthreshold swing, achievable with steep subthreshold slope devices, also results in a faster response time for the biosensor. The impact-ionization MOS (I-MOS) transistor can achieve very steep subthreshold slopes as it is turned ON abruptly due to the impact ionization phenomenon. In this paper, we propose an underlap I-MOS (UI-MOS) transistor sensor for the label-free detection of the charged biomolecules. The UI-MOS is a three-terminal device with an underlap in the middle of the gate electrode serving as the location for immobilization by biomolecules. The gate electrode of the UI-MOS offers the advantage of individual addressability of biosensors in a sensor array. The compatibility of the UI-MOS with the CMOS process enables monolithic integration with the measurement circuitry. Using the TCAD simulation, we demonstrate that a biosensor based on the UI-MOS is highly sensitive to the presence of charged biomolecules. The UI-MOS, when operating in the linear regime, also experiences a large threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) shift due to the presence of biomolecules. The performance of UI-MOS is found to be less sensitive to gate-oxide thickness variations, and shows high sensitivity for a range of gate and underlap lengths. The very high sensitivity of the UI-MOS biosensor and its compatibility with the existing CMOS processes make it an exciting alternative to the conventional FET-based biosensors.

Simulation and Analysis of Interface Properties Due to Variation of Gate Oxide Thickness in Au/Al2O3/n-GaSb MOSCAP

Simulation and Analysis of Interface Properties Due to Variation of Gate Oxide Thickness in Au/Al₂O₃/<i>n</i>-GaSb MOSCAP

DG-FINFET-BASED SRAM CONFIGURATIONS FOR INCREASED SEU IMMUNITY

In this paper, we propose a new circuit level hardening techniques that can decrease the sensitivity of Static Random Access Memory (SRAM) cells to radiation induced Single Event Upsets (SEUs). Five different types of 32 nm double gate (DG)-FinFET-based SRAM cells are analyzed. Proposed SRAM cell outperforms over the unhardened SRAM when exposed to radiation. This is primarily due to the modification of the source potential used to reduce the effect of SEU without affecting normal operation. Static Noise Margin (SNM), Read Noise Margin (RNM), Write Noise Margin (WNM) and Power Delay Product (PDP) are the performance metrics computed for each type of SRAM cell. Effect of back gate voltage and back gate oxide thickness variation on device characteristic show detrimental effects on radiation hardened capabilities of a device. Benchmarking is done against DICE latch and it is found that as compared to DICE latch proposed DG-FinFET SRAM has low transistor count, less area, low recovery time and fault tolerance to internal as well as external nodes.

Reverse short channel effects in high- k gated nMOSFETs

Anomalous threshold voltage roll-up behavior, commonly referred as reverse short channel effect (RSCE), has been observed in high- k (HfO 2 on SiON buffer, Al 2O 3 on SiON buffer) gated submicron nMOSFETs, while the SiO 2 or SiON control samples show normal short channel effect (SCE) behavior. The possible causes such as inhomogeneous channel doping profile and gate oxide thickness variation near S/D ends have been ruled out. The results indicate that interface trap density that dependents on channel length is the main cause of the RSCE observed here. In addition, oxide charge also plays a role.

Analog device design for low power mixed mode applications in deep submicron CMOS technology

Analog device design in the deep sub-micron regime is particularly challenging due to conflicting device performance requirements and the circuit requirements in analog applications. It is shown that novel single pocket devices improve the intrinsic analog performance compared to the conventional super steep retrograde devices, within the constraints imposed by circuit requirements. The effect of gate oxide thickness variation on the analog performance of the novel single pocket and conventional super steep retrograde n-channel MOSFETs is also evaluated. It is shown that for constraints on power supply scaling, single pocket structures offer a better option for low-power analog applications.

Electrical testing for process evaluations

MOS LSI process evaluation techniques based on electrical measurements are presented. Important processing parameters, such as gate length, gate oxide thickness, junction depth and channel doping which determine major device characteristics, e.g. threshold voltage and gain factor, are evaluated by electrical measurements, and compared with those measured by optical or in-process monitoring methods. Good agreement between these results indicates the effectiveness of this electrical evaluation technique. According to the analysis, threshold voltage variations across the wafer are primarily due to variations in gate oxide thickness, while anomalous threshold voltage reduction in the short channel region is attributed to MOSFET punch-through.