Gate Oxide n-MOSFET Research Articles

Temperature-Oriented Mobility Measurement and Simulation to Assess Surface Roughness in Ultrathin-Gate-Oxide ($\sim$1 nm) nMOSFETs and Its TEM Evidence

On a 1.27-nm gate-oxide nMOSFET, we make a comprehensive study of SiO2/Si interface roughness by combining temperature-dependent electron mobility measurement, sophisticated mobility simulation, and high-resolution transmission electron microscopy (TEM) measurement. Mobility measurement and simulation adequately extract the correlation length λ and roughness rms height Δ of the sample, taking into account the Coulomb-drag-limited mobilities in the literature. The TEM measurement yields the apparent correlation length λm and roughness rms height Δm. It is found that the following hold: 1) λ ≈ λm for both the Gaussian and exponential models, validating the temperature-oriented extraction process; 2) the extracted Δ (~1.3 A for the Gaussian model and 1.0 A for the exponential one) is close to that (~1.2 A) of Δm, all far less than the conventional values (~3 A) in thick-gate-oxide case; and 3) the TEM 2-D projection correction coefficient Δm/Δ is approximately 1.0, which cannot be elucidated with the current thick-gate-oxide-based knowledge.

Influence of gate voltage on gate-induced drain leakage current in ultra-thin gate oxide and ultra-short channel LDD nMOSFET's

The influence of gate voltage VG on gate induced drain leakage (GIDL) current is studied in LDD nMOSFET with a gate oxide of 1.4nm and a channel length of 100nm. It is found that the split phenomena of ln(Id/(VDG-1.2))-1/(VDG-1.2) curves under different VG values occurs, which are different from the large MOSFET. Through comparing varieties of ln(Id/(VDG-1.2)) of different VG values, the mechanism of this split phenomenon is obtained. This is ascribed to the change of the hole-tunneling part of GIDL current under different VG values. The absolute value of ln(Id/(VDG-1.2)) curve slope decrease with |VG| value decreasing . It is further found that the values of slope c and intercept d of ln(Id/(VDG-1.2)) curves are linear with VG and the slopes of c and d are 3.09 and -0.77, respectively. The values of c and d quantificationally show the influence of VG on the GIDL current in an ultra-thin ultra-short MOSFET. On the basis of these results, a new GIDL current model including VG is proposed.

The impact of gate–image charge on RTS amplitudes in ultra-thin gate oxide n-MOSFETs

An experimental study of RTS (random telegraph signal) noise amplitudes in ultra-thin gate oxide n-MOSFETs biased in sub-threshold and linear regions was conducted. At the same time, a modified model integrating effects of trapped charge and its gate image charge on the carrier number and mobility fluctuations in the conducting channel was presented. Compared with the widely used model, the newly built model fits the experimental RTS noise data of ultra-thin gate oxide n-MOSFETs better than the former one. By employing this model in the extraction of dynamic border trap characteristics by RTS noise means in ultra-thin gate oxide n-MOSFETs, a more accurate result can be expected.

Degradation of Ultra-Thin Gate Oxide NMOSFETs under CVDT and SHE Stresses

Degradation of device under substrate hot-electron (SHE) and constant voltage direct-tunnelling (CVDT) stresses are studied using NMOSFET with 1.4-nm gate oxides. The degradation of device parameters and the degradation of the stress induced leakage current (SILC) under these two stresses are reported. The emphasis of this paper is on SILC and breakdown of ultra-thin-gate-oxide under these two stresses. SILC increases with stress time and several soft breakdown events occur during direct-tunnelling (DT) stress. During SHE stress, SILC firstly decreases with stress time and suddenly jumps to a high level, and no soft breakdown event is observed. For DT injection, the positive hole trapped in the oxide and hole direct-tunnelling play important roles in the breakdown. For SHE injection, it is because injected hot electrons accelerate the formation of defects and these defects formed by hot electrons induce breakdown.

Electrical Measurement of Local Stress and Lateral Diffusion Near Source/Drain Extension Corner of Uniaxially Stressed n-MOSFETs

On a 1.27-nm gate oxide n-MOSFET that undergoes longitudinal stress via a layout technique, subthreshold current is measured as a function of the gate edge to shallow-trench isolation (STI) spacing and is transformed via bandgap shift into the source/drain extension corner stress. The extracted local stress is quantitatively comparable with those of the channel as created by the gate direct tunneling measurement in inversion, the mobility measurement, and the threshold voltage measurement. In addition, its dependencies on the gate edge to STI spacing confirm the validity of the layout technique in controlling the corner or channel stress. The gate edge direct tunneling (EDT) measurement in accumulation straightforwardly leads to the quantified gate- to-source/drain-extension overlap length. Particularly, a retarded diffusion length of 1.1 nm for a stress change of -320 MPa and the resulting strain-induced activation energy both are in satisfactory agreement with those of the process simulation. A physically oriented analytic model is, therefore, reached, expressing the lateral diffusion as a function of the corner stress.

N-MOSFET oxide trap characterization induced by nitridation process using RTS noise analysis

This paper presents oxide trap characterization of nitrided and non-nitrided gate oxide N-MOSFETs using low frequency noise (LFN) measurements. The identification of defects generated by the gate oxide growth and the nitridation process is carried out using random telegraph signal noise analysis. Significant properties of traps induced by the nitridation process are pointed out. Main trap parameters, such as their nature, capture and emission times, cross-sections, energy levels, and position with respect to the Si/SiO 2 interface, are extracted. These results illustrate the potential of noise investigation for oxide characterizations.

The breakdown characteristics of ultra-thin gate oxide n-MOSFET under voltage stress

The characteristics of the TDDB (Time-dependent dielectric breakdown) under the CVS (constant voltage stress) and the gate current model of devices under V-ramp stress were studied in the 1.4nm-thick n-MOSFET. The degradation and failure mechanisms were analyzed. The gate current is produced by the tunneling, the electron surmounting and percolation. During the stress process, the created traps in the oxide not only debase the height of the SiO2 barrier, but also diminish the breadth of the barrier. Every trap engenders a conduction path. These paths enhance the gate current, degrade the device performance and prolong the broken-time of the gate oxide.

Effect of reverse substrate bias on ultra-thin gate oxide n-MOSFET degradation under different stress modes

Degradation of ultra-thin gate oxide n-MOSFET with halo structure is studied under different stress modes with the increase of reverse substrate bias. The variation of device degradation is characterized by monitoring the substrate current during stress. When the gate voltage is smaller than a critical value, the device degradation first decreases and then increases with the increase of reverse substrate voltage; otherwise, the device degradation increases continually. The critical gate voltage can be determined by measuring the substrate current variation with the increase of reverse substrate voltage.

Conduction mechanism of ultra-thin gate oxide n-MOSFET after soft breakdown

The conduction mechanism of ultra-thin gate oxide n-metal-oxide-semiconductor fi eld effect transistor (n-MOSFET) after soft breakdown is studied in this paper. It is found that in a certain range of gate voltage Vg, the gate cur r ent Ig follows the Fowler-Nordheim-like tunneling mechanism, and the experimen tal tunneling barrier b is 0936 eV in average, which is much smal ler t han the interface barrier of Si/SiO2 We think that after soft brea kdown, the electrons existing in the quantization energy levels of the Si/SiO2 interface , not directly tunnel to the oxide conduction band, but tunnel to the oxide defe ct band. b is determined by both the defect band energy level and t he qu antization energy level of the tunneling electrons. With rising experimental tem perature, the tunneling of high energy level electron is also increasing, which reduces b gradually.

On the correlation between radiation-induced oxide- and border-trap effects in the gate-oxide nMOSFET’s

In this study, combined voltage- and frequency-charge pumping techniques were used to investigate the generation and evolution of border-traps in degraded NMOS transistors by using 1.25 MeV 60Co γ-rays. In addition, gate length effects on border-trap charge density were discussed. First result, both border- and oxide-trap reveal two behaviors as function of total dose at low dose rate. Primarily, there is an increase of both trapped charges, followed later by a decrease of their net charge. Second result, border-trap presents a strong dependence on designed transistor channel length. Transistors with longer gate lengths exhibit less important border-trap during irradiation than transistors with smaller gate lengths. This is due to differences in the near-interfacial stress. However, the same effects were observed for oxide-traps. These results show a great correlation between radiation-induced border- and oxide-trap behaviors at low dose rate. Therefore, this similarity strengthens the idea that both border- and oxide-trap could have the same defect ( E ′).

A comprehensive study of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFETs

The mechanisms and characteristics of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFETs are investigated. Both interface trap and oxide charge effects are analyzed. Various drain leakage current components at zero V/sub gs/ such as drain-to source subthreshold leakage, band-to-band tunneling current, and interface trap-induced leakage are taken into account. The trap-assisted drain leakage mechanisms include charge sequential tunneling current, thermionic-field emission current, and Shockley-Read-Hall generation current. The dependence of drain leakage current on supply voltage, temperature, and oxide thickness is characterized. Our result shows that the trap-assisted leakage may become a dominant drain leakage mechanism as supply voltage is reduced. In addition, a strong oxide thickness dependence of drain leakage degradation is observed. In ultra-thin gate oxide (30 /spl Aring/) n-MOSFETs, drain leakage current degradation is attributed mostly to interface trap creation, while in thicker oxide (53 /spl Aring/) devices, the drain leakage current exhibits two-stage degradation, a power law degradation rate in the initial stage due to interface trap generation, followed by an accelerated degradation rate in the second stage caused by oxide charge creation.

Hot-carrier-induced degradation of N/sub 2/O-oxynitrided gate oxide NMOSFETs

Measurement of long term electrical characteristics of N/sub 2/O-oxynitrided gate oxide NMOSFETs revealed that the role of the nitrogen-rich layer as a blocking barrier for molecular hydrogen diffusion is dominant in the reduced device degradation. A two-step model was proposed, in which the release of hydrogen species and their reaction with the trivalent silicon atoms are the main factors for hot-carrier-induced-degradation. Hot carrier immunity of the NMOSFETs was also found to originate partially from the small increase of both the effective barrier height for electron injection and the interface trap creation energy due to the negatively charged nitrogen-rich layer.

Fabrication of n-metal–oxide semiconductor field effect transistor with Ta2O5 gate oxide prepared by plasma enhanced metalorganic chemical vapor deposition

n-metal–oxide semiconductor field effect transistors (MOSFETs) were fabricated with plasma enhanced metalorganic chemical vapor deposited Ta2O5 gate oxide on Czochralski grown Si wafers using localized oxidation of silicon isolation technology by the conventional Si-based process. The Ta2O5 gate oxide n-MOSFETs showed excellent electrical characteristics such as subthreshold swing of 68–74 mV/dec, transconductance of 4 μS/μm for 4 μm gate length, and carrier mobility of 400 cm2/V s at the saturation region. The large Cox of the gate oxide with the high dielectric constant, εr=20–25, allowed the higher drain current of the device. During the whole process of n-MOSFET fabrication, the cross sectional transmission electron microscopy analysis of the Ta2O5/Si interface showed SiO2 interfacial oxide formation of about 35 Å thick. The Ta2O5 gate oxide n-MOSFET showed good performance compared to the high-temperature silicon oxide gate devices and thus has great potential for applications in the electronic devices.

Analysis on gate-oxide thickness dependence of hot-carrier-induced degradation in thin-gate oxide nMOSFET's

The analysis indicates that a thinner gate oxide nMOSFET shows smaller degradation. Mechanisms for the smaller degradation were analyzed using a simple degraded MOSFET model. It was found that the number of the generated interface states is defined uniquely by the amount of peak substrate current, independently from the gate-oxide thickness. The major cause of the smaller degradation in the thinner gate-oxide device is smaller mobility degradation due to the generated interface states. The degraded mobility was measured and formulated. The smaller mobility degradation is explained by the difference between the vertical electric field dependence of the Coulomb scattering term and that of the phonon term under the inversion condition. The effect of a larger channel conductance, due to the larger inversion charges for the thinner gate-oxide device, is the secondary cause for the smaller degradation. >