Gate Oxide Leakage Currents Research Articles

Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current

A circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. PMOS-only sleep transistors and a dual threshold voltage CMOS technology are utilized to place an idle domino logic circuit into a low leakage state. Sleep transistors are added to the dynamic nodes in order to reduce the subthreshold leakage current by strongly turning off all of the high threshold voltage transistors. Similarly, the sleep switches added to the output nodes suppress the voltages across the gate insulating layers of the transistors in the fan-out gates, thereby minimizing the gate tunneling current. The proposed circuit technique lowers the total leakage power by 88 to 97% as compared to the standard dual threshold voltage domino logic circuits. Similarly, a 22 to 44% reduction in the total leakage power is observed as compared to a previously published sleep switch scheme in a 45nm CMOS technology.

Static leakage reduction through simultaneous V/sub t//T/sub ox/ and state assignment

Standby leakage current minimization is a pressing concern for mobile applications that rely on standby modes to extend battery life. In this paper, we propose new leakage current reduction methods in standby mode. First, we propose a combined approach of sleep-state assignment and threshold voltage (V/sub t/) assignment in a dual-V/sub t/ process for subthreshold leakage (I/sub sub/) reduction. Second, for the minimization of gate oxide leakage current (I/sub gate/) which has become comparable to I/sub sub/ in 90-nm technologies, we extend the above method to a combined sleep-state, V/sub t/ and gate oxide thickness (T/sub ox/) assignments approach in a dual-V/sub t/ and dual-T/sub ox/ process to minimize both I/sub sub/ and I/sub gate/. By combining V/sub t/ or V/sub t//T/sub ox/ assignment with sleep-state assignment, leakage current can be dramatically reduced since the circuit is in a known state in standby mode and only certain transistors are responsible for leakage current and need to be considered for high-V/sub t/ or thick-T/sub ox/ assignment. A significant improvement in the leakage/performance tradeoff is therefore achievable using such combined methods. We formulate the optimization problem for simultaneous state/V/sub t/ and state/V/sub t//T/sub ox/ assignments under delay constraints and propose both an exact method for its optimal solution as well as two practical heuristics with reasonable run time. We implemented and tested the proposed methods on a set of synthesized benchmark circuits and show substantial leakage current reduction compared to the previous approaches using only state assignment or V/sub t/ assignment alone.

Analysis of variation in leakage currents of Lanthana thin films

Lanthana (La 2O 3) films were deposited by E-beam evaporation on n-Si(1 0 0). Conduction mechanisms for the as-deposited film have been investigated. In order to study the annealing effect of the as-deposited films on the conduction mechanisms, some films were annealed in an ex situ way at different temperatures with nitrogen or oxygen gas flow for 5 min. From current–voltage measurement of the as-deposited films, extremely low gate oxide leakage currents were observed while some films showed variation in the scale of the currents. It is shown that all the currents of as-deposited films obey the same conduction mechanisms irrelevant of the magnitude of the leakage currents. From the electric field and temperature dependences of the currents of the gate oxide, it is shown that the main conduction mechanisms are the space-charge limited current (SCLC) at low oxide field region and Fowler–Nordheim (F–N) conduction at high oxide field region. It is also shown that conduction mechanisms of the nitrogen annealed films were basically the same as those of the as-deposited films although the magnitude of the conduction current and flat-band voltage ( V FB) are different.

Gate oxide leakage current analysis and reduction for VLSI circuits

In this paper we address the growing issue of gate oxide leakage current (I/sub gate/) at the circuit level. Specifically, we develop a fast approach to analyze the total leakage power of a large circuit block, considering both I/sub gate/ and subthreshold leakage (I/sub sub/). The interaction between I/sub sub/ and I/sub gate/ complicates analysis in arbitrary CMOS topologies and we propose simple and accurate heuristics based on lookup tables to quickly estimate the state-dependent total leakage current for arbitrary circuit topologies. We apply this method to a number of benchmark circuits using a projected 100-nm technology and demonstrate accuracy within 0.09% of SPICE on average with a four order of magnitude speedup. We then make several observations on the impact of I/sub gate/ in designs that are standby power limited, including the role of device ordering within a stack and the differing state dependencies for NOR versus NAND topologies. Based on these observations, we propose the use of pin reordering as a means to reduce I/sub gate/. We find that for technologies with appreciable I/sub gate/, this technique is more effective at reducing total leakage current in standby mode than state assignment, which is often used for I/sub sub/ reduction.

Nonvolatile memory disturbs due to gate and junction leakage currents

We address disturbs due to gate oxide and junction leakage currents in floating gate nonvolatile memories (NVM). The junction leakage is important, because the gate oxide current is proportional to junction current. We find the low gate leakage current to be caused by field ionization (FI) from traps within the gate oxides. Such low gate leakage currents can lead to sufficient charge accumulation to disturb charge in the floating gate. Through detailed simulations and measurements, we have determined the main cause of “write disturb” and “erase disturb” to be FI gate oxide current at low electric fields and Fowler–Nordheim current at high electric fields. Additional currents are due to high-energy electrons from the junction leakage current.

Nitrogen Implantation and In Situ HF Vapor Clean for Deep Submicrometer n-MOSFETs

This work describes a high performance and reliable deep submicrometer n-channel metal oxide semiconductor field effect transistor (n-MOSFET) with ultrathin gate oxide prepared by combining nitrogen gate electrode implantation and native-oxide-free in situ HF vapor preoxidation cleaning. The results herein reveal that the performance and reliability, including the leakage current of the ultrathin gate oxide, charge-to-breakdown, drain current, transconductance, charge pumping current, stress induced leakage current, and hot carrier reliability of n-MOSFETs are all significantly improved. The enhanced reliability and performance are attributed to the native-oxide-free process, smooth interface, and reduced incorporation of As in the gate oxide which results from HF vapor cleaning and nitrogen implantation. © 2001 The Electrochemical Society. All rights reserved.

Does short wavelength lithography process degrade the integrity of thin gate oxide?

This paper presents the results of investigation on integrity of X-ray/E-beam irradiated thin gate oxides. A large increase of gate oxide leakage current is observed after irradiation on thin gate oxide under X-ray/E-beam lithography conditions. This radiation-induced leakage current (RILL) can be removed by a thermal annealing at 400°C and above, without adverse effect to the oxide integrity. In addition, it is found that ionizing exposures do not significantly affect the breakdown and quasi-breakdown characteristics in ultra-thin oxide.

A new extrapolation law for data-retention time-to-failure of nonvolatile memories

In this letter, we demonstrate that the commonly assumed Arrhenius law is inconsistent with extrapolation of data-retention time-to-failure of nonvolatile memories in highly accelerated life-tests. We argue that the retention time, namely log(t/sub H/), varies linearly with temperature T rather than with 1/T as commonly assumed, yielding an important reduction in the extrapolated time-to-failure. Extensive experimental results demonstrate the physical consistency of the new model. In particular, data-retention of EPROM devices and leakage current of interpoly dielectric and gate oxide have been investigated over a wide range of temperatures. Finally, it is shown that our model reconciles seemingly controversial activation energy data from the literature.

Effects of Oxidation Ambient and Low Temperature Post Oxidation Anneal on the Silicon/Oxide Interface Structure and the Electrical Properties of the Thin Gate Oxide

Electrical properties of ultra thin gate oxide in thickness of 4 to 10 nm have been evaluated, manufactured either by wet or dry oxidation process. The relationship between silicon/oxide interfacial structure and the electrical properties was analyzed. In addition, the effect of post oxidation annealing (POA) temperature on improvement of the electrical characteristics of the gate oxide has been evaluated when the temperature was lower than 950°C, the conventional POA temperature. The leakage current of the ultra thin gate oxide was found to increase as the thickness decreased. The accelerated degradation of breakdown characteristics was observed as the thickness decreased below 7 nm. The physical properties of the silicon/oxide interface were found to depend on oxidation ambient and POA temperature. The wet oxidation process resulted in a smoother surface than the dry oxidation process did. The POA treatment further decreased the micro-roughness of the silicon/oxide interface. The electrical properties of the gate oxide were found to be closely related to the micro-roughness of the silicon/oxide interface. Good electrical properties were obtained for the gate oxide manufactured by the wet oxidation process followed by the POA treatment at 850°C.

The effect of native oxide on thin gate oxide integrity

We have studied the effect of native oxide on thin gate oxide integrity. Much improved leakage current of gate oxide can be obtained by in situ desorbing the native oxide using HF-vapor treated and H/sub 2/ baked processes. Furthermore, an extremely sharp interface between oxide and Si is obtained, and good oxide reliability is achieved even under a high current density stress of 11 A/cm/sup 2/ and a large charge injection of 7.9/spl times/10/sup 4/ C/cm/sup 2/. The presence of native oxide will increase the interface roughness, gate oxide leakage current and stress-induced hole traps.

Effects of NH/sub 3/ plasma passivation on N-channel polycrystalline silicon thin-film transistors

The NH/sub 3/-plasma passivation has been performed on polycrystalline silicon (poly-Si) thin-film transistors (TFT's), It is found that the TFT's after the NH/sub 3/-plasma passivation achieve better device performance, including the off-current below 0.1 pA//spl mu/m and the on/off current ratio higher than 10/sup 8/, and also better hot-carrier reliability than the H/sub 2/-plasma devices. Based on optical emission spectroscopy (OES) and secondary ion mass spectroscopy (SIMS) analysis, these improvements were attributed to not only the hydrogen passivation of the defect states, but also the nitrogen pile-up at SiO/sub 2//poly-Si interface and the strong Si-N bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films. Furthermore, the gate-oxide leakage current significantly decreases and the oxide breakdown voltage slightly increases after applying NH/sub 3/-plasma treatment. This novel process is of potential use for the fabrication of TFT/LCD's and TFT/SRAM's.

Novel N2O Plasma Passivation on Polycrystalline Silicon Thin-Film Transistors

AbstractA novel defect passivation process of polycrystalline silicon thin-film transistors (poly-Si TFT's) utilizing nitrous oxide (N2O) plasma was investigated. In terms of the gas flow rate, chamber pressure, and plasma exposure time, the optimum plasma condition has been found to significantly improve the electrical characteristics of poly-Si TFTs. The performance is even better than those passivated with conventional hydrogen plasma. It is believed that the nitrogen radicals from the N2O gas as well as the hydrogen ones from the residual H2O both can diffuse into the gate-oxide/poly-Si interface and the channel poly-Si layer to passivate the defect-states. Furthermore, the gate-oxide leakage current significantly decreases and the oxide breakdown voltage slightly increases after applying N2O-plasma treatment. This novel process is promising for the applications of TFT/liquid crystal displays and TET/static random access memories.

Nonplanar oxidation and reduction of oxide leakage currents at silicon corners by rounding-off oxidation

We report that, based on the curvature radius at the convex corner of a trenched Si surface and electric field intensification, sacrificial thermal oxidation before gate oxide formation is very effective to round off the convex corner. We call it a rounding-off oxidation. From a simple one-dimensional model that considers both stress generation during Si oxidation and Stress relaxation by oxide viscous flow, it is foreseen that oxidation in a diluted oxidizing ambient and/or at a higher oxidation temperature reduces the stress in the oxide films. Experimentally, we report that the rounding-off oxidation with the above condition effectively rounds off the convex Si corner and decreases the thin gate oxide leakage currents and that the addition of a few percent of H 2 O to the dry oxygen rounding,off oxidation ambient is also effective. The relation between the sacrificial rounding-off oxidation and the time-dependent dielectric breakdown of thin gate oxides formed at the convex corner is also shown.