Gate Library Research Articles

Improved Ternary Reversible Logic Synthesis Using Group Theoretic Approach

Quantum computation relies on exploiting quantum mechanical phenomena, and has received significant attention in recent years. Higher-dimensional quantum systems increase the density of encoded information per computing element (e.g., qutrit for three-level system), resulting in less resource overhead. For instance, 63% reduction in the number of qutrits is possible for ternary quantum systems as compared to the corresponding binary systems. The proposed work exploits this fact to synthesize ternary reversible circuits employing a cycle-based technique. The method starts from the ternary reversible specification of a given function in the form of a permutation. The permutation cycles are factored into simpler three-cycles and two-cycles, which are then mapped to ternary reversible gates. Different gate libraries are used to synthesize three-cycles and two-cycles, respectively. A gate decomposition approach is also proposed to synthesize a quantum gate netlist in terms of elementary ternary quantum gates, viz. Muthukrishnan–Stroud gate and shift gate. Synthesis results on benchmark functions indicate that the proposed method results in 27% and 6% improvements in quantum cost and gate count, respectively, over existing works in the literature.

Techniques for fault-tolerant decomposition of a multicontrolled Toffoli gate

Physical implementation of scalable quantum architectures faces an immense challenge in the form of fragile quantum states. To overcome it, quantum architectures with fault tolerance are desirable. These are achieved currently by using a surface code along with a transversal gate set. This indicates the need for decomposition of universal $n$-qubit multicontrolled Toffoli ($n$-MCT) gates using a transversal gate set. Additionally, the transversal non-Clifford phase gate incurs high latency, which makes it an important factor to consider during decomposition. Additionally, the decomposition of a large MCT gate without ancillas presents an additional hurdle. In this paper, we address both of these issues by introducing the $\mathrm{Clifford}+{Z}_{N}$ gate library. We present an ancilla-free decomposition of MCT gates with linear phase depth and quadratic phase count. Furthermore, we provide a technique for decomposition of MCT gates in unit phase depth using the $\mathrm{Clifford}+{Z}_{N}$ library, albeit at the cost of ancillary lines and exponential phase count.

Energy Efficient Lightweight Cryptography Algorithms for IoT Devices

Over few decades, people have been working on providing security solutions, whereas attackers too have been working simultaneously. We present an evaluation of security algorithms, comparing performances and robustness. These comparisons are performed after hardware implementation and use crypt analysis. The targeted devices are wrist watches, RFID tags, IoT devices and others, which don't have a lot of areas (millions of gate equivalent). While performing this, the primary concern has been exploration of an algorithm that can work in these constrained limits. This led to a search for an algorithm that has low hardware footprints, low power consumption and better speed but at the same time implements adequate security. PRESENT has been found to be one such suitable algorithm. It has been also included in the new international standard for light-weight cryptographic methods under ISO/IEC 29192-2:2012 for its straight forward and light design. Our paper reports hardware implementation results of PRESENT, AES, ECDH, DH and RSA cryptography algorithms. We have implemented these algorithms with standard gate library of UMC-90 nm. Each algorithm has its own architecture and hence requires different crypt-analysis techniques like brute force, Pollard's Rho and biclique for “difficulty to break” measurement. It is a measure in term of time and data complexity of efforts required of a cryptographic attack. We have obtained improvement in area and improvement in power for modified PRESENT algorithm as compared to AES. It has also been observed that the proposed PRESENT algorithm has a time complexity of break attack as for 128 bit key length.

A Ternary Decision Diagram (TDD)-Based Synthesis Approach for Ternary Logic Circuits

Ternary reversible logic synthesis has started gaining the attention of researchers in recent years because of its distinct advantages over binary reversible logic synthesis. However, the existing methods for the synthesis of ternary reversible logic circuits are applicable only to smaller benchmarks. The present paper proposes an efficient synthesis approach in this regard using ternary decision diagrams (TDDs). A TDD is first generated for the function that is to be synthesized. Then, using a gate library of ternary reversible gates, each TDD node is mapped to a sequence of ternary reversible gates that are finally merged together to form the required netlist. The ternary gate library consists of ternary reversible gates such as multi-polarity ternary Feynman gate and multi-polarity ternary Toffoli gate. To estimate the quantum cost, we propose a decomposition approach to represent a ternary reversible gate in terms of ternary elementary gates. We have carried out experimental evaluation on two types of benchmarks. The first type consists of binary reversible benchmarks converted into ternary reversible benchmarks using a transformation approach. The second type is based on ternary non-reversible benchmarks. We have reported the results for benchmarks with up to 13 inputs with a longest runtime of 7 min, which compares favourably with the existing works in the literature.

MIL-61 and Eu3+@MIL-61 as Signal Transducers To Construct an Intelligent Boolean Logical Library Based on Visualized Luminescent Metal-Organic Frameworks.

MIL-61 and its postsynthesis product (Eu3+@MIL-61) are employed as signal transducers to construct a series of basic logic gates (NOT, NAND, INHIBIT, and XNOR) on account of their simple synthetic process and fascinating luminescent properties. Also, a two-output combinational logic gate and a cascaded logic gate can be constructed on these two signal transducers by changing the inputs. In this logic gate library system, the fluorescence of MIL-61 (λ395nm) or Eu3+@MIL-61 (λ615nm) is used as outputs with a threshold of 0.5. The advantage of this boolean logical library is that the two signal transducers are readily available and cost effective. In addition, the luminescence change is visible to the naked eye under a UV lamp, which is more convenient in application. More importantly, it presents a new route for the design of a molecular logic gate library based on luminescent metal-organic frameworks. And for further application, we experimentally construct two logic devices (a 4-to-2 encoder and a parity checker) based on Eu3+@MIL-61 to perform nonarithmetic information.

An improved KFDD based reversible circuit synthesis method

Since reversible logic has promising applications in domains like low-power design and quantum computing, it is necessary to efficiently design high-performance reversible logic circuits. In this paper, in order to reduce the number of qubits while achieving low quantum cost, the Kronecker functional decision diagram (KFDD) based reversible circuit synthesis method is improved by using two strategies. One is to generate a locally optimal reversible cascade for each of the KFDD nodes by performing transformations on the function represented by a node and using a gate library consisting of NOT, CNOT, Toffoli gates and mixed-polarity Peres gates. This strategy helps reduce the quantum cost and the number of qubits. The other is to map KFDD nodes to their locally optimal reversible cascades level by level via breadth-first traversal of the KFDD. This strategy reduces the number of qubits by using the circuit line labeled by an input variable of the KFDD as the target line of a reversible gate. Comparison results are presented in tabular and graphical forms. Compared to the existing decision diagram based reversible circuit synthesis methods, the proposed method can reduce both the quantum cost and the number of qubits in many cases. Compared to other state-of-the-art synthesis methods for reversible circuits, the proposed method can achieve much lower quantum cost but still incurs a high number of qubits for many functions. However, it can achieve the minimum number of qubits for a few irreversible functions while achieving much lower quantum cost. In addition, the proposed method is very time efficient.

Towards Silicon Carbide VLSI Circuits for Extreme Environment Applications

A Process Design Kit (PDK) has been developed to realize complex integrated circuits in Silicon Carbide (SiC) bipolar low-power technology. The PDK development process included basic device modeling, and design of gate library and parameterized cells. A transistor–transistor logic (TTL)-based PDK gate library design will also be discussed with delay, power, noise margin, and fan-out as main design criterion to tolerate the threshold voltage shift, beta ( β ) and collector current ( I C ) variation of SiC devices as temperature increases. The PDK-based complex digital ICs design flow based on layout, physical verification, and in-house fabrication process will also be demonstrated. Both combinational and sequential circuits have been designed, such as a 720-device ALU and a 520-device 4 bit counter. All the integrated circuits and devices are fully characterized up to 500 °C. The inverter and a D-type flip-flop (DFF) are characterized as benchmark standard cells. The proposed work is a key step towards SiC-based very large-scale integrated (VLSI) circuits implementation for high-temperature applications.

Building ATMR circuits using approximate library and heuristic approaches

Approximate Triple Modular Redundancy (ATMR), which is the implementation of TMR with approximate versions of the target circuit, has emerged in recent years as an alternative to partial hardware replication where designers can explore reduced area overhead combined with some compromise on fault masking. This work presents a novel approach for implementing approximate TMR that combines the approximate gate library (ApxLib) technique with heuristics. The algorithm initially defines the gates to be approximated using testability and observability measures and then chooses the gate transformation based on the bits difference. Experimental results showed good trade-off between the ATMR schemes efficiency in terms of area and fault masking and the computational effort needed to generate them.

Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies

This paper deals with the analysis of the impact of process variations on the detection of resistive short defects, in the context of a logic-based test. Two types of short defects are considered for our investigation, i.e. resistive short to either ground terminal (GND) or power supply terminal (VDD). For both defect types, simple analytical models are proposed that permit to evaluate the robust detectability range in presence of process variations. These models rely on a pre-characterization of the gate library through Monte-Carlo simulation and permit to evaluate the detectability range of a given defect without performing any fault simulation. These models are applied to perform a comparative analysis of 28 nm Bulk and FDSOI (Fully Depleted Silicon-On-Insulator) technologies, considering both regular-VT and low-VT devices. The influence of operating conditions on defect detectability range is also investigated.

Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates

Reversible logic has 100% fault observability meaning that a fault in any circuit node propagates to the output stage. In other words, reversible circuits are latent-fault-free. Our motivation is to incorporate this unique feature of reversible logic to design CMOS circuits having perfect or 100% Concurrent Error Detection (CED) capability. For this purpose, we propose a new fault preservative reversible gate library called Even Target - Mixed Polarity Multiple Control Toffoli (ET-MPMCT). By using ET-MPMCT, we ensure that the evenness/oddness of applied 1’s at input, is preserved at all levels of a circuit including output level unless there is a faulty node. A single fault always destroys the parity of input at the output. Our design strategy has two steps for a given function: 1) implement the function with our proposed reversible ET-MPMCT gate library; and 2) apply reversible-to-CMOS gate conversion. For the first step, we propose two approaches. For our first approach in step 1, we first need to have a reversible form of the given function if it is irreversible. Then, synthesize the reversible function using Mixed Polarity Multiple Control Toffoli (MPMCT) gate library by conventional reversible logic synthesis techniques. Finally, the synthesized circuit is converted to ET-MPMCT constructed circuit which is fault preservative. Our second approach, is an ESOP - Exclusive Sum of Products - based synthesis approach modified for our proposed fault preservative ET-MPMCT gate library. It does work with both irreversible and reversible functions. We synthesize our circuits with both approaches in step 1 and choose the circuit with lower number of reversible gates to be fed to step 2 of our design strategy. In second step of our design strategy, we convert our fault preservative reversible circuits into their CMOS counterparts. The performance of our designs is compared with other CED schemes in the literature in terms of area, power consumption, delay and detection rate. Simulations are done with Cadence Genus tool using TSMC 40nm technology. Clearly, results are in favor of our proposed techniques.

Resettable and enzyme-free molecular logic devices for the intelligent amplification detection of multiple miRNAs via catalyzed hairpin assembly.

The integration of multi-level DNA logic gates for biological diagnosis is far from being fully realized. In particular, the simplification of logical analysis to implement advanced logic diagnoses is still a critical challenge for DNA computing and bioelectronics. Here, we developed a magnetic bead/DNA system to construct a library of logic gates, enabling the sensing of multiplex target miRNAs. In this assay, the miRNA-catalyzed hairpin assembly (CHA) was successfully applied to construct two/three-input concatenated logic circuits with excellent specificity extended to design a highly sensitive multiplex detection system. Significantly, the CHA-based multiplex detection system can distinguish individual target miRNAs (such as miR-21, miR-155, and miR let-7a) under a logic function control, which presents great applications in the development of rapid and intelligent detection. Another novel feature is that the multiplex detection system can be reset by heating the output system and the magnetic separation of the computing modules. Overall, the proposed logic diagnostics with high amplification efficiency is simple, fast, low-cost, and resettable, and holds great promise in the development of biocomputing, multiparameter sensing, and intelligent disease diagnostics.

Developing an intelligent library gate to detect unauthorized borrowing and to minimize electrical power consumption

Developing an intelligent library gate to detect unauthorized borrowing and to minimize electrical power consumption

Automated logic synthesis for electro-optic logic-based integrated optical computing.

Integrated optical computing attracts increasing interest recently as Moore's law approaches the physical limitation. Among all the approaches of integrated optical computing, directed logic that takes the full advantage of integrated photonics and electronics has received lots of investigation since its first introduction in 2007. Meanwhile, as integrated photonics matures, it has become critical to develop automated methods for synthesizing optical devices for large-scale optical designs. In this paper, we propose a general electro-optic (EO) logic in a higher level to explore its potential in integrated computing. Compared to the directed logic, the EO logic leads to a briefer design with shorter optical paths and fewer components. Then a comprehensive gate library based on EO logic is summarized. At last, an And-Inverter Graphs (AIGs) based automated logic synthesis algorithm is described as an example to implement the EO logic, which offers an instruction for the design automation of high-speed integrated optical computing circuits.

A template-based technique for efficient Clifford+T-based quantum circuit implementation

The near-future possibility of Quantum supremacy, which aspires to establish a set of algorithms running efficiently on a Quantum computer – have significantly fuelled the interest in design and automation of Quantum circuits. Multiple technologies such as Ion-Trap, Nuclear Magnetic Resonance (NMR), have made great progress in recent years towards a practical Quantum circuit implementation. For all these technologies, in order to suppress the inherent computation noise, fault-tolerance is a desirable feature. Fault tolerance is achieved by Quantum error correction codes, such as surface code. Due to the efficient realization of surface codes using Clifford + T gate library of Quantum logic gates, it is now becoming de facto gate library for Quantum circuit implementation. In this paper, we improve two key performance metrics, T − depth and T − count, for Quantum circuit realization using Clifford + T gates. In contrast with the previous approaches, we have incorporated two techniques - 1) restructuring of the gate positions in the designs to make it amenable towards a lower T − depth 2) using Binary Decision Diagrams (BDD) as an intermediate representation for achieving scalability. To validate our proposed optimizations, we have tested a wide spectrum of benchmarks, registering an average improvement of 74% and 21% on T − depth and T − count in compared works.

Design of approximate-TMR using approximate library and heuristic approaches

Approximate Triple Modular Redundancy (ATMR), which is the implementation of TMR with approximate versions of the target circuit, has emerged in recent years as an alternative to partial hardware replication where designers can explore reduced area overhead combined with some compromise on fault masking. This work presents a novel approach for implementing approximate TMR that combines the approximate gate library (ApxLib) technique with heuristics. The algorithm initially defines the gates to be approximated using testability and observability measures and then choose the gate transformation based on the bits difference. Experimental results compare the proposed new approach with another state of the art technique that uses approximate gate libraries with genetic algorithm showing a good trade-off between the ATMR schemes efficiency in terms of area and fault masking and the computational effort needed to generate them.

Shorter Stabilizer Circuits via Bruhat Decomposition and Quantum Circuit Transformations

In this paper, we improve the layered implementation of arbitrary stabilizer circuits introduced by Aaronson and Gottesman in Phys. Rev. A 70 (052328), 2004: to implement a general stabilizer circuit, we reduce their 11-stage computation -H-C-P-C-P-C-H-P-C-P-Cover the gate set consisting of Hadamard, controlled-NOT, and phase gates, into a 7-stage computation of the form -C-CZ-P-H-P-CZ-C-. We show arguments in support of using -CZ- stages over the -C- stages: not only the use of -CZ- stages allows a shorter layered expression, but -CZ- stages are simpler and appear to be easier to implement compared to the -C- stages. Based on this decomposition, we develop a two-qubit gate depth(14n-4) implementation of stabilizer circuits over the gate library {H, P, CNOT}, executable in the Linear Nearest Neighbor (LNN) architecture, improving best previously known depth25n circuit, also executable in the LNN architecture. Our constructions rely on Bruhat decomposition of the symplectic group and on folding arbitrarily long sequences of the form (-P-C-) <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> into a three-stage computation -P-CZ-C-. Our results include the reduction of the 11-stage decomposition -H-C-P-C-PC-H-P-C-P-Cinto a 9-stage decomposition of the form -C-P-C-PH-C-P-C-P-. This reduction is based on the Bruhat decomposition of the symplectic group. This result also implies a new normal form for stabilizer circuits. We show that a circuit in this normal form is optimal in the number of Hadamard gates used. We also show that the normal form has an asymptotically optimal number of parameters.

Quantum Circuit Synthesis Targeting to Improve One-Way Quantum Computation Pattern Cost Metrics

One-way quantum computation (1WQC) is a model of universal quantum computations in which a specific highly entangled state called a cluster state allows for quantum computation by single-qubit measurements. The needed computations in this model are organized as measurement patterns. The traditional approach to obtain a measurement pattern is by translating a quantum circuit that solely consists of CZ and J (α) gates into the corresponding measurement patterns and then performing some optimizations by using techniques proposed for the 1WQC model. However, in these cases, the input of the problem is a quantum circuit, not an arbitrary unitary matrix. Therefore, in this article, we focus on the first phase—that is, decomposing a unitary matrix into CZ and J (α) gates. Two well-known quantum circuit synthesis methods, namely cosine-sine decomposition and quantum Shannon decomposition are considered and then adapted for a library of gates containing CZ and J (α), equipped with optimizations. By exploring the solution space of the combinations of these two methods in a bottom-up approach of dynamic programming, a multiobjective quantum circuit synthesis method is proposed that generates a set of quantum circuits. This approach attempts to simultaneously improve the measurement pattern cost metrics after the translation from this set of quantum circuits.

Reversible circuit synthesis by genetic programming using dynamic gate libraries

We have defined a new method for automatic construction of reversible logic circuits by using the genetic programming approach. The choice of the gate library is 100% dynamic. The algorithm is capable of accepting all possible combinations of the following gate types: NOT TOFFOLI, NOT PERES, NOT CNOT TOFFOLI, NOT CNOT SWAP FREDKIN, NOT CNOT TOFFOLI SWAP FREDKIN, NOT CNOT PERES, NOT CNOT SWAP FREDKIN PERES, NOT CNOT TOFFOLI PERES and NOT CNOT TOFFOLI SWAP FREDKIN PERES. Our method produced near optimum circuits in some cases when a particular subset of gate types was used in the library. Meanwhile, in some cases, optimal circuits were produced due to the heuristic nature of the algorithm. We compared the outcomes of our method with several existing synthesis methods, and it was shown that our algorithm performed relatively well compared to the previous synthesis methods in terms of the output efficiency of the algorithm and execution time as well.

Influence of Body-Biasing, Supply Voltage, and Temperature on the Detection of Resistive Short Defects in FDSOI Technology

This paper presents an in-depth analysis of the impact of body-biasing, supply voltage, and temperature on the detection of resistive short defects in FDSOI technology. Three types of short defects are considered for our investigation, namely resistive short to ground terminal, resistive short to power supply terminal (VDD), and intergate resistive bridging defect. The two implementation options offered by the technology, i.e., low VT (LVT) and regular VT (RVT) devices are also studied. Defect detectability is evaluated in the context of logic test using the concept of critical resistance. The optimal body-biasing, supply voltage, and temperature settings to achieve the maximum defect coverage are determined through HSPICE simulations using a didactic circuit implemented with 28-nm UTBB FDSOI gate library. An analytical analysis is also proposed based on the on-resistance model of P and N networks, which permits to evaluate the value of the critical resistance without performing fault simulations. In addition, this paper quantifies the individual as well as the combined improvements in detection brought by body-biasing, supply voltage, and temperature settings for the different defect types and different implementations.

Automatic Model Generation for Gate-Level Circuit PDES with Reverse Computation

Gate-level circuit simulation is an important step in the design and validation of complex circuits. This step of the process relies on existing libraries for gate specifications. We start with a generic gate model for Rensselaer’s Optimistic Simulation System, a parallel discrete-event simulation framework. This generic model encompasses all functionality needed by optimistic simulation using reverse computation. We then describe a parser system that uses a standardized gate library to create a specific model for simulation. The generated model is composed of several functions, including those needed for an accurate model of timing behavior. To quantify the improvements that an automatically generated model can have over a hand written model, we compare two gate library models: an automatically generated lsi -10 k library model and a previously investigated, handwritten, simplified gtech library model. We conclude that the automatically generated model is a more accurate model of actual hardware. In comparison to previous results, we find that the automatically generated model is able to achieve better optimistic simulation performance when measured against conservative simulation. To test the automatically generated model, we evaluate the performance of a simulation of a full-scale OpenSPARC T2 processor model. This model consists of nearly 6 million LPs. We achieve a peak performance of 1.63 million events per second during a conservative simulation. To understand the relatively weaker performance of optimistic simulation, we investigate hot spots of event activity and visually identify a workload imbalance.