Gate-level Models Research Articles

A Closer Look at the Chaotic Ring Oscillators based TRNG Design

TRNG is an essential component for security applications. A vulnerable TRNG could be exploited to facilitate potential attacks or be related to a reduced key space, and eventually results in a compromised cryptographic system. A digital FIRO-/GARO-based TRNG with high throughput and high entropy rate was introduced by Jovan Dj. Golic (TC’06). However, the fact that periodic oscillation is a main failure of FIRO-/GARO-based TRNGs is noticed in the paper (Markus Dichtl, ePrint’15). We verify this problem and estimate the consequential entropy loss using Lyapunov exponents and the test suite of the NIST SP 800-90B standard. To address the problem of periodic oscillations, we propose several implementation guidelines based on a gate-level model, a design methodology to build a reliable GARO-based TRNG, and an online test to improve the robustness of FIRO-/GARO-based TRNGs. The gate-level implementation guidelines illustrate the causes of periodic oscillations, which are verified by actual implementation and bifurcation diagram. Based on the design methodology, a suitable feedback polynomial can be selected by evaluating the feedback polynomials. The analysis and understanding of periodic oscillation and FIRO-/GARO-based TRNGs are deepened by delay adjustment. A TRNG with the selected feedback polynomial may occasionally enter periodic oscillations, due to active attacks and the delay inconstancy of implementations. This inconstancy might be caused by self-heating, temperature and voltage fluctuation, and the process variation among different silicon chips. Thus, an online test module, as one indispensable component of TRNGs, is proposed to detect periodic oscillations. The detected periodic oscillation can be eliminated by adjusting feedback polynomial or delays to improve the robustness. The online test module is composed of a lightweight and responsive detector with a high detection rate, outperforming the existing detector design and statistical tests. The areas, power consumptions and frequencies are evaluated based on the ASIC implementations of a GARO, the sampling circuit and the online test module. The gate-level implementation guidelines promote the future establishment of the stochastic model of FIRO-/GARO-based TRNGs with a deeper understanding.

In-network generalized trustworthy data collection for event detection in cyber-physical systems.

Sensors in Cyber-Physical Systems (CPS) are typically used to collect various aspects of the region of interest and transmit the data towards upstream nodes for further processing. However, data collection in CPS is often unreliable due to severe resource constraints (e.g., bandwidth and energy), environmental impacts (e.g., equipment faults and noises), and security concerns. Besides, detecting an event through the aggregation in CPS can be intricate and untrustworthy if the sensor's data is not validated during data acquisition, before transmission, and before aggregation. This paper introduces In-network Generalized Trustworthy Data Collection (IGTDC) framework for event detection in CPS. This framework facilitates reliable data for aggregation at the edge of CPS. The main idea of IGTDC is to enable a sensor's module to examine locally whether the event's acquired data is trustworthy before transmitting towards the upstream nodes. It further validates whether the received data can be trusted or not before data aggregation at the sink node. Additionally, IGTDC helps to identify faulty sensors. For reliable event detection, we use collaborative IoT tactics, gate-level modeling with Verilog User Defined Primitive (UDP), and Programmable Logic Device (PLD) to ensure that the event's acquired data is reliable before transmitting towards the upstream nodes. We employ Gray code in gate-level modeling. It helps to ensure that the received data is reliable. Gray code also helps to distinguish a faulty sensor. Through simulation and extensive performance analysis, we demonstrate that the collected data in the IGTDC framework is reliable and can be used in the majority of CPS applications.

Leakage Models for High-Level Power Estimation

Leakage currents are one major concern when designing recent CMOS devices, making design for leakage at all stages of the design process mandatory. Early leakage optimization requires early leakage prediction, and for electronic system level design, this means estimation capabilities at register transfer (RT) level or above. Existing models are very accurate, but slow [transistor level such as Berkeley Simulator (BSIM)], or the slightly faster gate level models (such as the Liberty library), disregard relevant parameters. We present RT level leakage macro models, which are faster than recent gate level models, while preserving the accuracy of the transistor level models to a great extent. An estimation framework is proposed, describing the subthreshold, gate, and junction leakage of recent technology devices. The models are characterized using BSIM compact models and a Monte Carlo process variation description. Each varying BSIM parameter can be described. As an example of use, channel length, oxide thickness, and channel doping are regarded together with the temperature, supply voltage and body voltage. The final macro model needs less than a hundred parameters to capture the leakage behavior of an entire RT component and is still analytically describing the dependence to the process parameters. Compared to SPICE + BSIM, a model prediction is computed up to a hundred times faster for large RT components, and is, depending on the analyzed technology, within 2.1% (for 16-nm LP)–6.8% (for 65-nm bulk) deviation over a wide range of operating conditions and process variation settings.

A T-DIMM ID Based Command Routing Method for the DIMM Tree Architecture

The DIMM tree architecture was proposed to overcome the drawbacks of the traditional DIMM interface methods such as multi-drop bus and point-to-point links. As the DIMM tree architecture has a tree topology, the most important function of the DIMM tree architecture is the command routing function between upper-level and lower-level DIMMs. In order to implement this function, it uses a special type of DIMMs, called tree DIMMs (T-DIMMs). However, because the pre-proposed T-DIMM uses the command routing method based on routing tables, some problems occur such as hardware cost increase due to the routing table, routing table initialization, and limitation in the number of ranks in one T-DIMM. To solve such problems, this paper proposes a command routing method based on a T-DIMM ID without the routing table. The proposed method was modeled with a register transfer model (RTL). The model of the proposed method has 2 ranks per T-DIMM, and doesn't use the routing table for command. This RTL model was synthesized into the gate-level model. The experimental results confirmed that hardware cost of the proposed method is reduced dramatically while its performance is the same, as compared with the previous routing method in the DIMM tree architecture.

Multilevel Ionizing-Induced Transient Fault Simulator

ABSTRACTThis paper presents a multilevel fault simulator for digital circuits. Single and multiple transient phenomena are examined at low level in order to model accurately single/multiple event transients at logic level. Multilevel simulation is used for precision of electrical modeling and the conciseness of the coarse grain gate-level modeling. This simulator handles natural and maliciously induced transient faults, allowing evaluating the robustness of dependable circuits as well as countermeasures against ionizing-induced fault attacks on secure circuits.

Efficient modulo 2n+1 multiply and multiply-add units based on modified Booth encoding

In this work a new efficient modulo 2n+1 modified Booth multiplication algorithm for both operands in the weighted representation is proposed. Furthermore, the same algorithm is extended to realize modulo 2n+1 multiply-add units. The derived partial products are reduced by an inverted end around carry-save adder tree to two operands, which are finally added by a modulo 2n+1 adder. The performance and efficiency of the proposed multipliers are evaluated and compared against the earlier modulo 2n+1 multipliers, based on a single gate level model. Comparisons based on experimental CMOS implementations for both the multiply and multiply-add units are also given. The proposed multipliers yield area and power savings by an average of 15% and 10% respectively, while the corresponding area and power savings of the proposed multiply-add units are 14% and 21% respectively.

POWER-MODES

Innovation cycles have been shortening significantly during the last years. This process puts tremendous pressure on designers of embedded systems for security-or reliability-critical applications. Eventual design problems not detected during design time can lead to lost money, confidentiality, or even loss of life in extreme cases. Therefore it is of vital importance to evaluate a new system for its robustness against intentionally and random induced operational faults. Currently this is generally done using extensive simulation runs using gate-level models or direct measurements on the finished silicon product. These approaches either need a significant amount of time and computational power for these simulations or rely on existing product samples. This article presents a novel system evaluation platform using power emulation and fault injection techniques to provide an additional tool for developers of embedded systems in security-and reliability-critical fields. Faults are emulated using state-of-the-art fault injection methods and a flexible pattern representation approach. The resulting effects of these faults on the power consumption profile are estimated using state-of-the-art power emulation hardware. A modular system augmentation approach provides emulation flexibility similar to fault simulation implementations. The platform enables the efficient evaluation of new hardware or software implementations of critical security or reliability solutions at an early development phase.

MULTES: Multilevel Temporal-Parallel Event-Driven Simulation

Multilevel temporal-parallel event-driven simulation is a new radically different approach to simulation of designs described in Verilog HDL. It is based on a concept of time-parallel simulation applied to gate-level timing simulation. The simulation is performed in two steps: 1) fast reference simulation that runs on a higher, reference-level design model (typically RTL) and saves the design state at predetermined checkpoints; and 2) target simulation, which runs on a lower, gate-level model and distributes the simulation run slices to individual simulators. The paper addresses a number of important issues that make this approach practical: 1) finding initial state for each simulation slice; 2) resolving initial state mismatches; and 3) handling designs with multiple asynchronous clocks. Experimental results performed on industrial designs demonstrate the validity and efficiency of the method in terms of its performance and the debugging efficiency.

Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection

Estimation of soft error sensitivity is crucial in order to devise optimal mitigation solutions that can satisfy reliability requirements with reduced impact on area, performance, and power consumption. In particular, the estimation of Single Event Transient (SET) effects for complex systems that include a microprocessor is challenging, due to the huge potential number of different faults and effects that must be considered, and the delay-dependent nature of SET effects. In this paper, we propose a multilevel FPGA emulation-based fault injection approach for evaluation of SET effects called AMUSE (Autonomous MUltilevel emulation system for Soft Error evaluation). This approach integrates Gate level and Register-Transfer level models of the circuit under test in a FPGA and is able to switch to the appropriate model as needed during emulation. Fault injection is performed at the Gate level, which provides delay accuracy, while fault propagation across clock cycles is performed at the Register-Transfer level for higher performance. Experimental results demonstrate that AMUSE can emulate soft error effects for complex circuits including microprocessors and memories, considering the real delays of an ASIC technology, and support massive fault injection campaigns, in the order of tens of millions of faults within acceptable time.

A bottom-up approach for System-On-Chip reliability

We demonstrate here for the first time that it is possible by a bottom-up approach to build transistor- and gate-level models with enough accuracy to allow direct comparison with experimental degradations at system-level. This work opens new ways to optimize high level digital systems with respect to aging with great accuracy.

Efficient Implementation of a Scalable Encryption Algorithm using FPGA

SEA is designed for software implementations in controllers, smart cards, or processors. In this Paper we proposed a system that investigates its performances in recent field-programmable gate array (FPGA) devices. The present symmetric encryption algorithms result from a tradeoff between implementation cost and resulting performances. The proposed system is applicable where there are limited processing resources with high throughput requirements. For this purpose, we propose a SEA loop Architecture with Behavior model (VHDL) coding. So the number of logic gates required is very less when compared with Gate level model. Because of less number of logic gates, time taken to execute the loop architecture is less. So we are achieving a faster execution time (Frequency in MHZ). The proposed design is parametric in the key and word size, provably secure against linear or differential cryptanalysis. Beyond its low cost performances, a significant advantage of the proposed architecture is its full flexibility for any parameter of the scalable encryption algorithm, taking advantage of generic VHDL coding.

Reversible Logic Synthesis-Oriented Multi-Objective Automatic Design Method Based on Evolutionary Design Techniques

This paper applies evolutionary design techniques to the reversible logic synthesis, and proposes a reversible logic synthesis-oriented multi-objective automatic design method based on evolutionary design techniques. Firstly, build a gate-level array model of reversible logic circuits (RLC) in order to model the synthesis problems as ones of constrained multi-objective optimizations. Then, encode the candidate RLC to a set of binary evolutionary individuals which are solved by the specialized Pareto-optimal multi-objective evolutionary algorithm. In addition, adopt “pre-bit priority” mechanism to repair infeasible individuals and adopt the rule-based local transformation method to simple the redundant RLC. The results of synthesis experiments demonstrate that the proposed method is feasible and effective, and can automatically synthesize the better RLC.

Simulated fault injections and their acceleration in SystemC

SystemC has found a large acceptance for the description of electronic systems. An essential advantage of a SystemC description is the possibility of a built-in compiled-code simulation. Beyond the functional simulation for validation of a hardware design, there are additional requirements for an advanced simulation of faults in order to analyze the system behavior under fault conditions. The article introduces known and novel methods of SystemC-based simulations with fault injections and provides simulation results. Some strategies are shown to accelerate the SystemC simulation by parallel computing. Furthermore, we present gate level and switch level models for an effective simulation in SystemC.

On the Use of Functional Test Generation in Diagnostic Test Generation for Synchronous Sequential Circuits

We study the relationship between diagnostic test generation for a gate-level fault model, which is used for generating diagnostic test sets for manufacturing defects, and functional test generation for a high-level fault model. In general, a functional fault may partially represent some of the effects of one gate-level fault but not another. Generating a test sequence for the functional fault is then likely to detect one gate-level fault but not the other, thus distinguishing the two faults. This relationship points to the ability to use a functional test generation procedure (that targets functional fault detection) as a way of generating diagnostic test sequences for gate-level faults. We use this observation in two ways. The more direct way is to define functional faults that correspond to the differences between pairs of gate-level faults. The second way is to use functional test sequences as diagnostic test sequences without explicitly considering gate-level faults. We support the use of the resulting procedures with experimental results.

The Realization-Independent Testing Based on the Black Box Fault Models

The design complexity of systems on a chip drives the need to reuse legacy or intellectual property cores, whose gate-level implementation details are unavailable. In this paper we consider the realization-independent testing and the impact of circuit realization on the fault coverage. We investigated two fault models (input-output pin pair fault and input-input-output pin triplet fault) that are used by test generation for circuits described at system description level. The test generation on the system-level model is preferable if the efforts and the duration of the test supplement activities are less than the efforts and the duration of the test generation on gate-level model. The test set for the black-box model is larger as compared to the test set for the particular realization of the circuit. However, large test sets for the black-box model can be compacted by analysis not only according to the stuck-at faults, but also according to various defects for the particular realization.

Logic-level mapping of high-level faults

Many high-level fault models have been proposed in the past to perform verification at functional level, however high-level automatic test pattern generators (ATPGs) are still in a prototyping phase, while very efficient logic-level ATPGs are available.On the other side, coverage metrics and functional fault models are used to guide the generation of functional tests achieving high fault coverage in a relatively short time with respect to traditional gate-level ATPGs. However, what is the effectiveness of test sequences generated at functional level with respect to the more traditional gate-level stuck-at fault model?The paper presents an accurate analysis of the correlation between high-level fault models and the gate-level stuck-at fault model and it proposes a strategy to map high-level faults into logic-level faults. Thus, functional verification, based on a high-level fault model, can be performed by exploiting the capability of state of the art logic-level ATPGs. Experimental results highlight the effectiveness of the methodology.

Partitioning sequential circuits on dynamically reconfigurable FPGAs

A fundamental feature of Dynamically Reconfigurable FPGAs (DRFPGAs) is that the logic and interconnect are time-multiplexed. Thus, for a circuit to be implemented on a DRFPGA, it needs to be partitioned such that each subcircuit can be executed at a different time. In this paper, the partitioning of sequential circuits for execution on a DRFPGA is studied. To determine how to correctly partition a sequential circuit and what are the costs in doing so, we propose a new gate-level model that handles time-multiplexed computation. We also introduce an enchanced force directed scheduling (FDS) algorithm to partition sequential circuits that finds a correct partition with low logic and communication costs, under the assumption that maximum performance is desired. We use our algorithm to partition seven large ISCAS'89 sequential benchmark circuits. The experimental results show that the enhanced FDS reduces communication costs by 27.5 percent with only a 1.1 percent increase in the gate cost compared to traditional FDS.

Deterministic Built-in Pattern Generation for Sequential Circuits

We present a new pattern generation approach for deterministic built-in self testing (BIST) of sequential circuits. Our approach is based on precomputed test sequences, and is especially suited to sequential circuits that contain a large number of flip-flops but relatively few controllable primary inputs. Such circuits, often encountered as embedded cores and as filters for digital signal processing, are difficult to test and require long test sequences. We show that statistical encoding of precomputed test sequences can be combined with low-cost pattern decoding to provide deterministic BIST with practical levels of overhead. Optimal Huffman codes and near-optimal Comma codes are especially useful for test set encoding. This approach exploits recent advances in automatic test pattern generation for sequential circuits and, unlike other BIST schemes, does not require access to a gate-level model of the circuit under test. It can be easily automated and integrated with design automation tools. Experimental results for the ISCAS 89 benchmark circuits show that the proposed method provides higher fault coverage than pseudorandom testing with shorter test application time and low to moderate hardware overhead.

Delay fault models for VLSI circuits

State-of-the-art technologies for VLSI circuits give rise to various defect mechanisms that may cause a circuit to fail when operated at its designated speed of operation. Such defects are conventionally modeled by delay faults. In this paper, we review delay fault models used for circuits described at the gate level. The shortcomings of these models in accommodating physical phenomena that determine the worst-case delay of a circuit, and in modeling physical defects, were described in several works. We review methods proposed recently to address these shortcomings at the gate level, and describe a new approach based on a generalized fault model. This model requires that several tests be used for each fault to encompass the conditions leading to the worst-case delay associated with the fault, thus alleviating the need for accurate modeling of these conditions. Functional delay fault models were also proposed to address several of the shortcomings of gate-level models. We review these models and discuss their advantages and disadvantages. Throughout this paper, we also review test generation procedures for delay faults, and present experimental results of these procedures where appropriate.

A graph representation for programmable logic arrays to facilitate testing and logic design

In this paper, we present a new graph model and an associated set of operations for representing programmable logic arrays (PLAs). The signal lines and devices of a PLA are represented as the edges and vertices of a directed graph, respectively. Through this graph model, most realistic PLA faults, including cross-point, stuck-at, break, and bridging faults, can be modeled and classified, and the maximal diagnosis resolution of a PLA can be determined. Moreover, the model can be easily transformed into a gate-level model. Hence, the work of automatic test-pattern generation for a PLA and for other random logic ran be done simultaneously. We also show that this representation can be extended to some logic design techniques such as logic minimization, folding, and decomposition for PLAs. Thus, this graph model can unify the data structure and operations required in PLA design and test.