Gate-level Fault Research Articles

High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors

The paper proposes a novel high-level approach for implementation-independent generation of functional software-based self test programs for processors with RISC architectures. The approach enables fast generation of manufacturing tests with high stuck-at fault coverage. The main concept of the method is based on separate test generation for the control and data parts of the high-level functional units. For the control part, a novel high-level control fault model is introduced whereas for the data part, pseudo-exhaustive test approaches can be applied to keep the independence from the implementation details. For the control parts, a novel high-level fault simulation method is proposed for evaluating the high-level fault coverage. The approach can be used for easy identification of redundant gate-level faults in the control part. The redundant faults can be identified by simple gate-level fault simulation of the generated high-level test when implementation is available. Experimental results of test generation for different units of a RISC processor support the solutions presented in the paper.

On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic Circuits

Selecting the ideal trade-off between reliability improvement and cost (i.e., area, timing and power overhead) associated with a fault tolerant architecture generally requires an extensive Design Space Exploration. In this paper, we present a feasibility study that addresses the problem of selective hardening of arithmetic circuits by considering a duplication/comparison scheme as error detection architecture. Four different selective hardening methods have been investigated and compared: i) a full duplication scheme, ii) a reduced duplication scheme based on a structural susceptibility analysis, iii) a reduced duplication scheme based on the logical weight of the arithmetic circuit outputs and iv) a reduced duplication scheme that uses an approximate version of the arithmetic circuit. Experimental results performed on adder and multiplier case studies demonstrate the interest of using approximate structures in a duplication scheme since they provide much better error detection capability than other selective hardening methods with lower area and power overheads. Note that all experiments have been done without considering the area and power overhead due to the comparators. This may slightly biased the results from a quantitative point of view, although it does not jeopardize the main conclusion about the interest of using approximate structures as duplication scheme. Moreover, validations using a gate-level fault injection campaign have shown that approximate structures offer a better reliability level compared to the other considered duplication scenarios.

Invisible-Scan: A Design-for-Testability Approach for Functional Test Sequences

Functional test sequences can detect defects that are not detected by scan-based tests, but overall, achieve a lower gate-level fault coverage than scan-based tests. Design-for-testability (DFT) approaches for functional test sequences cause the sequences to deviate from functional operation conditions in arbitrary ways over the entire design. This paper introduces the concept of invisible-DFT as a DFT approach for functional test sequences, where the effects of activating the DFT logic are confined to selected logic blocks. This paper develops an invisible-scan approach. Considering a single logic block, the procedure described in this paper inserts scan shift cycles into a functional test sequence while maintaining the same primary input and output sequences for the logic block. This makes the activation of the DFT logic invisible to other logic blocks. The procedure allows a limited number of primary output vectors to be corrected for this purpose. Experimental results are presented to demonstrate the increase in fault coverage that can be achieved by invisible-scan.

RSBST: an Accelerated Automated Software-Based Self-Test Synthesis for Processor Testing

Software-based test (SBST) techniques are increasingly being used for testing of modern processors because of the ease of synthesis using evolutionary approaches, coverage for difficult to test faults, non-intrusive nature, low hardware overhead, etc. However, the test synthesis time required by SBST is high. In this paper, an advanced SBST technique, termed as Rapid SBST (RSBST) is proposed that reduces the overall test synthesis time by reusing the simulation responses of existing test programs of identical observability. The test codes, developed using the evolutionary process, that produce similar fault simulation results are reused for the fault evaluation. We exploit this reusability to enhance the speed of the test synthesis process. The efficacy of the proposed scheme is demonstrated on a 32-bit MIPS processor and on a minimal configuration of 7-stage SPARC V8 Leon3 soft processor. The traditional SBST synthesis requires 122 hours for the MIPS processor and 142 hours for the Leon3 processor to develop test program sets that cover 93.9% and 92.9% of the behavioral-level faults of these processors, respectively. An existing enhanced greedy-cover method, that also detects the hard-to-test faults, improves the coverage towards 96.3% for the MIPS processor and 95.8% for the Leon3 processor, but this slower test development consumes 168 hours and 172 hours, respectively. In the proposed RSBST scheme, the synthesized test codes achieve an adequate fault coverage of 96.1% for the MIPS processor and 95.5% for the Leon3 processor. This accelerated test pattern generation takes 90 hours and 98 hours for these two processors. So it may be concluded that the proposed RSBST technique speeds up the traditional SBST synthesis by a factor of 1.35 while maintaining the fault coverage above 95.5%. To validate the test quality evaluation using behavioral fault models, a strong correlation (94.8%) between the behavioral faults and gate-level faults of MIPS processor is demonstrated and verified for the proposed RSBST scheme. Also, the simulation responses of the test programs synthesized by RSBST scheme consumes only 14.25% of storage space when compared with the storage consumption of the actual simulation used by the existing test code generation methods.

Reliable S-Box Hardware Implementation by Gate-Level Fault Masking Enhancement

With technology scaling, fault tolerance has become more essential for digital circuits. Some solutions, like all types of redundancies, have been proposed to increase the reliability of the systems. In this paper, we present a cost-aware algorithm to enhance the fault tolerance ability of combinational digital circuits. Proposed algorithm improves the circuit logical masking with minimum area overhead based on an improved version of genetic algorithm (GA). Given a set of potential gates that are more sensitive to fault occurrence, we first extract feasible functional redundant, ffr, between the source nodes and the potential gates’ outputs that their improvement on logical masking be more than a pre-defined threshold and hold them in a library, Masking_Lib. Then, we have to find a set of minimum number of potential gates as a target to add appropriate ffr, so that the maximum improvement on logical masking with minimum area overhead is achieved. Since, finding a set of potential gates with their suitable ffrs to meet these objectives is an NP-hard problem, we formulize this, as an optimization problem and solve using GA. We introduce an efficient chromosome representation and an adaptive objective function along with the basic GA operators. Besides, we integrate an assimilation operator with GA in order to enhance its searching ability. Our approach is applied to composite field substitution box implementation (S-box) that forms the core building block of any hardware implementation of the Advanced Encryption Standard algorithm. The simulation and synthesis results have been reported to show the effectiveness of our approach. Through these results, it has been shown that our proposed algorithm provides reliable digital circuits based on different level of logical masking (from 25.58 to 52.15).

Dynamically Determined Preferred Values and a Design-for-Testability Approach for Multiplexer Select Inputs under Functional Test Sequences

Earlier works observed that certain primary inputs have preferred values, which help increase the gate-level fault coverage when they appear in a functional test sequence. This article observes that multiplexers present additional opportunities for increasing the fault coverage of a functional test sequence, which are not captured by preferred primary input values. Because multiplexers are prevalent, their effect on the fault coverage can be significant. A static analysis that is independent of any functional test sequence is performed in this article to identify preferred values for the outputs of multiplexers. This is followed by a dynamic analysis that adjusts the select inputs of the multiplexers for a given functional test sequence to ensure that the preferred values appear on the outputs of the multiplexers more often. The analysis yields design-for-testability logic for the select inputs of the multiplexers that have preferred values. The logic is independent of the functional test sequence, and it allows the fault coverage to be increased when the select inputs are not primary inputs, or when the same select inputs are used for different multiplexers. Experimental results are presented to demonstrate that this approach has a significant effect on the fault coverage of functional test sequences.

Automation of Test Program Synthesis for Processor Post-silicon Validation

Software-based self-testing (SBST) is introduced for at-speed testing of processors, which is difficult with any of the external testing techniques. Evolutionary approaches are used for the automatic synthesis of SBST programs. However, a number of hard-to-detect faults remain unidentified by these autogenerated test programs. Also, these approaches have considered fault models which have low correlation with the gate-level fault models. This paper presents a greed-based strategy, where the instruction sequences that detect the freshly identified faults are preserved throughout the evolutionary process to identify the hard-to-test faults of the processor. Subsequently, the overall coverage is also improved. A selection probability is estimated from the testability properties of the processor components and assigned to every instruction to accelerate the test synthesis. The range of performance and scalability are comprehensively evaluated on a configurable MIPS processor and a full-fledged 7-stage pipeline SPARC V8 Leon3 soft processor using behavioral fault models. The efficacy of our approach was explained by demonstrating the correlation between behavioral faults and gate-level faults of MIPS processor for the proposed scheme. Experimental results show that improved coverages of 96.32% for the MIPS processor and 95.8% for the Leon3 processor are achieved in comparison with the conventional methods, which have about 90% coverage on the average.

Analysis of Reliability for the Gate Level Fault Tolerant Design using Probabilistic Transfer Matrix method

Analysis of Reliability for the Gate Level Fault Tolerant Design using Probabilistic Transfer Matrix method

Clock Sequences for Increasing the Fault Coverage of Functional Test Sequences

A functional test sequence for a design may not be effective as a manufacturing test for a logic block in the design because it achieves a low gate-level fault coverage. This paper describes a procedure for selecting a clock sequence that increases the gate-level fault coverage of a functional test sequence when it is used for testing a subset of logic blocks. The procedure deactivates the clocks to the logic blocks in the subset when a primary input vector has a negative effect on their fault coverage. The procedure is different from earlier test generation and test compaction procedures in that it increases the fault coverage without modifying the functional test sequence. It thus preserves some of the functional characteristics and the test application process for the sequence. Experimental results for benchmark circuits are presented to demonstrate the effectiveness of the procedure.

From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires

Controllable-polarity silicon nanowire transistors (CP-SiNWFETs) are among the promising candidates to complement or even replace the current CMOS technology in the near future. Polarity control is a desirable property that allows the online configuration of the device polarity. CP-SiNWFETs result in smaller and faster logic gates unachievable with conventional CMOS implementations. From a circuit testing point of view, it is unclear if the current CMOS and FinFET fault models are comprehensive enough to model all the defects of CP-SiNWFETs. In this paper, we explore the possible manufacturing defects of this technology through analyzing the fabrication steps and the layout structure of logic gates. Using the obtained defects, we then evaluate their impacts on the performance and the functionality of CP-SiNWFET logic gates. Out of the results, we extend the current fault model to a new a hybrid model, including stuck at p-type and stuck-at n-type, which can be efficiently used to test the logic circuits in this technology. The newly introduced fault model can be utilized to adequately capture the malfunction behavior of CP logic gates in the presence of nanowire break, bridge, and float defects. Moreover, the simulations revealed that the current CMOS test methods are insufficient to cover all faults, i.e., stuck-Open. We proposed an appropriate test method to capture such faults as well.

Functional Test-Sequence Grading at Register-Transfer Level

We propose output deviations as a surrogate metric to grade functional test sequences at the register-transfer level without explicit fault simulation. Experimental results for the open-source Biquad filter core and the Scheduler module of the Illinois Verilog Model show that the deviations metric is computationally efficient and it correlates well with gate-level coverage for stuck-at, transition-delay and bridging faults. Results also show that functional test sequences reordered based on output deviations provide steeper gate-level fault coverage ramp-up compared to other ordering methods.

Concatenation of Functional Test Subsequences for Improved Fault Coverage and Reduced Test Length

Functional test sequences have several advantages over structural tests when they are applied at-speed. A large pool of functional test sequences may be available for a circuit due to the application of a simulation-based design verification process. This paper describes a versatile procedure that uses a pool of functional test sequences as a basis for forming a single compact functional test sequence that achieves the same or higher gate-level fault coverage than the given pool. The procedure extracts test subsequences from the test sequences in the pool and concatenates them to form a single test sequence. It also employs an enhanced static test compaction process aimed at improving the fault coverage in addition to reducing the test sequence length.

A Genetic Algorithm based Two Phase Fault Simulator for Sequential Circuit

Testing has become an important design step now days in digital circuit. A gate level fault simulation environment based on realistic fault models has been presented in this paper. A Genetic Algorithm (GA) is proposed which allows having fault simulation with conditional execution of test vector under 2 phase scheme. By using this approach a random search of test vectors is possible without being caught in a local minima or maxima. The award of fitness to the vector set allows having a selection of test vectors with high fault coverage and with large fault detection scores. Experimental results are provided which shows that the proposed technique can be employed for the detection of faults in a sequential circuit with high fault coverage.

Instruction-Level Impact Analysis of Low-Level Faults in a Modern Microprocessor Controller

We investigate the correlation between low-level faults in the control logic of a modern microprocessor and their instruction-level impact on the execution of typical workload. Such information can prove immensely useful in accurately assessing and prioritizing faults with regards to their criticality, as well as commensurately allocating resources to enhance online testability and error/fault resilience through concurrent error detection/correction methods. To this end, we developed an extensive fault simulation infrastructure which allows injection of stuck-at faults and transient errors of arbitrary starting time and duration, as well as cost-effective simulation and classification of their repercussions into various instruction-level error types. As a test vehicle for our study, we employ a superscalar, dynamically-scheduled, out-of-order, Alpha-like microprocessor, on which we execute SPEC2000 integer benchmarks. Extensive fault injection campaigns in control modules of this microprocessor facilitate valuable observations regarding the distribution of low-level faults into the instruction-level error types that they cause. Experimentation with both Register Transfer (RT-) and Gate-Level faults, as well as with both stuck-at faults and transient errors, confirms the validity and corroborates the utility of these observations.

Sampling + DMR

With technology scaling, manufacture-time and in-field permanent faults are becoming a fundamental problem. Multi-core architectures with spares can tolerate them by detecting and isolating faulty cores, but the required fault detection coverage becomes effectively 100% as the number of permanent faults increases. Dual-modular redundancy(DMR) can provide 100% coverage without assuming device-level fault models, but its overhead is excessive. In this paper, we explore a simple and low-overhead mechanism we call Sampling-DMR: run in DMR mode for a small percentage (1% of the time for example) of each periodic execution window (5 million cycles for example). Although Sampling-DMR can leave some errors undetected, we argue the permanent fault coverage is 100% because it can detect all faults eventually. Sampling-DMR thus introduces a system paradigm of restricting all permanent faults' effects to small finite windows of error occurrence. We prove an ultimate upper bound exists on total missed errors and develop a probabilistic model to analyze the distribution of the number of undetected errors and detection latency. The model is validated using full gate-level fault injection experiments for an actual processor running full application software. Sampling-DMR outperforms conventional techniques in terms of fault coverage, sustains similar detection latency guarantees, and limits energy and performance overheads to less than 2%.

RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences

Functional test sequences are often used in manufacturing testing to target defects that are not detected by structural test. However, they suffer from low defect coverage since they are mostly derived in practice from existing design-verification test sequences. Therefore, there is a need to increase their effectiveness using design-for-testability (DFT) techniques. We present a DFT method that uses the register-transfer level (RTL) output deviations metric to select observation points for an RTL design and a given functional test sequence. Simulation results for six ITC?99 circuits show that the proposed method outperforms two baseline methods for several gate-level coverage metrics, including stuck-at, transition, bridging, and gate-equivalent fault coverage. Moreover, by inserting a small subset of all possible observation points using the proposed method, significant fault coverage increase is obtained for all benchmark circuits.

Test generation at the algorithm-level for gate-level fault coverage

We present a test generation approach that enables to construct functional test patterns at early stages of the design according to the software prototype of the circuit. The presented approach is based on an input–output pin pair and an input–input–output pin triplet fault models. The basic properties of these models are analyzed. Random test generation was implemented on the base of these fault models. ISCAS’85 and ITC’99 benchmark circuits were used for the experiments. The obtained results for the presented fault models were compared with the gate level test generation. The problem of termination of random search is explored and the solution is proposed.

Mixed hierarchical-functional fault models for targeting sequential cores

Current work presents a set of fault models allowing high coverage for sequential cores in systems-on-a-chip. We propose a novel approach combining a hierarchical fault model for functional blocks, a functional fault model for multiplexers and a mixed hierarchical-functional fault model for comparison operators, respectively. The fault models are integrated into a fast high-level decision diagram based test path activation tool. According to the experiments, the proposed method significantly outperforms state-of-the-art test pattern generation tools. The main new contribution of this paper is a formal definition of high-level decision diagram representations and the combination of the three fault models in order to target high gate-level stuck-at fault coverage for sequential cores.

On the Use of Functional Test Generation in Diagnostic Test Generation for Synchronous Sequential Circuits

We study the relationship between diagnostic test generation for a gate-level fault model, which is used for generating diagnostic test sets for manufacturing defects, and functional test generation for a high-level fault model. In general, a functional fault may partially represent some of the effects of one gate-level fault but not another. Generating a test sequence for the functional fault is then likely to detect one gate-level fault but not the other, thus distinguishing the two faults. This relationship points to the ability to use a functional test generation procedure (that targets functional fault detection) as a way of generating diagnostic test sequences for gate-level faults. We use this observation in two ways. The more direct way is to define functional faults that correspond to the differences between pairs of gate-level faults. The second way is to use functional test sequences as diagnostic test sequences without explicitly considering gate-level faults. We support the use of the resulting procedures with experimental results.

Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors

In this paper, we present a satisfiability (SAT)-based framework for automatically generating test programs that target gate-level stuck-at faults in microprocessors. The microarchitectural description of a processor is first translated into a unified register-transfer level (RTL) circuit description, called assignment decision diagram (ADD), for test analysis. Test generation involves extraction of justification/propagation paths in the unified circuit representation from an embedded module's input-output (I/O) ports to primary I/O ports, abstraction of RTL modules in the justification/propagation paths, and translation of these paths into Boolean clauses in conjunctive normal form (CNF). Additional clauses are added that capture precomputed test vectors/responses at the embedded module's I/O ports. An SAT solver is then invoked to find valid paths that justify the precomputed vectors to primary input ports and propagate the good/faulty responses to primary output ports. Since the ADD is derived directly from a microarchitectural description, the generated test sequences correspond to a test program. If a given SAT instance is not satisfiable, then Boolean implications (also known as the unsatisfiable segment) that are responsible for unsatisfiability are efficiently and accurately identified. We show that adding design for testability (DFT) elements is equivalent to modifying these clauses such that the unsatisfiable segment becomes satisfiable. Test generation at the RTL also imposes a large number of initial conditions that need to be satisfied for successful detection of targeted stuck-at faults. We demonstrate that application of the Boolean constraint propagation (BCP) engine in SAT solvers propagates these conditions leading to significant pruning of the sequential search space which in turn leads to a reduction in test generation time. Experimental results demonstrate an 11.1X speedup in test generation time for test generation at the RTL over a state-of-the-art gate-level sequential generator called MIX, at comparable fault coverages. An unsatisifiability-based DFT approach at the RTL improves this fault coverage to near 100% and incurs very low area overhead (3.1%). Unlike previous approaches that either generate a test program consisting of random instruction sequences or assume the existence of test program templates, the proposed approach constructs test programs in a deterministic fashion from the microarchitectural description of a processor