Abstract
Testing has become an important design step now days in digital circuit. A gate level fault simulation environment based on realistic fault models has been presented in this paper. A Genetic Algorithm (GA) is proposed which allows having fault simulation with conditional execution of test vector under 2 phase scheme. By using this approach a random search of test vectors is possible without being caught in a local minima or maxima. The award of fitness to the vector set allows having a selection of test vectors with high fault coverage and with large fault detection scores. Experimental results are provided which shows that the proposed technique can be employed for the detection of faults in a sequential circuit with high fault coverage.
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