Gate-level Description Research Articles

Quantum Circuit Reconstruction from Power Side-Channel Attacks on Quantum Computer Controllers

The interest in quantum computing has grown rapidly in recent years, and with it grows the importance of securing quantum circuits. A novel type of threat to quantum circuits that dedicated attackers could launch are power trace attacks. To address this threat, this paper presents first formalization and demonstration of using power traces to unlock and steal quantum circuit secrets. With access to power traces, attackers can recover information about the control pulses sent to quantum computers. From the control pulses, the gate level description of the circuits, and eventually the secret algorithms can be reverse engineered. This work demonstrates how and what information could be recovered. This work uses algebraic reconstruction from power traces to realize two new types of single trace attacks: per-channel and total power attacks. The former attack relies on per-channel measurements to perform a brute-force attack to reconstruct the quantum circuits. The latter attack performs a single-trace attack using Mixed-Integer Linear Programming optimization. Through the use of algebraic reconstruction, this work demonstrates that quantum circuit secrets can be stolen with high accuracy. Evaluation on 32 real benchmark quantum circuits shows that our technique is highly effective at reconstructing quantum circuits. The findings not only show the veracity of the potential attacks, but also the need to develop new means to protect quantum circuits from power trace attacks. Throughout this work real control pulse information from real quantum computers is used to demonstrate potential attacks based on simulation of collection of power traces.

Hardware Trojan Detection based on Testability Measures in Gate Level Netlists using Machine Learning

Modern integrated circuit design manufacturing involves outsourcing intellectual property to third-party vendors to cut down on overall cost. Since there is a partial surrender of control, these third-party vendors may introduce malicious circuit commonly known as Hardware Trojan into the system in such a way that it goes undetected by the end-users’ default security measures. Therefore, to mitigate the threat of functionality change caused by the Trojan, a technique is proposed based on the testability measures in gate level netlists using Machine Learning. The proposed technique detects the presence of Trojan from the gate-level description of nodes using controllability and observability values. Various Machine Learning models are implemented to classify the nodes as Trojan infected and non-infected. The efficiency of linear discriminant analysis obtains an accuracy of 92.85 %, precision of 99.9 %, recall of 80%, and F1 score of 88.8% with a latency of around 0.9 ms.

CoCEC: An Automatic Combinational Circuit Equivalence Checker Based on the Interactive Theorem Prover

Checking the equivalence of two Boolean functions, or combinational circuits modeled as Boolean functions, is often desired when reliable and correct hardware components are required. The most common approaches to equivalence checking are based on simulation and model checking, which are constrained due to the popular memory and state explosion problems. Furthermore, such tools are often not user-friendly, thereby making it tedious to check the equivalence of large formulas or circuits. An alternative is to use mathematical tools, called interactive theorem provers, to prove the equivalence of two circuits; however, this requires human effort and expertise to write multiple output functions and carry out interactive proof of their equivalence. In this paper, we (1) define two simple, one formal and the other informal, gate-level hardware description languages, (2) design and develop a formal automatic combinational circuit equivalence checker (CoCEC) tool, and (3) test and evaluate our tool. The tool CoCEC is based on human-assisted theorem prover Coq, yet it checks the equivalence of circuit descriptions purely automatically through a human-friendly user interface. It either returns a machine-readable proof (term) of circuits’ equivalence or a counterexample of their inequality. The interface enables users to enter or load two circuit descriptions written in an easy and natural style. It automatically proves, in few seconds, the equivalence of circuits with as many as 45 variables (3.5 × 10 13 states). CoCEC has a mathematical foundation, and it is reliable, quick, and easy to use. The tool is intended to be used by digital logic circuit designers, logicians, students, and faculty during the digital logic design course.

Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model

Dynamic power estimation is essential in designing VLSI circuits where many parameters are involved but the only circuit parameter that is related to the circuit operation is the nodes’ toggle rate. This paper discusses a deterministic and fast method to estimate the dynamic power consumption for CMOS combinational logic circuits using gate-level descriptions based on the Logic Pictures concept to obtain the circuit nodes’ toggle rate. The delay model for the logic gates is the real-delay model. To validate the results, the method is applied to several circuits and compared against exhaustive, as well as Monte Carlo, simulations. The proposed technique was shown to save up to 96% processing time compared to exhaustive simulation.

Certificate-based encoding of gate level description for secure transmission

Modern system-on-chip design strongly depends on secure exchange of intellectual properties among various authorities. Since it involves large amount of data, the conventional message encryption techniques need improvised use. We propose a novel obfuscation technique for synthesised digital circuits that facilitates secure transmission. It does not need traditional cryptographic data encryption of the whole circuit, and thus requires significantly less time compared to RSA-based encryption. The encoding/decoding of the circuit is guided by a certificate generated specially for the circuit itself. The encoded description hides the functionality of the original circuit. The inbuilt integrity checking at the receiver enables in identifying any intentional modification. We propose two distinct approaches for certificate generation that allow a greater trade-off between the volume of data and the protection. Experimental results show that the proposed technique can withstand a variety of attacks from intruders.

Resolution of Diagnosis Based on Transition Faults

The conventional detection conditions for transition faults do not predict fault effects that may be created when transition faults are activated and/or propagated by pulses (or hazards). For this, detection conditions that take hazards into consideration need to be used. However, since the occurrence of pulses cannot be predicted accurately based on a gate-level circuit description, the transition fault model becomes more susceptible to pattern-dependent effects, where errors on observed outputs that are predicted by the fault model may not appear in a circuit-under-diagnosis. This paper considers the implications of these pattern-dependent effects on the resolution of fault diagnosis based on transition faults.

FPGA-based switch-level fault emulation using module-based dynamic partial reconfiguration

In order to design a fault tolerant digital system, it is necessary to understand its behavior with the presence of faults in early design stage. Fault simulation is a process to purposely inject faults into a software circuit model and observe its faulty behavior. However, such simulation’s runtime tends to grow exponentially when test circuit becomes large. FPGA-based fault emulation, which is fault simulation implemented in FPGA, is an efficient way to accelerate fault simulation process. This paper introduces a novel FPGA-based switch-level fault emulation system utilizing module-based dynamic partial reconfiguration. In this approach, faults are modeled at switch-level and mapped to gate-level description for efficient FPGA implementation. The circuit under test is partitioned using unbalanced partitioning structure so that faults are injected only in a small sub-circuit. Using module-based dynamic partial reconfiguration, faulty circuit partition can be downloaded to FPGA without erasing the fault-free part of the circuit. The resulting system’s runtime increases linearly with circuit size, therefore indicating high efficiency of this system when emulating large and complex circuits.

THE IMPROVEMENT OF TEST INDEPENDENCE FROM CIRCUIT REALIZATION

We consider the possibilities of supplementing or expanding a particular realization test having a purpose to enhance test quality for detecting various defects. We suggest complementing the existing test suites of the IP core with sensitive adjacent patterns. Then the suitable test patterns for the synthesized gate level implementation have to be selected on the base of the fault simulation. Our experiments prove that such a complement would enhance the test quality for any synthesized IP core gate level description. We believe that the practice of sensitive adjacent patterns is a very cheap way to adopt test patterns for the re-synthesized gate level description of IP core, because the fault simulation is not so critical task as a test generation.

Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation

This paper presents a novel fault simulation environment in VHDL. By writing a library of special fault simulation models, a traditional model is transformed into a new model that performs fault simulation using a VHDL simulation engine. Pre- and post-synthesis VHDL models are used for an effective implementation, better performance and to minimize the overhead associated with VHDL simulation. Models are written such that an automatic switching mechanism selects gate level descriptions for originating faults and behavioral descriptions for propagating them.

Universal and robust testing of stuck-open faults in Reed–Muller canonical CMOS circuits

Testability of stuck-open faults in CMOS implementation of the Reed–Muller canonical (RMC) form of a switching function is considered in this paper. It is shown that a slightly modified RMC expression can be used to synthesize an easily testable combinational logic circuit. The design admits a universal test sequence TS that robustly detects all single stuck-open faults in the CMOS transistors. For an n-variable switching function, TS consists of only (2n + 8) vectors and can be generated by a simple test pattern generator. All single stuck-at faults in the corresponding gate-level description of the network are also detected by the same test set.

ATM over SDH: design of a STM-16c transceiver using GaAs technology

This article describes an ATM transceiver implementation with add/drop function over Synchronous Digital Hierarchy (SDH) able to handle STM-16c (OC-48c) signals. The design has been developed using Vitesse HGaAs-IV technology using Direct Coupled FET Logic (DCFL) standard cells and obtaining, in this way, a logic gate level description which could be easily exportable to any technology.

Generation of High Power Test Vector Set for Combinational VLSI Circuits

Burn-in is a well-known technique that helps to accelerate failure mechanisms to surface out latent defects, which are not activated during normal testing of the VLSI devices. The devices are kept at a specified high temperature, for a specified period, in static or dynamic conditions. Since this method is cumbersome, an alternate method based on complementary metal oxide semiconductor (CMOS) signal switching for VLSI devices is considered. The majority of power dissipation in CMOS circuitry is due to the switching current associated with charging and discharging of load capacitances. Hence, if the test vectors can be so designed that maximum activity is conjured, the stress on the device can be maximised. In this paper, a new algorithm for generation of these power vectors from a gate-level description of the circuit is presented. The method has been applied to different circuits and the results compared.

Defect-oriented mixed-level fault simulation in digital systems

A new method for mixed level defect-oriented fault simulation of Digital Systems represented with Decision Diagrams (DD) is proposed. We suppose that a register transfer level (RTL) information along with gate-level descriptions for RTL blocks are available. Decision diagrams (DDs) are exploited as a uniform model for describing circuits on both levels. The physical defects in the system are mapped to the logic level and are simulated on the mixed gate- and RT levels. The approach proposed allows to increase the accuracy of test quality estimation, and to reduce simulation cost in comparison to traditional gate-level fault simulation methods.

A hierarchical test generation approach for large controllers

A testing approach targeted at Hardware Description Language (HDL)-based specifications of complex control devices is proposed. For such architectures, gate-level test pattern generators require insertion of scan paths to enable the flat gate-level representations to be efficiently handled. In contrast, we present a testing methodology based on the hierarchical finite state machine model. Our approach allows the generation of compact test sets with very high stuck-at fault coverages, without any design-for-testability logic other than hardware reset. This method can be used any time the functional information is available together with the gate-level structural description. High fault coverages are achieved with smaller test lengths and execution times with respect to state-of-the-art gate-level test pattern generators.

Exploiting timed transition relations in sequential cycle-based simulation of embedded systems

Embedded systems are increasingly important. They are currently implemented as a mix of hardware and software components, and they must satisfy strict real-time constraints. To achieve this, several counting devices are usually introduced in the system. As a result, embedded systems exhibit extremely deep state spaces, and standard analysis methods may be excessively expensive. More specifically, there is interest in very long sequences of states without 'observable' or 'relevant' external effects. A new symbolic approach to represent them is described which is based on timed transition relations. The methodology may be used for a variety of applications, from synthesis to verification and to simulation. The paper concentrates on simulation. In this field, starting from a register-transfer or gate-level description, a binary-decision-diagram-based model is extracted automatically which is capable of jumping in time, avoiding the simulation of internal events. Finally, a set of experimental results obtained using a state-of-the-art simulator is discussed.

Extraction of functional regularity in datapath circuits

Datapath circuits exhibit a very high degree of regularity, which is exploited by designers to generate layouts with a high density and performance as well as to reduce the overall design effort. Regularity in a datapath circuit manifests itself at functional, structural, and topological levels. Functional regularity of a circuit implies the existence of logically equivalent subcircuits-a common feature of datapath circuits. We present a new and comprehensive approach to extract functional regularity for datapath circuits from their high-level or gate-level descriptions. The key step is the generation of a large set of templates, where a template is a subcircuit with multiple instances in the circuit. Two novel template generation algorithms are presented-one for templates with a tree structure, and the other for a special class of multioutput templates, called single-principal-output-graph (SPOG) templates, where all outputs of a template are in the transitive fanin of a particular output. The set of templates generated is shown to be complete under a few simplifying, yet practical, assumptions, which is key in obtaining a desirable cover of the circuit using templates. We present a few extensions to our regularity extraction approach to demonstrate its generality; these extensions include hierarchical representation of regularity and generation of instances of user-specified templates. We show that the generation of the above two classes of templates results in good covers for datapath circuits with a regular bus structure, including several International Conference on Computer-Aided Design benchmark circuits. The regularity extracted from these circuits can be used to easily understand their structure. We have successfully used our approach to identify bit slices of very large datapath circuits from general-purpose microprocessors.

Functional test generation for delay faults in combinational circuits

We propose a functional fault model for delay faults in combinational circuits and describe a functional test generation procedure based on this model. The proposed method is most suitable when a gate-level description of the circuit-under-test, necessary for employing existing gate-level delay fault test generators, is not available or does not accurately describe the circuit. It is also suitable for generating tests in early design stages of a circuit, before a gate-level implementation is selected. In addition, it can potentially be employed to supplement conventional test generators for gate-level circuits to reduce the cost of handling large numbers of paths. A parameter called Δ is used to control the number of funtional faults targeted and thus the number of tests generated. If Δ is unlimited, the functional test set detects every robustly testable path delay fault in any gate-level implementation of the given ciruit. An appropriate subset of tests can be selected once the implentation is known. The test sets generated for various values of Δ are fault simulated on gate-level realizations to demonstrate their effectiveness. The experiments indicate that functional test sets may be able to identify functions whose realizations have low path delay fault coverage.

A Practical Methodology for the Formal Verification of RISC Processors

In this paper a practical methodology for formally verifying RISC cores is presented. Using a hierarchical model which reflects the abstraction levels used by designers of real RISC processors, proofs between neighboring levels are performed for simplifying the verification process. The proofs are performed by showing that each instruction is executed correctly by the pipelined machine with respect to the semantics of the instruction set architecture. During this proof, temporal abstractions are used to find correspondences between the various levels of abstractions. Additionally, lower level implementational details such as, multiphased clocks and gate level descriptions of the final implementation, are accounted for. The overall correctness proof is managed in two complementary steps, namely, {\it pipeline\ data} and {\it pipeline\ control} correctness. In the former, we show that the cumulative effect of pipeline suboperations yields the data semantics of architecture instructions. While in the latter, we are concerned with interferences (conflicts) between the different instructions and suboperations in the pipeline. We have developed a set of parametrized proof scripts which highly automate the different proof tasks. In addition, the pipeline control proof is constructive, in the sense that the conditions under which the pipeline conflicts occur are automatically generated and explicitly stated thus aiding the user in its removal. All developed specifications and proof scripts are kept general, so that the methodology could be applied for a wide range of RISC cores (e.g., those used in embedded systems). In this paper, the described formalization and proof strategies are illustrated via the DLX RISC processor.

Design of Chip Set for CDMA Mobile Station

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMS, and the chip size is 10 mm x 10.1 mm which is fabricated using a 0.8 μm 2 metal CMOS technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32k (2k x 16 bit) RAM, and 240k (10kx24 bit) ROM. The die size is 8.7 mmx8.3 mm and the chip is fabricated using 0.8 μm CMOS technology.

Universal TSC module and its application to the design of TSC circuits

In this paper, we present a universal totally self-checking (TSC) module and show that it can be used as a TSC AND, OR, NAND or NOR gate by performing appropriate routing at its input and/or output. We use the two-rail code to encode the signals and consider the multiple unidirectional stuck-at-fault model. We study the utility of such TSC modules in obtaining the TSC realization of a given circuit from its gate level description. We show that it is possible to obtain the SFS realization of a given circuit by replacing each gate in it with its respective TSC version. We discuss the properties that a circuit must have in order to obtain its TSC realization in this manner using the TSC gate.