Gate Leakage Current Research Articles

Single-crystalline High-κ GdOCl dielectric for two-dimensional field-effect transistors

Two-dimensional (2D) dielectrics, integrated with high-mobility semiconductors, show great promise to overcome the scaling limits in miniaturized integrated circuits. However, the 2D dielectrics explored to date still face the challenges of low crystallinity, diminished dielectric constant, and the lack of effective synthesis methods. Here, we report the controllable synthesis of ultra-thin gadolinium oxychloride (GdOCl) nanosheets via a chloride hydrate-assisted chemical vapor deposition (CVD) method. The resultant GdOCl nanosheets display good dielectric properties, including a high dielectric constant (high-κ) of 15.3, robust breakdown field strengths (Ebd) exceeding 9.9 MV/cm, and minimal gate leakage currents of approximately 10−6 A/cm2. The top-gated GdOCl/MoS2 field-effect transistors (FETs) exhibit commendable switch characteristics, a negligible hysteresis of ~5 mV and a subthreshold swing down to 67.9 mV dec−1. The GdOCl/MoS2 FETs can also be employed to construct functional logic gates. Our study underscores the significant potential of the 2D GdOCl dielectric for innovative high-speed operated nanoelectronic devices.

Threshold Voltage Recovery Time Measurement Technique Post VTH Instability in Normally-Off p-Gate GaN High Electron Mobility Transistors

In this study, we propose a simple measurement technique to quantitatively measure the time taken by threshold voltage of normally-off p-GaN AlGaN/GaN HEMTs to recover from a nominal operational gate stress-induced instability. The proposed technique eliminates the requirement to perform a full transfer characteristic sweep post-stress, thereby eliminating the measurement-induced instability effect, often colluding precise recovery time measurement. The rate of recovery and extracted recovery times hold significance in empirically correlating the location of traps in the p-GaN or AlGaN barrier region causing VTH instability. The gate of the HEMT is stressed at nominal operational drive voltages 1.5 V, 2 V, and 4 V for various time intervals from 500 μs to 100 s, and the time taken for the drain current to recover to prestress levels measured at near-threshold voltage (~1.1 VTH) is measured as the threshold voltage recovery time. With increasing gate stress voltages, 2DEG gets trapped at relatively deeper trap energy levels at the AlGaN/GaN interface requiring more emission time during the process of recovery, mandating larger recovery times. At higher stress voltage of 4 V, the Schottky gate leakage current is high enough enabling injected holes to cross the AlGaN barrier and counter-compensate for the deeply trapped 2DEG, requiring relatively the same recovery times as lower stress voltages where the gate leakage is negligibly small. With increasing stress time, the amount of 2DEG trapped increases, requiring more recovery time to de-trap and beyond a certain time, saturation of the trap density occurs causing the recovery time to plateau.

On-demand performance optimization of AlGaN/GaN high electron mobility transistors using stoichiometric variation of dielectric alloy AlxTayO

The current research investigates the potential advantages of optimally combining wide bandgap Al2O3 with high dielectric constant (high-κ) Ta2O5 for gate dielectric applications. Various compositions of 10 nm AlxTayO oxide films are grown on the Al0.3Ga0.7N/GaN heterostructure by co-sputtering Al and Ta metals, followed by thermal oxidation at 500 °C. The average root-mean-square roughness of the grown oxide films is ∼1.2–1.4 nm compared to 0.4 nm for as-deposited metal. X-ray photoelectron spectroscopy and transmission electron microscopyconfirm the formation and thickness of the grown oxide films. The bandgap (Eg) of the oxide films calculated from O1s electron energy loss spectra show a linear increase from 4.85 eV for pure Ta2O5 to 6.4 eV for pure Al2O3. The dielectric constant (εox) calculated from capacitance–voltage (CG−VG) measurements decreases linearly from 25.7 for Ta2O5 to 7.9 for Al2O3. The interface trap density (Dit) is estimated from the frequency dispersion of capacitance–voltage (CG−VG) characteristics. The DC and radio frequency (RF) characteristics of AlxTayO/Al0.3Ga0.7N/GaN high electron mobility transistor (HEMT) devices are measured and compared with the Schottky HEMT devices (without any gate oxide). Compared to Schottky HEMT devices, AlxTayO/Al0.3Ga0.7N/GaN HEMT devices show superior DC characteristics, which helps us achieve maximum RF output power. Furthermore, the OFF-state measurements show that the AlxTayO/Al0.3Ga0.7N/GaN HEMT devices can sustain higher source-to-drain voltages, from a minimum of 88 V on pure Ta2O5 metal-oxide-semiconductor (MOS)-HEMTs to a maximum of 138 V on pure Al2O3 MOS-HEMTs before the dielectric breakdown happens, compared to a 57 V breakdown voltage on Schottky HEMT devices. An oxide variation of AlxTayO, with Al composition ratio of 0.34, shows an exceptional ION/IOFF ratio of 4 × 1011, a gate leakage current of 8 × 10−12 A/mm, a near-ideal subthreshold slope of 63.8 mV/dec, and the unity current gain frequency (fT) of 25.6 GHz.

Characteristics of silicon-based polycrystalline diamond MOSFETs prepared by three-step growth method

Hydrogen-terminated diamond (H-diamond) metal oxide field effect transistors (MOSFETs) were successfully fabricated on polished first-grown and unpolished secondary-grown silicon-based polycrystalline diamond films. The devices have a gate length of 8 μm, while an Al2O3 dielectric bilayer was deposited at 200 °C and 100 °C using atomic layer deposition (ALD). Compared to the first-grown diamond films with a root-mean-square roughness (Rq) of 257 nm, the films after polishing and subsequent second growth change the diamond growth mode, resulting in a mixed surface morphology characterized by faceted and step-bunching structures with a roughness (Rq) of 16.6 nm, and also leading to a decrease in grain boundary density and polishing-induced defects. Device analysis demonstrates that these changes result in an increase in the on/off ratio from 102 to 107 at a gate leakage current of 10−7 mA/mm. Meanwhile, although polished first-grown diamond films have atomic-level smoothness, the devices channels on unpolished secondary-grown diamond films show higher carrier concentration and mobility. The improvement in device performance indicates that the three-step growth method provides a new opportunity for the application of large-sized silicon-based polycrystalline diamond films in electronic devices.

High-temperature operation of Al2O3/Ga2O3 bi-layer gate stack GaN MOS-HEMT up to 450 °C with suppressed gate leakage

Abstract In this work, we report the reduced gate leakage current by using aluminum oxide (Al2O3) and gallium oxide (Ga2O3) as a bi-layer gate stack for GaN MOS-HEMT on a silicon substrate up to 450 °C. The bi-layer gate stack MOS-HEMTs suppressed the gate leakage by more than four orders of magnitude compared to only Al2O3-based GaN MOS-HEMT at 450 °C. The low gate leakage current is attributed to the reduced oxygen vacancies present in the Ga2O3 layer, which effectively impede the conduction path of the Poole-Frenkel emission at high temperatures, thereby enhancing the overall performance of GaN HEMTs.

Improved DC and RF Characteristics of GaN-Based Double-Channel HEMTs by Ultra-Thin AlN Back Barrier Layer.

In order to improve the off-state and breakdown characteristics of double-channel GaN HEMTs, an ultra-thin barrier layer was chosen as the second barrier layer. The strongly polarized and ultra-thin AlN sub-barrier and the InAlN sub-barrier are great candidates. In this article, the two epitaxial structures, AlGaN/GaN/AlN/GaN (sub-AlN) HEMTs and AlGaN/GaN/InAlN/GaN (sub-InAlN) HEMTs, were compared to select a more suitable sub-barrier layer. Through TEM images of the InAlN barrier layer, the segregation of In components can be seen, which decreases the mobility of the second channel. Thus, the sub-AlN HEMTs have a higher output current density and transconductance than those of the sub-InAlN HEMTs. Because the high-quality AlN barrier layer shields the gate leakage current, a 294 V breakdown voltage was achieved by the sub-AlN HEMTs, which is higher than the 121 V of the sub-InAlN HEMTs. The current gain cut-off frequency (fT) and maximum oscillation frequency (fmax) of the sub-AlN HEMTs are higher than that of the sub-InAlN HEMTs from low to high bias voltage. The power-added efficiency (PAE) and output power density (Pout) of the sub-AlN HEMTs are 57% and 11.3 W/mm at 3.6 GHz and 50 V of drain voltage (Vd), respectively. For the sub-InAlN HEMTs, the PAE and Pout are 41.4% and 8.69 W/mm, because of the worse drain lag ratio. Thus, the Pout of the sub-AlN HEMTs is higher than that of the sub-InAlN HEMTs.

Nonresonant Terahertz Detector Based on Improved N‐Polar AlGaN/GaN Plasma Wave High‐Electron‐Mobility Transistors

The THz photoresponse of four different structures of N‐ and Ga‐polar AlGaN/GaN plasma wave high‐electron‐mobility transistors (HEMTs) has been comparatively investigated. Based on these results, an improved N‐polar plasma wave HEMT detector is proposed: an AlGaN cap layer is introduced in the standard N‐polar HEMT, so as to obtain a lower gate leakage current, thus improving the operating characteristics of plasma wave HEMT. The results show that the responsivity of the improved N‐polar HEMT obtains a significant improvement and as the Al component of AlGaN cap layer increases, the noise equivalent power of the improved N‐polar HEMT has also been optimized.

Single-crystalline metal-oxide dielectrics for top-gate 2D transistors.

Two-dimensional (2D) structures composed of atomically thin materials with high carrier mobility have been studied as candidates for future transistors1-4. However, owing to the unavailability of suitable high-quality dielectrics, 2D field-effect transistors (FETs) cannot attain the full theoretical potential and advantages despite their superior physical and electrical properties3,5,6. Here we demonstrate the fabrication of atomically thin single-crystalline Al2O3 (c-Al2O3) as a high-quality top-gate dielectric in 2D FETs. By using intercalative oxidation techniques, a stable, stoichiometric and atomically thin c-Al2O3 layer with a thickness of 1.25 nm is formed on the single-crystalline Al surface at room temperature. Owing to the favourable crystalline structure and well-defined interfaces, the gate leakage current, interface state density and dielectric strength of c-Al2O3 meet the International Roadmap for Devices and Systems requirements3,5,7. Through a one-step transfer process consisting of the source, drain, dielectric materials and gate, we achieve top-gate MoS2 FETs characterized by a steep subthreshold swing of 61 mV dec-1, high on/off current ratio of 108 and very small hysteresis of 10 mV. This technique and material demonstrate the possibility of producing high-quality single-crystalline oxides suitable for integration into fully scalable advanced 2D FETs, including negative capacitance transistors and spin transistors.

WSe2 Negative Capacitance Field-Effect Transistor for Biosensing Applications.

Field-effect transistor (FET) biosensors based on two-dimensional (2D) materials are highly sought after for their high sensitivity, label-free detection, fast response, and ease of on-chip integration. However, the subthreshold swing (SS) of FETs is constrained by the Boltzmann limit and cannot fall below 60 mV/dec, hindering sensor sensitivity enhancement. Additionally, the gate-leakage current of 2D material biosensors in liquid environments significantly increases, adversely affecting the detection accuracy and stability. Based on the principle of negative capacitance, this paper presents for the first time a two-dimensional material WSe2 negative capacitance field-effect transistor (NCFET) with a minimum subthreshold swing of 56 mV/dec in aqueous solution. The NCFET shows a significantly improved biosensor function. The pH detection sensitivity of the NCFET biosensor reaches 994 pH-1, nearly an order of magnitude higher than that of the traditional two-dimensional WSe2 FET biosensor. The Al2O3/HfZrO (HZO) bilayer dielectric in the NCFET not only contributes to negative capacitance characteristics in solution but also significantly reduces the leakage in solution. Utilizing an enzyme catalysis method, the WSe2 NCFET biosensor demonstrates a specific detection of glucose molecules, achieving a high sensitivity of 4800 A/A in a 5 mM glucose solution and a low detection limit (10-9 M). Further experiments also exhibit the ability of the biosensor to detect glucose in sweat.

Thermal stability of TiN gate electrode for 4H-SiC MOSFETs and integrated circuits

In this research, the thermal stability of single-stage amplifiers based on a 4H-SiC MOSFET with a TiN gate electrode was investigated. The results show that after 100 h aging at 400 °C in N2 ambient, the amplifier maintained good performance with stable voltage gain. The thermal stability of the amplifier is attributed to the stability of Ni/Nb/4H-SiC source/drain ohmic contact, implanted load resistor, and MOS structure with the TiN gate electrode. The results obtained from the 4H-SiC MOS structure show that the interface trap density at the SiO2/SiC decreases during the aging process. While the gate leakage current of the capacitor based on the Al gate electrode increases, it remains stable in structures with TiN gate electrodes after 100 h aging. The results obtained in this study indicate that TiN is promising for the gate electrode of 4H-SiC MOSFETs for high-temperature applications.

Prediction of IGBT Gate Oxide Layer's Performance Degradation Based on MultiScaleFormer Network.

Insulated gate bipolar transistors (IGBTs) are widely used in power electronic devices, and their health prediction problems have attracted much attention in the field of power electronic equipment health management. The performance degradation of IGBT gate oxide is one of the most important failure modes. In order to analyze this failure mechanism and the ease of implementation of a monitoring circuit, the gate leakage current of IGBTs was selected as the fault precursor parameter for the degradation of their gate oxide performance, and feature selection and fusion were carried out by using time domain characteristic analysis, grayscale correlation, Mahalanobis distance, Kalman filter, and other methods. Thus, a health indicator was obtained to characterize the degradation of IGBT performance, which was used to indicate the degree of aging of the IGBT gate oxide layer. In this paper, we propose an improved degradation prediction model called MultiScaleFormer, inspired by advanced design ideas of the iTransformer network architecture, combined with the health parameters of IGBTs to construct a degradation prediction model for the IGBT gate oxide layer. MultiScaleFormer showed the highest fitting accuracy compared with the Long Short-Term Memory (LSTM), Convolutional Neural Network (CNN), Support Vector Regression (SVR), Gaussian Process Regression (GPR), CNN-LSTM, and Transformer models in our experiment. The mean absolute error (MAE) of the MultiScaleFormer prediction was as low as 0.0087. Extraction of the health indicator and the construction and verification of the degradation prediction model were carried out on the dataset released by the NASA-Ames Laboratory. These results demonstrate the feasibility of the gate leakage current as a fault precursor parameter for IGBT gate oxide failure, and the feasibility and accuracy of the MultiScaleFormer prediction model for IGBT performance degradation.

Reduction of interface defects in gate-recessed GaN HEMTs by neutral beam etching

This study investigates and compares the impact of different etching techniques on the fabrication of GaN high electron mobility transistors (HEMTs) between the inductively coupled plasma reactive ion etching (ICP-RIE) and the neutral beam etching (NBE) for the gate recess. By conducting direct current analysis, it was found that devices manufactured using the NBE exhibited superior electrical performance as compared with those produced using the ICP-RIE. These enhanced electrical characteristics include a transconductance of up to 100.4 mS/mm, a threshold voltage (Vth) of −2.3 V, an on/off current ratio of 1.1 × 109, a subthreshold swing (S.S.) of 99.63 mV/dec, and a remarkably low gate leakage current. Additionally, we noted varying degrees of hysteresis in the I–V characteristics were related to process disparities possibly leading to interface defects. Multi-frequency capacitance-voltage (C–V) measurements were used to identify the interface defects at the oxide/AlGaN interface of the gate. The results revealed that devices fabricated using the NBE exhibited a lower interface defect density as compared with those fabricated using the ICP-RIE, thereby elucidating the reduced hysteresis observed in the I–V characteristics. These findings indicated the significant advantages of the NBE process in the fabrication of GaN HEMTs.

Design optimization of wide-gate swing E-mode GaN HEMTs with junction barrier Schottky gate

To increase the gate swing, a GaN-based high-electron-mobility transistor with a junction barrier Schottky gate (JBS-HEMT) was proposed. Compared to conventional p-GaN Schottky gate HEMTs (Conv-HEMT), the high electric field at the surface is transferred to the pn junction inside the body, and the extended depletion region of the pn junction shields the surface Schottky contact interface for the JBS-HEMT. After fitting the model to the reported device, the proposed JBS-HEMT was simulated and optimized using the Sentaurus TCAD tool. The simulation results of the optimized JBS-HEMT demonstrate a high gate breakdown voltage (17.6 V), which is 158.5% higher than the gate breakdown voltage of the Conv-HEMT (11.1 V) and a lower gate leakage current of six orders of magnitude than the Conv-HEMT at the gate-to-source voltage of 10 V. The proposed JBS-HEMT exhibits a positive threshold voltage (1.68 V) and excellent threshold voltage stability, and the maximum threshold voltage drift of the JBS-HEMT (+0.237 V) is smaller than that of the Conv-HEMT (−0.714 V) under gate stress conditions. The peak transconductance of the JBS-HEMT (186 mS mm−1) at athe drain-to-source voltage of 10 V showed almost no reduction compared to the Conv-HEMT (189 mS mm−1), which solves the problem of decreased transconductance capability of the reported GaN HEMT with a p-n junction gate (PNJ-HEMT). It was confirmed that the JBS-HEMT has excellent gate stability and potential for power electronics applications.

Reduced trap state density in AlGaN/GaN HEMTs with low-temperature CVD-grown BN gate dielectric

In this Letter, low-temperature (400 °C) chemical vapor deposition-grown boron nitride (BN) was investigated as the gate dielectric for AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MISHEMTs) on a Si substrate. Comprehensive characterizations using x-ray photoelectron spectroscopy, reflection electron energy loss spectroscopy, atomic force microscope, high-resolution transmission electron microscopy, and time-of-flight secondary ion mass spectrometry were conducted to analyze the deposited BN dielectric. Compared with conventional Schottky-gate HEMTs, the MISHEMTs exhibited significantly enhanced performance with 3 orders of magnitude lower reverse gate leakage current, a lower off-state current of 1 × 10−7 mA/mm, a higher on/off current ratio of 108, and lower on-resistance of 5.40 Ω mm. The frequency-dependent conductance measurement was performed to analyze the BN/HEMT interface, unveiling a low interface trap state density (Dit) on the order of 5 × 1011–6 × 1011 cm−2 eV−1. This work shows the effectiveness of low-temperature BN dielectrics and their potential for advancing GaN MISHEMTs toward high-performance power and RF electronics applications.

Effect of hydrogen poisoning on p-gate AlGaN/GaN HEMTs

In this work, we investigate the degradation behavior and mechanism of p-gate AlGaN/GaN high-electron mobility transistors (HEMTs) for the first time under hydrogen (H2) atmosphere. The experimental results reveal significant decrease in drain-to-source current, negative drift in threshold voltage, increase in off-state gate leakage current, and deterioration of subthreshold swing in the p-gate AlGaN/GaN HEMT after H2 treatment. The degradation of the electrical parameters is considered to hydrogen poisoning phenomenon. Through secondary ion mass spectrometry and variable temperature photoluminescence spectroscopy, we observe the increase in hydrogen concentration in the p-GaN layer and the formation of electrically inactive Mg–H complexes after H2 treatment. As results, the effective hole concentration decreases and the trap density of the device increases, which are confirmed by Hall effect measurement and low-frequency noise analysis, respectively. The detrimental effect of hydrogen on p-gate AlGaN/GaN HEMTs can be attributed primarily to the compensation of Mg doping and the generation of defects.

Effect of tensile and compressive strain on the gate leakage current and inverse piezoelectric effect in AlGaN/GaN HEMT devices

The influence of external strain on the gate leakage current of AlGaN/GaN high-electron-mobility transistors was studied. The magnitude of the leakage current increased by 39% under 0.1% tensile strain but decreased by 23% under −0.1% compressive strain. The leakage current obeyed the Poole–Frenkel conduction mechanism, demonstrating a decrease/increase in the barrier height for electron emission from the trap state into the continuum dislocation state. Furthermore, the magnitude of critical reverse stressing voltage for the onset of degradation induced by the inverse piezoelectric effect became lower/higher under tensile/compressive strain compared with that of the initial state, which was attributed to the modification of the total stress in the film. In addition, using the transient current method, it was established that the detrapping time constant for the traps in the AlGaN barrier increased as a result of the tensile strain, which is ascribed to movement of the dislocation level away from the conduction band.

Current-collapse suppression and leakage-current decrease in AlGaN/GaN HEMT by sputter-TaN gate-dielectric layer

In this paper, we explore the electrical characteristics of high-electron-mobility transistors (HEMTs) using a TaN/AlGaN/GaN metal insulating semiconductor (MIS) structure. The high-resistance tantalum nitride (TaN) film prepared by magnetron sputtering as the gate dielectric layer of the device achieved an effective reduction of electronic states at the TaN/AlGaN interface, and reducing the gate leakage current of the MIS HEMT, its performance was enhanced. The HEMT exhibited a low gate leakage current of 2.15 × 10−7 mA/mm and a breakdown voltage of 1180 V. Furthermore, the MIS HEMT displayed exceptional operational stability during dynamic tests, with dynamic resistance remaining only 1.39 times even under 400 V stress.

Mobility Extraction Using Improved Resistance Partitioning Methodology for Normally-OFF Fully Vertical GaN Trench MOSFETs

In this work, fully vertical GaN trench MOSFETs were fabricated and characterized to evaluate their electrical performances. Transistors show a normally-OFF behavior with a high ION/IOFF (~109) ratio and a significantly small gate leakage current (10−11 A/mm). Thanks to an improved resistance partitioning method, the resistances of the trench bottom and trench channel were extracted accurately by taking into account different charging conditions. This methodology enabled an estimation of the effective channel and bottom mobility of 11.1 cm2/V·s and 15.1 cm2/V·s, respectively.

Effect of rapid thermal annealing on DC performance of Mg0.30Zn0.70O/Cd0.15Zn0.85O MOSHFET

This study focuses on a cost-effective method for fabrication of a metal oxide semiconductor-heterostructure field effect transistor (MOSHFET) based on MgZnO/CdZnO (MCO) using dual ion beam sputtering (DIBS), in contrast to the more expensive epitaxial growth system. The MOSHFETs developed in this research exhibit notable characteristics, such as a substantial two-dimensional electron gas (2DEG) transconductance (∼2.6 mS), a high ION/IOFF response ratio in the order of 108, and minimal gate leakage current. Furthermore, we explore the impact of rapid thermal annealing (RTA) on the drain current at various temperatures (600 °C and 800 °C). The results indicate a fourfold improvement in drain current compared to unannealed conditions, primarily attributed to reduced contact resistance and no degradation in term of MgZnO/CdZnO structure. Additionally, an analysis of post-RTA treatment under a nitrogen (N2) atmosphere on gate leakage current is presented. The investigation spans temperatures ranging from 400 °C to 800 °C, revealing that above 600 °C (gate leakage at 400 °C–600 °C is around ∼10−9 A), gate leakage in HFET is augmented by one order of magnitude (∼10−8 A) due to a phase change in the dielectric. These findings underscore the feasibility of DIBS-grown MCO MOSHFETs as an economical solution for the mass production of switching devices and sensors.

Reducing Off-State and Leakage Currents by Dielectric Permittivity-Graded Stacked Gate Oxides on Trigate FinFETs: A TCAD Study.

Since its invention in the 1960s, one of the most significant evolutions of metal-oxide semiconductor field effect transistors (MOSFETs) would be the 3D version that makes the semiconducting channel vertically wrapped by conformal gate electrodes, also recognized as FinFET. During recent decades, the width of fin (Wfin) and the neighboring gate oxide width (tox) in FinFETs has shrunk from about 150 nm to a few nanometers. However, both widths seem to have been leveling off in recent years, owing to the limitation of lithography precision. Here, we show that by adapting the Penn model and Maxwell-Garnett mixing formula for a dielectric constant (κ) calculation for nanolaminate structures, FinFETs with two- and three-stage κ-graded stacked combinations of gate dielectrics with SiO2, Si3N4, Al2O3, HfO2, La2O3, and TiO2 perform better against the same structures with their single-layer dielectrics counterparts. Based on this, FinFETs simulated with κ-graded gate oxides achieved an off-state drain current (IOFF) reduced down to 6.45 × 10-15 A for the Al2O3: TiO2 combination and a gate leakage current (IG) reaching down to 2.04 × 10-11 A for the Al2O3: HfO2: La2O3 combination. While our findings push the individual dielectric laminates to the sub 1 nm limit, the effects of dielectric permittivity matching and κ-grading for gate oxides remain to have the potential to shed light on the next generation of nanoelectronics for higher integration and lower power consumption opportunities.