Gate Layer Research Articles

Ultra-thin Atomic Layer Deposited HfO2: Tailoring Dielectric Thickness for Low-Operating Voltage Thin-Film Transistors

To achieve low-power consumption and high performance in TFTs, it is crucial to reduce the thickness of the dielectric gate layer while maintaining a defect-free structure and high dielectric properties. This study explores the effects of varying HfO2 layer thickness on TFT performance. X-ray photoelectron spectroscopy analysis indicates a decrease in oxygen defects as the film thickness increases. The morphological and topological properties of the films were characterized using grazing incidence small and wide-angle X-ray scattering and atomic force microscopy. Impedance spectroscopy was utilized to analyze the dielectric properties, showing that the 10 nm HfO2 film exhibited a low leakage current density of 13 nA cm−2 at 1 V and a permittivity of 5.98. The fabricated ZnO TFT with a 10 nm HfO2 gate dielectric layer operated at an ultra-low voltage of -1.59 V, achieving a high current on/off ratio exceeding 106. These findings highlight the importance of controlling dielectric layer thickness for the development of high-performance TFTs and their potential for low-power microelectronic applications.

Impact of Interfacial Proton Accumulation on Protonation in a Brownmillerite Oxide

AbstractElectrochemical protonation provides ways to control physical properties and even explore unprecedented phases of solid‐state materials. While how proton accumulation changes materials’ properties is investigated, how protonation of solids can be controlled and promoted remains an enigmatic puzzle. In the work reported here, the influence of electrochemical proton injection duration (tVg) is investigated on the protonation of SrCoO2.5 (SCO) films in electric‐field‐effect transistor structures with gate layers of the proton‐conducting electrolyte Nafion. The proton concentration accumulated in SCO films varies depending on the duration of the proton injection. When protons are injected in a relatively short tVg (≤ 600 s), the hydrogen concentration accumulated in SCO film increases with increasing tVg, reaching the maximum proton concentration of ≈1.9 per formula unit of SCO for the tVg = 600 s case. On the other hand, when tVg is longer than 900 s, the proton concentration decreases with tVg, implying the occurrence of counterreactions that extract protons from protonated SCO and oxidize the channel. These observations indicate that protons accumulated at the Nafion/SCO interface play a role in the protonation of SCO films and that suppressing the interfacial proton accumulation is the key to maximizing the proton concentration accumulated in SCO films.

Epitaxial growth of quasi-2D van der Waals ferromagnets on crystalline substrates

Intrinsic magnetism in van der Waals materials has instigated interest in exploring magnetism in the 2D limit for potential applications in spintronics and also in understanding novel control of 2D magnetism via variation of layer thickness, gate tunability and magnetoelectric effects. The chromium telluride (CrxTey) family is an interesting subsection of ferromagnetic materials with highTCvalues, also presenting diverse stoichiometry arising from self-intercalation of Cr. Apart from the layered CrTe2system, the other non-layered CrxTeycompounds also offer exceptional magnetic properties, and a novel growth technique to grow thin films of these non-layered compounds offers exciting possibilities for ultra-thin spin-based electronics and magnetic sensors. In this work, we discuss the role of crystalline substrates in chemical vapor deposition growth of non-layered 2D ferromagnets, where the crystal symmetry of the substrate as well as the misfit and strain are the key players governing the growth mechanism of ultra-thin Cr5Te8, a non-layered ferromagnet. The magnetic studies of the as-grown Cr5Te8reveal the signatures of co-existing soft and hard ferromagnetic phases, which makes this system an intriguing system to search for emergent topological phases, such as magnetic skyrmions.

Fully Scalable Randomized Benchmarking Without Motion Reversal

We introduce , a protocol that streamlines traditional RB by using circuits consisting almost entirely of independent identically distributed (IID) layers of gates. BiRB reliably and efficiently extracts the average error rate of a Clifford gate set by sending tensor-product eigenstates of random Pauli operators through random circuits with IID layers. Unlike existing RB methods, BiRB does not use motion reversal circuits—i.e., circuits that implement the identity (or a Pauli) operator—which simplifies both the method and the theory proving its reliability. Furthermore, this simplicity enables scaling BiRB to many more qubits than the most widely used RB methods. Published by the American Physical Society 2024

Exploring Neuromorphic Computing with Double-Gate Floating Device Based on Van Der Waals Heterostructures

Neuromorphic devices represent a frontier in technological development, aiming to emulate the intricate parallel functionalities inherent to the human brain [1, 2]. Traditional computing models, such as Von Neumann architecture, grapple with limitations in parallel processing, prompting the exploration of neuromorphic computing to integrate memory and processing efficiently. Our research presents the double gate floating device based on Vander Waals heterostructure (DG-VH-FET), employing molybdenum disulfide (MoS2), hexagonal boron nitride (h-BN), and graphene (Gr) as key components. These devices, based on 2D materials, enable independent modulation of channel doping through electrostatic means [3].In this study, we initially assessed the fundamental characteristics of the floating gate, including transfer characteristics, output characteristics, retention, and endurance. By applying constant drain-to-source voltages (VDS) while introducing variations in the back gate voltage (VBG) sweeping range, the memory window of the transfer characteristics changes. Conversely, maintaining a constant VBG and VDS while varying the top gate voltage (VTG) solely results in a shift in the threshold voltage of the memory window. This is attributed to the crucial role of VBG in charge trapping in the floating gate layer, with the influence of VTG on charge trapping being negligible due to the screening effect of MoS2 [4]. Moreover, by using VTG and VBG this study shows that DG-VH-FET could have potential applications in exploring and understanding various neurological effects, thereby bridging the gap between electronics and biology. Figure 1

Error-corrected Hadamard gate simulated at the circuit level

We simulate the logical Hadamard gate in the surface code under a circuit-level noise model, compiling it to a physical circuit on square-grid connectivity hardware. Our paper is the first to do this for a logical unitary gate on a quantum error-correction code. We consider two proposals, both via patch-deformation: one that applies a transversal Hadamard gate (i.e. a domain wall through time) to interchange the logical X and Z strings, and another that applies a domain wall through space to achieve this interchange. We explain in detail why they perform the logical Hadamard gate by tracking how the stabilisers and the logical operators are transformed in each quantum error-correction round. We optimise the physical circuits and evaluate their logical failure probabilities, which we find to be comparable to those of a quantum memory experiment for the same number of quantum error-correction rounds. We present syndrome-extraction circuits that maintain the same effective distance under circuit-level noise as under phenomenological noise. We also explain how a SWAP-quantum error-correction round (required to return the patch to its initial position) can be compiled to only four two-qubit gate layers. This can be applied to more general scenarios and, as a byproduct, explains from first principles how the "stepping" circuits of the recent Google paper \cite{McEwenBaconGidney} can be constructed.

Novel III-V inverted T-channel TFET with dual-gate impact on line tunneling, with and without negative capacitance

We introduce two novel III-V inverted T-channel vertical line tunnel field-effect transistor (TFET) configurations, leveraging staggered bandgap compound materials. Design D-1 operate s without negative capacitance, while Design D-2 incorporates negative capacitance. Both designs employ area-enhanced gate normal line tunneling with dual-gate impact, utilizing InGaAs and GaAsSb materials to effectively reduce the overall bandgap. The double-area line tunneling, facilitated by the double gate, significantly enhances performance. D-1 exhibits notable improvements, with an ION value reaching 596.55 μA/μm, an ION/IOFF ratio of 2.5 × 108, a minimum subthreshold swing (SS) of 9.75 mV/dec, and an average subthreshold swing (AVSS) of 31.93 mV/dec. Building upon these achievements, D-2 takes a step further by implementing NC through a ferroelectric layer gate stack, significantly increasing the line tunneling rate symmetrically on the left and right channels beneath both gates. This marks the first proposal of double gate area-enhanced line tunneling with negative capacitance in this paper. D-2 demonstrates remarkable performance for future low-power applications.

A novel dimensionality reduction method based on flow model

The sparsity and redundancy of high-dimensional data poses challenges during processing. Dimensionality reduction is a commonly used approach, which helps to reduce data redundancy and noise, lower the complexity of learning algorithms, and improve classification accuracy. Typically, directly determining the intrinsic dimensionality of a dataset is challenging. Many of the present dimensionality reduction techniques suffer from pre-set target dimensions without considering the specific dataset features. To address this problem, a novel dimensionality reduction method based on flow model, which is called adaptive flow encoder (AFE), is proposed in this paper. Initially, the flow model is employed to achieve feature transformation and project the data onto an equip-dimensional feature space. Subsequently, a gating layer is utilized for feature selection. By configuring the gating layer parameters to be learnable, the model gains the ability to adaptively select features. To assess the efficacy of the proposed approach, the model’s ability to preserve data characteristics is first qualitatively evaluated through visual inspection by projecting the data onto a two-dimensional space. Subsequently, five standard datasets are employed and compared against six traditional dimensionality reduction techniques to ascertain the impact on downstream classification tasks under the adaptive learning of intrinsic feature dimensions by the model. Moreover, the impact of key parameters, including the initialization scheme of the gate layer, amplification factor, and dimension factor, on the test results is examined.

Low-temperature preparation and characteristics of top-gate thin-film transistors with La-ZTO active layers and polymethylmethacrylate dielectric layers

A top-gate coplanar-structure thin-film transistor (TFT) combining the advantages of both a co-sputtered amorphous La-doped ZnSnO (a-La-ZTO) active layer and solution-based polymethylmethacrylate (PMMA) gate dielectric layer has been prepared under low temperature (100 °C) with low cost for the first time. The results indicate that the PMMA thin film demonstrates anti-reflection properties when it combines with a-La-ZTO layer to form a double-layer film, displaying high transparency to visible light of ∼90.3%. Moreover, it was found that the La target power during the deposition of a-La-ZTO film plays an important role in suppressing the formation of oxygen vacancies and adjusting the carrier concentration of a-La-ZTO active layer, thus impacting a-La-ZTO TFT performance. Overall, the optimum a-La-ZTO TFT with a La target power of 13.9 W, working in an n-channel enhancement mode, possesses a large saturated mobility (>10 cm2 (Vs)−1) and an on/off drain current ratio over 105.

Non‐Volatile and Gate‐Controlled Multistate Photovoltaic Response in WSe2/h‐BN/Graphene Semi‐Floating Gate Field‐Effect Transistors

AbstractSemi‐floating gate field‐effect transistors (SFG‐FETs) based on 2D materials have received much attention due to their unique optoelectronic characteristics, potential applications in near‐memory computing and constructing sensing‐memory‐processing units. Here, the non‐volatile and gate‐controlled multistate photovoltaic response of a WSe2/h‐BN/graphene SFG‐FET is investigated both in experimental and theoretical aspects. Due to the ambipolar carrier transport of WSe2 channel, both electrons and holes can be stored in the graphene floating gate layer, which results in two evident memory windows on the round sweep transfer characteristic curve. Different charge‐stored states of the SFG layer enable the channel to form a lateral junction that can be adjusted by the gate voltage, which leads to the gate‐controlled multistate photovoltaic response. A theoretical model is implemented to explain the memory and the multistate photovoltaic response behaviors in a quasi‐quantitative level. The relationship between the charge‐stored states in the SFG and the photo‐response, as well as its dependence on the gate voltage are systematically analyzed. These research results provide a reliable way for realizing high‐performance multi‐functional photodetectors based on SFG‐FETs and for thorough understanding the complicated optoelectronic behaviors of SFG‐FETs.

Phase- and Angle-Sensitive Terahertz Hot-Electron Bolometric Plasmonic Detectors Based on Fets with Graphene Channel and Composite H-BN/Black-P/H-BN Gate Layer

In this paper, we propose and analyze the terahertz (THz) bolometric vector detectors based on the graphene-channel field-effect transistors (GC-FET) with the black-P gate barrier layer or with the composite b-BN/black-P/b-BN gate layer. The phase difference between the signal received by the FET source and drain substantially affects the plasmonic resonances. This results in a resonant variation of the detector response on the incoming THz signal phase shift and the THz radiation angle of incidence.

Physical insight into the abnormal VTH instability of Schottky p-GaN HEMTs under high-frequency operation

In this Letter, we investigate the threshold voltage (VTH) instability of Schottky p-GaN gate high electron mobility transistors (SP-HEMTs) under high-frequency operation by a resistive-load hard switching method. The abnormal VTH instability is observed, which is different between fully and partially depleted SP-HEMTs (FD- and PD-HEMTs). Notably, for FD-HEMT, VTH shifts positively with effective stress time. However, the VTH instability in PD-HEMT is more complex. At low VGS (e.g., 3 V) and high VGS (e.g., 6 V), VTH shifts positively with stress time consistently. Nevertheless, at intermediate VGS levels (e.g., 4 and 5 V), VTH initially shifts positively and then negatively, displaying a non-monotonous variation. Furthermore, the frequency dependence of VTH is contingent upon VGS. At low VGS, VTH exhibits a negative shift with the increase in frequency. This trend inverses when VGS exceeds 4 V. And it should be noted that the extracted VTH under high-frequency operation is lower than their quasi-static values for both transistor types. This work depicts the physical process and mechanism of the abnormal VTH instability; different from the quasi-static case, hole accumulation effects will be enhanced due to the high dV/dt, which results in a lower VTH. The distinct VTH behaviors of FD- and PD-HEMTs are closely related to the trapping effects, as well as hole accumulation and insufficiency, within the two different p-GaN gate layers.

A novel MOSFET with lateral–vertical charge coupling for extremely low C gd

A novel MOSFET with lateral–vertical charge coupling (LVCC-MOSFET) is proposed in this paper. Lateral charge coupling is enabled by a metal field plate, lightly doped drain and P-Epi layer to reduce the C gd. Vertical charge coupling is enabled by a shield gate, sinker and P-Epi layer to support a high breakdown voltage (BV) and further reduce the C gd. By combining both lateral charge coupling and vertical charge coupling, which is first proposed in low-voltage power MOSFETs, the trade-off relationship between BV, R on and C gd can be significantly improved. It is verified by both small-signal analysis and transient capacitance simulation that the gate-to-drain capacitance of the proposed LVCC-MOSFET can be reduced by more than 99% without deterioration of BV and R on. The LVCC-MOSFET achieves 93.7% reduction in Q gd, and R on × Q gd is only 0.81 mΩ·nC, which is reduced by 93.9%. Furthermore, E on and E off can be reduced by 73.6% and 53.8%, respectively. The hot carrier injection reliability can be enhanced by reducing the electric field and the impact ionization generation rate near the drain-side gate oxide. Moreover, the LVCC-MOSFET can be feasibly manufactured with compatible fabrication process flow, and only three extra steps are needed.

Al‐Rich AlGaN Transistors with Regrown p‐AlGaN Gate Layers and Ohmic Contacts

AbstractEpitaxial regrowth processes are presented for achieving Al‐rich aluminum gallium nitride (AlGaN) high electron mobility transistor (HEMTs) with p‐type gates with large, positive threshold voltage for enhancement mode operation and low resistance Ohmic contacts. Utilizing a deep gate recess etch into the channel and an epitaxial regrown p‐AlGaN gate structure, an Al0.85Ga0.15N barrier/Al0.50Ga0.50N channel HEMT with a large positive threshold voltage (VTH = +3.5 V) and negligible gate leakage is demonstrated. Epitaxial regrowth of AlGaN avoids the use of gate insulators which can suffer from charge trapping effects observed in typical dielectric layers deposited on AlGaN. Low resistance Ohmic contacts (minimum specific contact resistance = 4 × 10−6 Ω cm2, average = 1.8 × 10−4 Ω cm2) are demonstrated in an Al0.85Ga0.15N barrier/Al0.68Ga0.32N channel HEMT by employing epitaxial regrowth of a heavily doped, n‐type, reverse compositionally graded epitaxial structure. The combination of low‐leakage, large positive threshold p‐gates and low resistance Ohmic contacts by the described regrowth processes provide a pathway to realizing high‐current, enhancement‐mode, Al‐rich AlGaN‐based ultra‐wide bandgap transistors.

A Self‐Powered Photodetector Based on Graphene Enhanced WSe2/PtSe2 Heterodiode with Fast Speed and Broadband Response

AbstractNarrow bandgap 2D layered material platinum selenide (PtSe2) with good environmental stability, high carrier mobility, and high light absorption, has been widely investigated for uncooled midwave‐infrared (MWIR) photodetection. However, the phototransistor based on the PtSe2 operation at room temperature suffered from the high dark current and background noise. Here, a graphene (G)‐enhanced G‐WSe2/PtSe2 hetero‐diode placed on a metal electrode is reported. To enhance the photogain, a graphene layer placed on the WSe2/PtSe2 heterodiode as a local gating layer is designed. The device exhibits an ultra‐high light on/off ratio of up to 108 and ultra‐fast photoresponse speed with raising time τr = 0.9 µs and decay time of τd = 1.5 µs in the visible spectra range. Notably, ultrabroad band photoresponse from 405 to 3366 nm is demonstrated under the self‐power model. Notably, the device presented a competitive photovoltaic effect with a high energy conversion efficiency (PCE) of 3.45%. The results pave the way toward a new approach to tuning the performance of the atomic thin layered materials photodetector.

MoDE: A Mixture-of-Experts Model with Mutual Distillation among the Experts

The application of mixture-of-experts (MoE) is gaining popularity due to its ability to improve model's performance. In an MoE structure, the gate layer plays a significant role in distinguishing and routing input features to different experts. This enables each expert to specialize in processing their corresponding sub-tasks. However, the gate's routing mechanism also gives rise to "narrow vision": the individual MoE's expert fails to use more samples in learning the allocated subtask, which in turn limits the MoE to further improve its generalization ability. To effectively address this, we propose a method called Mixture-of-Distilled-Expert (MoDE), which applies moderate mutual distillation among experts to enable each expert to pick up more features learned by other experts and gain more accurate perceptions on their allocated sub-tasks. We conduct plenty experiments including tabular, NLP and CV datasets, which shows MoDE's effectiveness, universality and robustness. Furthermore, we develop a parallel study through innovatively constructing "expert probing", to experimentally prove why MoDE works: moderate distilling knowledge from other experts can improve each individual expert's test performances on their assigned tasks, leading to MoE's overall performance improvement.

The Performance of Organic Field Effect Transistor Affected by Different Thickness of Active Semiconductor Layer and Thickness of Gate Insulator

The purpose of this paper is to fabricate organic field effect transistor and to investigate the effect of the thickness of the pentacene active layer and the thickness of gate insulator layer on MOSFET performance. The fabricated structure is top-contact. When the thickness of the insulator gate layer increases from 10 nm to 30 nm, the magnitude of the drain source current, when VGS = VDS = -4 V, decreases from 1813 nA to 214 nA and then the threshold voltage shifts from -1.4 V to -2.4 V. When the thickness of the pentacene increases from 9 nm to 40 nm, the threshold voltage voltage shifts slightly in the negative direction from -1.4 V to -1.6 V for SiO2 thickness of 10 nm. In case of SiO2 thickness of 20 nm, the threshold voltage voltage shifts from -1.9 V to -2.2 V. In case of SiO2 thickness of 30 nm, the threshold voltage voltage shifts from -2.4 V to -2.9 V. Besides that, the mobility decreases from around 0.31 cm2/(Vs) to 0.15 cm2/(Vs) when the pentacene thickness increases from 9 nm to 40 nm.

First-principles study on MoSSe/ GaTe van der Waals heterostructures: A promising water-splitting photocatalyst

Photocatalytic water splitting using semiconductor electrocatalysts in photoelectrochemical cells is an appealing approach to converting sunlight and water into clean and renewable hydrogen fuel. MoSSe/GaTe der Waals heterojunctions has recently been suggested as a promising photocatalyst for water splitting. Depending on the stacking mode, the two type MoSSe/GaTe heterojunctions have moderate band gaps of 1.081 eV and 1.307 eV, significant visible absorption coefficients, and band-edge positions spanning the redox potential of water. Bader charge and differential charge density analyses show that the GaTe layer loses electrons and the MoSSe monolayer gains electrons, resulting in a built-in electric field pointing from the GaTe layer to the MoSSe layer. Moreover, the Gibbs free energy diagram indicates that solar energy can effectively drive water splitting on MoSSe/GaTe junction. The influence of the bi-axial strain and pH value of water are discussed. Therefore, the MoSSe/GaTe heterostructures are promising for applications in photocatalytic water decomposition.

Polarizable Nonvolatile Ferroelectric Gating in Monolayer MoS2 Phototransistors.

Given the requirements for power and dimension scaling, modulating channel transport properties using high gate bias is unfavorable due to the introduction of severe leakages and large power dissipation. Hence, this work presents an ultrathin phototransistor with chemical-vapor-deposition-grown monolayer MoS2 as the channel and a 10.2 nm thick Al:HfO2 ferroelectric film as the dielectric. The proposed device is meticulously modulated utilizing an Al:HfO2 nanofilm, which passivates traps and suppresses charge Coulomb scattering with Al doping, efficiently improving carrier transport and inhibiting leakage current. Furthermore, a bipolar pulses excitable polarization method is developed to induce a nonvolatile electrostatic field. The MoS2 channel is fully depleted by the switchable and stable floating gate originating from remanent polarization, leading to a high detectivity of 2.05 × 1011 Jones per nanometer of gating layer (Jones nm-1) and photocurrent on/off ratio >104 nm-1, which are superior to the state-of-the-art phototransistors based on two-dimensional (2D) materials and ferroelectrics. The proposed polarizable nonvolatile ferroelectric gating in a monolayer MoS2 phototransistor promises a potential route toward ultrasensitive photodetectors with low power consumption that boast of high levels of integration.

Tin disulfide nanoflowers and nitrogen doped graphene oxide based extended gate field effect transistor as immunosensors

Miniaturized biosensor design is widely preferred for its application in integrated platform to provide rapid and sensitive diagnosis. However, there are only few reports which employ extended gate field effect transistors (EG-FET) for immunosensing application. Herein, we designed EG-FET using four level lithography techniques. Further, the gate layer (Au/Ti) of device has been modified with Tin disulfide nanoflowers (SnS2) and nitrogen doped graphene oxide (N-GO) hybrid composite for enhanced electrical sensing. The as-prepared SnS2 and N-GO based nanocomposite (SnS2/N-GO) was characterized by various techniques. The designed SnS2/N-GO based EG-FET was employed as an immunosensor to detect HIgG using anti-HIgG antibody. Under optimum conditions, our miniaturized immunosensor demonstrated the detection of HIgG as low as 4.81 ng/mL. The proposed immunosensor exhibited excellent sensitivity, selectivity and reproducibility towards HIgG detection, thereby suitable for a reliable integrated biosensing platform which can detect protein concentration in real samples for clinical diagnostics.