Gate Field-effect Transistor Memory Research Articles

Simple Synthesis of Palladium Nanoparticles, β-Phase Formation, and the Control of Chain and Dipole Orientations in Palladium-Doped Poly(vinylidene fluoride) Thin Films

Palladium nanoparticles (Pd-NP's) are prepared by a simple one-step procedure when poly(vinylidene fluoride) (PVDF) is used as a polymer stabilizer. High-quality Pd-NP-doped PVDF thin films are fabricated where the heat-controlled spin-coating technique is adopted. The effect of Pd-NP's on the crystal modifications and lamellae orientation in PVDF films is investigated using Fourier transform infrared-grazing incidence reflection absorption spectroscopy. The electroactive β phase and edge-on crystalline lamellae are found to be formed preferentially in Pd-NP-doped PVDF films. As a result, Pd-NP-doped PVDF ultrathin films gave a very good discernible contrast between the written and erased data bits, which suggests that they can be used as a scanning-probe-microscopy-based ferroelectric memory device or a ferroelectric gate field-effect transistor memory device in the future.

Technology of Ferroelectric Thin-Film Formation with Large Coercive Field on Amorphous SiO2 by Ion-Bombardment-Assisted Sputtering and Oxygen Radical Treatment for Future Scaling Down of Ferroelectric Gate Field-Effect Transistor Memory Device

Sr2(Ta1-x,Nbx)2O7 (perovskite STN; x=0.3) is one of the most practical candidates for one-transistor-type ferroelectric memory devices, because it has a low dielectric constant. However, in the application to metal–ferroelectric–insulator–Si field-effect transistor (MFIS-FET) memory devices, the fabrication of STN on an amorphous insulator, such as SiO2, is difficult. In particular, in the case of STN, because its crystallization annealing temperature is 950 °C, the metal elements of STN and Si react with each other during crystallization annealing. As a result, perovskite STN cannot be fabricated. To overcome this problem, we have developed an ion-bombardment-assisted sputtering method. Furthermore, to obtain universal conditions for forming perovskite STN based on plasma physics, plasma parameters such as ion bombardment energy and ion flux, were measured. Perovskite STN was obtained when the ion bombardment energy was 38 eV and the normalized Kr ion flux was 78 [ions/atom]. An IrO2/STN (140 nm)/STN seed layer (10 nm)/Si device whose STN was fabricated under these plasma conditions, shows square hysteresis curves and a memory window of 1.7 V under an 8 V writing operation. This value corresponds to a coercive field of 55 kV/cm.

Fabrication and Characterization of Ferroelectric Gate Field-Effect Transistor Memory Based on Ferroelectric–Insulator Interface Conduction

A new type of ferroelectric gate field-effect transistor (FET) using ferroelectric–insulator interface conduction has been proposed. Drain current flows along the interface between the ferroelectric and insulator layers and requires no semiconductor. The channel region of the FET is composed of a Pt/insulator HfO2/ferroelectric Pb(Zr0.52Ti0.48)O3 (PZT)/Pt/TiO2/SiO2/Si multilayer, and the source and drain areas are formed at the interface of the PZT and HfO2 films. Drain current versus gate voltage characteristics show a clockwise hysteresis loop similar to that for a conventional p-channel transistor. The FET shows that the on/off ratio of the conduction current is within 105 to 106 and that the off-state current is about 10-10 A.

Operation of Ferroelectric Gate Field-Effect Transistor Memory with Intermediate Electrode using Polycrystalline Capacitor and Metal–Oxide–Semiconductor Field-Effect Transistor

We have investigated the basic operation of a ferroelectric gate field-effect transistor (F-FET) memory with an intermediate electrode for data writing, using a discrete circuit which consists of a polycrystalline ferroelectric capacitor connected serially to the gate of a commercial n-channel metal–oxide–semiconductor (MOSFET). By sputtering, a ferroelectric capacitor Cf was formed as a (RuO2 top electrode)/poly-Pb(Zr0.52Ti0.48)O3(PZT)/(Pt/RuO2 bottom electrode) structure on a SiO2/Si substrate. The readout characteristics showed nondestructive operation. It was also shown that the output voltage for the positive and the negative polarization memory states corresponded very well with the intermediate electrode voltages on the gate of the MOSFET. Furthermore, the ratio of the ferroelectric capacitor to the input capacitor of the MOSFET was found to be an important factor influencing the cycle number of nondestructive reading and the difference in output voltage between the positive and negative polarization states.

Analysis on operation of a F-FET memory with an intermediate electrode

An operation model of a ferroelectric gate field-effect transistor memory with an intermediate electrode was proposed and analyzed. Read endurance characteristics of the memory during a consecutive reading was simulated using this model. The simulation results showed good agreement with the experimental data.

Retention and Read Endurance Characteristics of a Ferroelectric Gate Field Effect Transistor Memory with an Intermediate Electrode

Fundamental characteristics such as retention and read endurance of a ferroelectric gate field effect transistor (F-FET) memory with an intermediate electrode were investigated and reported. It was verified that the retention time of the new F-FET was longer than 98 h. By taking into account the leakage currents of both the ferroelectric capacitor Cf and the MOSFET used for data writing (W-FET), we found that, for positive reading voltage, the leakage currents of the ferroelectric capacitor and the W-FET are unfavorable for the Pr+ state and the Pr- state, respectively, in terms of read endurance. The overall read endurance is determined by a competition between the leakage currents of the Cf and the W-FET. The drain-connected configuration (DCC) was effective to minimize the unexpected influence of the leakage current of the W-FET.

Proposal for a New Ferroelectric Gate Field Effect Transistor Memory Based on Ferroelectric-Insulator Interface Conduction

A new type of ferroelectric gate field effect transistor (FET) using ferroelectric-insulator interface conduction has been proposed. Drain current flows along the interface between the ferroelectric and insulator layers and needs no semiconductor. The FET has been fabricated by forming drain and source electrodes on a SiON/Si substrate, depositing SrBi2Ta2O9 (SBT) film, and then forming the gate electrode. Drain current versus gate voltage characteristics show counterclockwise hysteresis loop similarly to the conventional metal-ferroelectric-insulator-semiconductor-FET (MFIS-FET), and the loop is due to polarization hysteresis of the SBT film. The FET shows that 1) the On/Off ratio of the conduction current is 3.8 at 0 bias voltage and 2) the relationship of the conduction current to channel width and length coincides well with the predicted characteristics.

Optical control of charge number in single floating quantum-dot gate in field-effect transistor structure

The optical characteristics of a single floating quantum-dot (QD) gate field-effect transistor memory cell were investigated at 77 K. The channel current, which can detect sensitively the charging of the QD, was saturated via some discrete levels after illuminations by light pulses, and the saturation value increased with the stronger illumination power. It was also found, by comparing the optical writing characteristics for different illumination powers at 77 K with retention characteristics at 120 K, that the discrete current levels observed in the optical characteristics corresponded to the hole number variation in the single QD. These results show that the number of holes stored in a single QD was controlled by changing the illumination power.

Analysis of stored charge volatility in an MAOS memory element

An exact analytical solution is derived for the dynamics of the interface discharging process for a metal/Al 2O 3/SiO 2/Si (MAOS) insulated gate field effect transistor memory device. The predicted results are shown to be in good agreement with experimental data. It is seen that the discharge current is through the Al 2O 3 rather than the SiO 2 layer for the self-bias discharging conditions usually encountered. At temperatures above about 200°C the ohmic component of the Al 2O 3 current controls the volatility, whereas at lower temperatures (including room temperature) the Poole-Frenkel current is important. Hence the discharge process is highly temperature sensitive. The theory also predicts that the usually quoted half-lives of the interface charge at room temperature (of the order of 10 15 h based on the log time dependence) are gross overestimates; a more realistic value based on the exact theory is about 10 4–10 5 h.