Gate FET Research Articles

Unsymmetrical calix[4]arene ionophore/silicone rubber composite membranes for high-performance sodium ion-sensitive field-effect transistors

As neutral carriers for soduim ion-sensitive field-effect transistors (ISFETs), unsymmetrical calix[4]arene ionophores have been designed which possess three ester linkages and an amide linkage as the cation-binding sites. One of the calix[4]arene derivative are highly soluble in silicone rubber, which is very adhesive to inorganic FET gates, thus affording stable sensing membranes for the ISFET. The resulting sodium ISFETs based on the calixarene ionophore/silicone rubber composities showed high sodium ion selectivity and high sensor durability

Fabrication of novel self-aligned metal insulator semiconductor field effect transistors (MISFETs) on InP by a S interface engineering technique

In this paper we demonstrate for the first time that self-aligned metal insulator semiconductor field effect transistors (MISFETs) can be realized on InP by incorporating an effective surface passivation technique in the fabrication process. A chemical sulfur treatment is used to passivate the InP – indirect plasma silicon nitride interface that results in interface state densities (Dit) in the low 1011/cm2 eV. It is observed that while passivated self-aligned MISFETs subjected to post-passivation high-temperature process cycles up to 700 °C exhibit acceptable transistor characteristics, unpassivated MISFETs using the same process do not show any transistor action. The passivation procedure has been successfully used to demonstrate for the first time a self-aligned InP–InGaAs–InP heterojunction insulated gate FET. We conclude from this work that interface engineering techniques like the one used in this study would be essential to realize and (or) improve the performance of self-aligned FET structures based on InP. The fabrication process described here can be directly applied to similar interface engineering techniques.

A pulsed microwave oscillator using optically controlled active feedback

An optically controlled microwave oscillator is demonstrated using MMIC compatible design techniques. The oscillator uses an optically controlled active inductor as a tunable feedback element in a two-port common gate FET circuit configuration. Experimental results are presented for a pulsed mode of operation that is triggered by illuminating the active feedback circuit. >

Heterostructure field effect transistors grown by MOVPE

Metalorganic vapor phase epitaxy (MOVPE) has received much attention as an important technique for the growth of III–V compound semiconductor layers for electronic and optoelectronic applications. The move of the AlGaAs/GaAs heterostructure field effect transistor (HFET) technology from research to production will be discussed in this paper. In addition developments such as undoped AlGaAs/GaAs heterostructure insulated gate FET (HIGFET) for digital applications will be reported. These FET offer the possibility of easy production of both n- and p-type channel devices on the same layer structure. The improvements in the performance of electronic devices such as latticematched InP-based n-channel HFET grown by MOVPE will be shown. Especially for p-type structures a reduction in the effective hole mass due to strain causes improvements in the operation of p-type pseudomorphic devices. These InP HFET grown by MOVPE are favorable candidates for the application in high-performance optoelectronic integrated circuits in the 1.1–1.65 μm region.

An InGaAs/InP p-i-n-JFET OEIC with a wing-shaped p/sup +/-InP layer

A receiver optoelectronic integrated circuit (OEIC) structure with an InGaAs p-i-n photodiode, InGaAs self-aligned junction FETs and a bias resistor has been fabricated on a semi-insulating InP substrate. The fabrication processes are highly compatible between the photodiode and the JFET, and reduction in FET gate length is achieved using anisotropic selective etching and a two-step organometallic vapor phase epitaxy (OMVPE) growth schedule. The 80- mu m diameter p-i-n detector exhibits a leakage current of 2 nA and a capacitance of about 0.35 pF at -5 V bias voltage. Extrinsic transconductance and a gate-source capacitance of the JFET are typically 45 mS/mm and 4.0 pF/mm at 0 V, respectively. The maximum voltage gain of the preamplifier is 12.5 and the bandwidth of the p-i-n amplifier OEIC is expected to be about 1.2 GHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Digital GaAs FET versus Si FET gate delay as predicted from the electron velocity

A FET model that takes into account the effective saturation velocity (including the effect of velocity overshoot), fringing capacitance, and source resistance is discussed. The model is applied to identical differential source-coupled FET logic gates in both GaAs and Si. The simulated gate delay of the Si logic gate is about 2.6 times that of the GaAs gate, thus refuting the common hypothesis that GaAs gate, thus refuting the common hypothesis that GaAs and Si delays should be about equal because their equilibrium saturated electron velocities are about equal. >

Developer selection for T-shaped gate FET's using PMMA/P(MMA-co-MAA)/PMMA

A T-shaped gate fabrication process has been developed based on a triple-layer resist system with gate cross section control by resist developer formulation. The new procedure allows a conventional e-beam exposure and single develop step to accomplish what requires position dependent e-beam doses or multiple exposures and multiple develop steps in other processes. General considerations in developer selection are discussed. For the process conditions used in this study, gate lengths from 80 to 280 nm were obtained from doses from 250 to 350 mu C/cm/sup 2/ with 20-keV electrons. Initial results on RF performance for a 1.2-mm periphery power FET are given.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Growth and properties of InAs xSb 1−x, Al yGa 1−ySb, and InAs xSb 1−x/Al yGa 1−ySb heterostructures

A series of undoped InSb and InAs xSb 1−x layers were grown using tetramer Sb 4 and As 4 sources on (100)-oriented semi-insulating GaAs and InP substrates with different growth parameters. Very high electron mobilities (70,000 and 110,000 cm 2/V⋯s in InSb at 300 and 77 K, respectively) and n-type conductivity are obtained for all alloy compositions. The flux ratio P Sb/ P In played a crucial role in determining the surface morphology and the mobility of InSb films. Barrier heights of A1 p−Al yGa 1−ySb Schottky diodes are measured and are 0.4 eV. A 300 Å Si-doped InAs 0.8Sb 0.2 channel region sandwiched bet ween undoped Al 0.4Ga 0.6Sb buffer and gate barrier regions has μ = 1000 cm 2/ V⋯ s and n s = 5.4×10 12 cm −2 at 300 K. 1 μm ga te FETs made with this heterostructure have shown a maximum extrinsic g m = 160 mS/mm and ƒ T = 5 GHz at 300 K .

Broadband active circulators

AbstractThis paper describes three types of active circulators: the first structure consists of three dual gate FETs and its operating frequency range is 0.4 to 2.6 GHz. This circulator uses a phase‐divider circuit. The forward insertion loss is 0.4 dB while the isolation is 21 dB; the second structure consists of three each of RF transformers and AGC amplifiers. The operating frequency range of this active circulator is 0.3 to 1.4 GHz. The forward insertion loss is 0.3 dB and the isolation is 29 dB; and the third active circulator consists of three each of phase inverters and broadband amplifiers. The operating frequency range is 5 to 10 GHz. The isolation and the forward insertion loss are 27 and 0.3 dB, respectively. This circulator can be used for an input power of up to 19 dBm.

High frequency GaAs switched capacitor filter implemented with GaAs insulated gate FET switches

A switched capacitor filter implemented with 5μn GaAs IGFET switches and GaAs MESFET operational amplifiers is presented. The circuit is clocked at 25MHz. By scaling to 1μm IGFETs, a switching speed of about 625 MHz should be attainable. Use of GaAs IGFET switches is shown to greatly reduce power consumption and complexity of the circuit. The low frequency switching instability of the GaAs IGFET is shown to be of no consequence in this application.

0.2- mu m gate AlGaAs/GaAs HIGFET (heterostructure insulated gate FET) with a

A GaAs HIGFET with a K value of 1 A/V/sup 2//mm has been developed for application to high-speed LSIs. A description is presented of the three essential processes for fabricating this HIGFET: (1) a gate process using a

Anisotropic Reactive Ion Etching of Submicron W Features In CF4 or SF6 Plasmas

ABSTRACTAnisotropie RIE etching of Tungsten (W) in a low voltage CF4 or SF6 plasma while achieving features as small as 0.50 μm is demonstrated using Titanium (Ti) as an etch mask. For reasons of reliability and tolerance to high temperature processing techniques, W can be a desirable contact metal in microelectronics fabrication. Due to its high melting point (3400°C) it is not practical to evaporate W contacts using conventional liftoff photolithography methods. Therefore pattern transfer of sputtered W must be performed by plasma etching using some type of mask. In III-V materials systems, a Fluorine based plasma is desirable due to its high selectivity for W over semiconductor materials. The problem is that when using conventional photoresist masks, W does not etch anisotropically. Therefore critical feature dimensions (which are sub-micron for FET gates) and vertical profiles cannot be successfully transferred to the underlying W. However by using a Ti mask during the CF4 or SF6 plasma etch, TiF4 is produced on the sidewalls of the W inhibiting any horizontal etch. The Ti mask can be removed selectively after etching of the W is complete. Using a Ti mask to etch W ensures excellent pattern transfer of device dimensions even at very low bias voltage.

Ultra-compact monolithic integration of polarization diversity waveguide photodiodes

A description is given of a device which consists of an input rib waveguide, a vertically defined coupler, a vertically coupled mesa p-i-n photodiode (PD), a second coupler, and a second PD, all serially connected. A gold cover on the first coupler ensures that only TE-polarized light is coupled into the first PD; the second coupler/PD pair collects the remaining TM light. Component lengths are 79 and 54 mu m for couplers and 21 and 31 mu m for PDs, for approximately 200- mu m total detector length. The device consists of p-InGaAsP/i-InGaAs/n-InGaAsP PD layers above semi-insulating coupler layers (two GaAsP:Fe guides, InP:Fe cladding). The vertically integrated coupler/detectors are more than an order of magnitude smaller than conventional couplers, and of comparable size to electronic components (e.g. FET gate widths).

Power MISFETs fabricated with superlatticed gate “insulators” and transition buffer layers

A new GaAs MISFET with superlatticed gate “insulator” and transition buffer layer structure is proposed in this paper. The use of an undoped GaAsAl 0.3Ga 0.7As superlatticed gate “insulator” provides a high gate breakdown voltage ( > 36 V) with very low prebreakdown leakage current and a low gate capacitance ( C gs ), compared to usual MESFET devices. Due to the existence of the gate “insulator”, a high carrier concentration can be employed in the active channel, which improves the outer-drain-current capability and transconductance (over 200 mS/mm can be expected if the gate length is reduced to 1 μm). Also three different transition-buffer layers i.e. superlattice, graded superlattice and modulation-doped (MD) structures have been inserted between the active-channel and buffer layer respectively, to offer an excellent carrier confinement (to obtain a small interface degraded region) or to enhance the electrical performance of the active channel. Finally, the I V characteristics, output conductance and transconductance g m of the superlatticed gate FETs with different transition-buffer layers are investigated and compared. From the experimental results, it is clear that the proposed structures are suitable for power application.

A 17.5-GHz 3-bit phase-shift receive MMIC-fabrication and test results

A high-yield, FET gate fabrication technology is described. The main advantage of this processing approach is that it permits fabrication of devices with gate lengths of less than 0.5 mu m using standard optical photolithography without recourse to deep UV or electron-beam lithography. The process is simple and easy to implement in a manufacturing environment. Exceptionally good gate-length control, typically 10% for a 0.4- mu m-long gate, is demonstrated. Yield of a 300- mu m-wide FET, designed for use in a gain block and in a switch, is found to be 89% on average. Data on wafer-to-wafer and on-wafer variations in device DC and RF parameters and equivalent circuit values are presented. Typical standard deviations are in the 5-10% range. This process technology has been used to fabricate a 17.5-GHz, 3-b phase-shift receive monolithic microwave integrated circuit (MMIC) of moderately high complexity. Statistics of RF data on 704 such devices, fabricated over a period of two years, are presented. It is shown that such MMICs can be fabricated with yields sufficient for prototype active phased-array antenna applications. >

A variable‐gain constant‐phase dual‐gate amplifier with series feedback

AbstractThis paper presents series feedback used in a variable‐gain constant‐phase dual‐gate amplifier for T / R module applications. The inductive series feedback element shifts the input match of the dual gate FET to an impedance that is much easier to match 50 ohms. This allows the amplifier to have a much broader bandwidth and increased gain while maintaining constant phase in the different gain states. This amplifier was fabricated as a MMIC chip using the ITT MSAG process, and we obtained excellent performance: variable gain range of 13 dB, VSWR better than 2.0:1, phase variation less than ±2°, and gain flatness of ±0.4 dB over the 4.5‐6‐GHz frequency range.

New suspended gate FET technology for physical deposition of chemically sensitive layers

Abstract The chemically sensitive layer that is located underneath the suspended gate metal of the field-effect transistor has until now been deposited exclusively by electrochemical means. A new method for the physical deposition of the sensitive layer within the suspended gate structure has been developed. By introducing the single-layer lift-off process to the fabrication sequence of the device, it is now possible to deposit selective materials before the suspended gate is made. Therefore general thin-film techniques can be used. This offers the advantage that materials of great interest, such as non-soluble metal oxides, can be deposited. Also all chips on a wafer can be processed at the same time.

High performance GaAs MESFETs grown on InP substrates by MOCVD using tertiarybutylarsine

Device performance of GaAs metal-semiconductor field effect transistors (MESFETs) grown by metalorganic chemical vapour deposition (MOCVD) on InP substrates using tertiarybutylarsine (t-BuAsH/sub 2/) is reported. The 1 mu m gate FETs have a maximum extrinsic transconductance of 135 mS/mm and an output transconductance of 5.5 mS/mm. A frequency of unity current gain of 11 GHz and a maximum frequency of oscillation of 22 GHz are obtained from S-parameter measurements. DC and microwave characteristics of t-BuAsH/sub 2/ grown GaAs MESFETs are comparable to those of GaAs MESFETs grown using AsH/sub 3/.

New distributed package model for the dual gate FET

A new distributed package model for a dual gate MESFET is presented. This model is based on the physical structure of the device package and describes the package effects accurately. With its simple structure, this model can easily be characterised using S-parameter fitting procedures. It serves as an accurate engineering level model.

Gallium arsenide MBE structure comprising mixer diodes and FETs for monolithic millimetre-wave receivers

The formation of millimetre-wave GaAs mixer diodes and 0.5 μm gate FETs on the same wafer has been demonstrated using a three-layer MBE structure. The diodes have a measured cut-off frequency of 780GHz and the FETs typically exhibit fmax greater than 50GHz. This technology is suitable for the implementation of monolithic microwave and millimetre-wave receivers.