Gate Delay Model Research Articles

Reliable Circuit Design Using a Fast Incremental-Based Gate Sizing Under Process Variation

As CMOS devices become smaller, aging-induced and process variations become major issues for circuit reliability. In this paper, a statistical gate sizing method is proposed to improve the lifetime reliability of manufactured chips in the presence of process variations and aging effects. To this end, we propose a canonical first order delay model to estimate the delay degradation of a gate under negative bias temperature instability and process variations considering spatial correlations. Using the proposed gate delay model, a statistical static timing analysis method is introduced to compute the circuit delay considering the joint effect of process variation and negative bias temperature instability. To guarantee that the circuit meets the required timing constraints, we propose an incremental gate sizing technique. This technique first computes the criticality of each gate defined as the probability that a gate lies on the critical path due to negative bias temperature instability and process variations. Then, a group of gates with the highest ranking according to criticality is chosen for a gate sizing-based timing optimization. It is worth nothing that, by using the proposed statistical gate delay model, we can compute the criticality of each gate incrementally. Experimental results based on ISCAS’85 benchmark circuits show that the proposed method can improve the lifetime reliability defined as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.1(\mu + 3\sigma)$ </tex-math></inline-formula> of the initial delay distribution of the circuit at the expense of 8.64% area overhead. In comparison with the path-based method, the proposed approach is much faster, especially for larger circuits, which makes it a viable solution to optimize the lifetime reliability of very large-scale circuits used in industry.

Statistical Gate-Delay Modeling with Copulas

The growing impact of process variations on circuit performance has become a major concern for deep-submicron integrated circuit design, resulting in numerous SSTA-algorithms. The acceptance of such algorithms in industry however will be dependent on modeling the real silicon behavior in SSTA. This includes that the statistical gate-delay models must consider arbitrary process variations and dependencies. In this paper, we introduce the innovative concept of Copulas to handle this topic. A complete Matlab based framework starting from process parameter statistics up to the computation of the statistical gate-delay distribution is presented. Experimental results demonstrate the importance of accounting realistic process variations.

New voltage and temperature scalable gate delay model applied to a 14nm technology

&lt;p&gt;The following work shows an innovative approach to model the timing of&lt;br /&gt;standard cells. By using mathematical models instead of the classical SPICE-based characterization, a high amount of CPU (Central Processing Unit) cores is saved and less amount of data is stored. In the present work,&lt;br /&gt;characterization of cells of a standard cell library is done in an hour whereas&lt;br /&gt;it is done in 650 hours with the classical method. Also, a method for&lt;br /&gt;validating and verification of the precision of the modelled data is presented&lt;br /&gt;by comparing them on a implemented circuit. The output of implementations shows less than 3% of error between the two methods.&lt;/p&gt;

Statistical gate-delay modeling with copulas

The growing impact of process variations on circuit performance has become a major concern for deep-submicron integrated circuit design, resulting in numerous SSTA-algorithms. The acceptance of such algorithms in industry however will be dependent on modeling the real silicon behavior in SSTA. This includes that the statistical gate-delay models must consider arbitrary process variations and dependencies. In this paper, we introduce the innovative concept of Copulas to handle this topic. A complete Matlab based framework starting from process parameter statistics up to the computation of the statistical gate-delay distribution is presented. Experimental results demonstrate the importance of accounting realistic process variations.

Joint Effects of Aging and Process Variations on Soft Error Rate of Nano-Scale Digital Circuits

Soft errors have always been a concern in the design of digital circuits. As technology down-scales toward Nanometer sizes, emergence of aging effects, process variations, and Multiple Event Transients (METs) has made the soft error rate (SER) estimation of digital circuits very challenging. This paper intends to characterize the challenges by investigating the cross effects of theses issues in overall SER of a circuit. To this regard, we employ a simulation-based SER estimation approach in which the aging effect, process variations and METs are jointly considered in our fault injection process. In our simulation-based SER estimation approach, a statistical gate delay model is used. The fault injection results into ISCAS85 circuit benchmark reveal that the SER estimation without taking into account the aging effects, the process variations, and METs is significantly inaccurate.

Process variation-aware gate sizing with fuzzy geometric programming

Limitations of manufacturing process in nanometer dimensions have led to large discrepancies between the circuit design and the manufactured chip known as process variation. In this paper, a new gate sizing method based on fuzzy geometric optimization approach is introduced for power minimization of digital circuits subjected to timing constraints under process variations. In the proposed geometric optimization approach, an accurate gate delay model is applied in which the delay variation is represented by fuzzy numbers; therefore, the subsequent optimization problem is a fuzzy geometric programing problem. In order to efficiently solve the fuzzy geometric programing problem, firstly, the problem is converted into a fuzzy linear programming problem and then, using the expected value and Mellin transform, it is converted into a non-fuzzy problem which is solved by traditional solution techniques. Experimental results show that, the proposed technique achieve more power reduction compared to a fuzzy linear programming method.

An Analytical Gate Delay Model in Near/Subthreshold Domain Considering Process Variation

Voltage scaling technique is widely employed in state-of-the-art low power circuits with excellent power reduction. However, voltage scaling to sub-threshold (STV) and near-threshold (NTV) domain introduces performance degradation and high process variation sensitivity. Accurate modeling of the statistical characteristics especially the probability distribution function (PDF) and the cumulative distribution function (CDF) is urgently required with process variation consideration. In this paper, a novel analytical model is derived based on log-skew-normal (LSN) distribution to precisely evaluate the gate delay variation. The multi-variate threshold variation in stacked gates are modeled with a linear approximation method in delay distribution derivation. By applying the CDF of the proposed model, the maximum and minimum delay indicated by ±3σ percentile point can be calculated essentially different from the common method with much higher accuracy. Experimental results show the proposed model is highly fitted with Monte Carlo (MC) results for stochastic delay modeling of generic logic gates in near/subthreshold regime with less than 8% and 6% error in delay variability and ±3σ delay prediction, showing maximum accuracy improvement about 40 times compared to preproposal models.

Comprehensive Reliability-Aware Statistical Timing Analysis Using a Unified Gate-Delay Model for Microprocessors

A framework is proposed to perform timing analysis of state-of-art microprocessors considering the impact of process-voltage-temperature (PVT) variations and the aging effect, including bias temperature instability (BTI), hot carrier injection (HCI), and time-dependent dielectric breakdown (TDDB). In this work, not only statistical timing analysis (StTA) due to each wearout mechanism is studied individually, but also the performance degradation while all these wearout mechanisms happen simultaneously is analyzed. Moreover, this work takes into account realistic use scenarios which include active, standby, and sleep modes. A unified gate-delay model, which combines both PVT variations and the aging effect, is constructed via a technique called multivariate adaptive regression splines (MARSP). Then a timing engine, which consists of two parts: a block-based analyzer and a path-based analyzer, is built to perform PVT-reliability-aware timing analysis. The accuracy and effectiveness of our framework has been verified on large industrial designs, like the LEON3 microprocessor, through a comparison with SPICE.

A Skew-Normal Canonical Model for Statistical Static Timing Analysis

The use of quadratic gate delay models and arrival times results in improved accuracies for a parameterized block-based statistical static timing analysis (SSTA). However, the computational complexity is significantly higher. As an alternative to this, we propose a canonical model based on skew-normal random variables (SN model). This model is derived from the quadratic canonical models and can consider the skewness in the gate delay distribution as well as the nonlinearity of the MAX operation. Based on conditional expectations, we derive the analytical expressions for the moments of the MAX operator and the tightness probability that can be used along with the SN canonical models. The computational complexity for both timing and criticality analysis is comparable with SSTA using linear models. There is a two to three orders of magnitude improvement in the run time as compared with the quadratic models. Results on ISCAS benchmarks show that the SN models have a lower variance error than the quadratic model, but the error in the third moment is comparable with that of the semiquadratic model.

System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown

A framework is proposed to analyze system-level reliability and evaluate the lifetimes of state-of-art microprocessors considering the impact of process–voltage–temperature (PVT) variations and device wearout mechanisms, including bias temperature instability (BTI), hot carrier injection (HCI), and gate oxide breakdown (GOBD). This work studies not only the system performance degradation due to each wearout mechanism individually, but also the performance degradation while all these wearout mechanisms happen simultaneously. A unified gate-delay model is developed to combine PVT variations and the aging effect, and then a statistical timing engine is constructed to analyze performance degradations and system lifetimes.

Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model

Dynamic power estimation is essential in designing VLSI circuits where many parameters are involved but the only circuit parameter that is related to the circuit operation is the nodes’ toggle rate. This paper discusses a deterministic and fast method to estimate the dynamic power consumption for CMOS combinational logic circuits using gate-level descriptions based on the Logic Pictures concept to obtain the circuit nodes’ toggle rate. The delay model for the logic gates is the real-delay model. To validate the results, the method is applied to several circuits and compared against exhaustive, as well as Monte Carlo, simulations. The proposed technique was shown to save up to 96% processing time compared to exhaustive simulation.

Fuzzy delay model based fault simulator for crosstalk delay fault test generation in asynchronous sequential circuits

In this paper, a fuzzy delay model based crosstalk delay fault simulator is proposed. As design trends move towards nanometer technologies, more number of new parameters affects the delay of the component. Fuzzy delay models are ideal for modelling the uncertainty found in the design and manufacturing steps. The fault simulator based on fuzzy delay detects unstable states, oscillations and non-confluence of settling states in asynchronous sequential circuits. The fuzzy delay model based fault simulator is used to validate the test patterns produced by Elitist Non-dominated sorting Genetic Algorithm (ENGA) based test generator, for detecting crosstalk delay faults in asynchronous sequential circuits. The multi-objective genetic algorithm, ENGA targets two objectives of maximizing fault coverage and minimizing number of transitions. Experimental results are tabulated for SIS benchmark circuits for three gate delay models, namely unit delay model, rise/fall delay model and fuzzy delay model. Experimental results indicate that test validation using fuzzy delay model is more accurate than unit delay model and rise/fall delay model.

Stochastic logical effort as a variation aware delay model to estimate timing yield

Considerable effort has been expended in the EDA community during the past decade in trying to cope with the so-called statistical timing problem. In this paper, we not only present a fast and approximate gate delay model called stochastic logical effort (SLE) to capture the effect of statistical parameter variations on the delay but also combine this model with a previously proposed transistor level smart Monte Carlo method to construct ISLE timing yield estimator. The results demonstrate that our approximate SLE model can capture the delay variations and ISLE achieves the same accuracy as the standard Monte Carlo estimator with a cost reduction of about 180×on the average for ISCAS’85 benchmark circuits and in the existence of both inter- and intra-die variations.

A gate-delay model focusing on current fluctuation over wide range of process–voltage–temperature variations

This paper proposes a gate-delay model suitable for timing analysis that takes into consideration wide-ranging process–voltage–temperature (PVT) variations. The proposed model translates an output-current fluctuation due to PVT variations into modifications of the output load and input waveform. After translation, any conventional model can compute delay taking into account PVT variations by using the modified output load and reshaped input waveform. Experimental results with 90- and 45-nm technologies demonstrate that the average error of the fall and rise delay estimation in single- and multi-stage gates was approximately 5% on average over a wide range of input slews, output loads, and PVT variations. The proposed model can be used in Monte Carlo STA (static timing analysis) in addition to corner-based timing analysis. It can be also used in statistical STA to calculate the sensitivities of delays to variation parameters on-the-fly even when the nominal operating condition changes as well.

High Speed Comparator for the Moduli {2&lt;sup&gt;&lt;i&gt;n&lt;/i&gt;&lt;/sup&gt;, 2&lt;sup&gt;&lt;i&gt;n&lt;/i&gt;&lt;/sup&gt;-1, 2&lt;sup&gt;&lt;i&gt;n&lt;/i&gt;&lt;/sup&gt;+1}

{2n, 2n-1, 2n+1} is one of the most commonly used moduli in residue number systems. In this express, we propose a novel comparator for the moduli {2n, 2n-1, 2n+1}. Based on the proposed architecture, we can design high speed comparator for the moduli {2n, 2n-1, 2n+1}, which is the fastest among all known comparators for the moduli {2n, 2n-1, 2n+1}. The performance of the proposed comparator is evaluated and compared with the earlier fast comparators for the moduli {2n, 2n-1, 2n+1}, based on a simple gate-count and gate-delay model. The proposed comparator can improve the state-of-art by 8% on the average in terms of area and 6% on the average in terms of performance delay.

Modified Booth encoding modulo (2&lt;i&gt;&lt;sup&gt;n&lt;/sup&gt;&lt;/i&gt;-1) multipliers

(2n-1) is one of the most commonly used moduli in Residue Number Systems. In this express, we propose a novel Booth encoding architecture. Based on the proposed Booth encoding architecture, we can design high speed and high-efficient modulo (2n-1) multipliers, which are the fastest among all known modulo (2n-1) multipliers. The performance and the efficiency of the proposed multipliers are evaluated and compared with the earlier fastest modulo (2n-1) multipliers, based on a simple gate-count and gate-delay model. These results reveal that the proposed multipliers lead to average approximately 14% faster than the fastest known modulo (2n-1) multipliers.

On modeling the digital gate delay under process variation

To achieve a characterization method for the gate delay library used in block based statistical static timing analysis with neither unacceptably poor accuracy nor forbiddingly high cost, we found that general-purpose gate delay models are useful as intermediaries between the circuit simulation data and the gate delay models in required forms. In this work, two gate delay models for process variation considering different driving and loading conditions are proposed. From the testing results, these two models, especially the one that combines effective dimension reduction (EDR) from statistics society with comprehensive gate delay models, offer good accuracy with low characterization cost, and they are thus competent for use in statistical timing analysis (SSTA). In addition, these two models have their own value in other SSTA techniques.

SAT based timing analysis for fixed and rise/fall gate delay models

This paper proposes a SAT based technique for timing analysis by an accurate modeling of event propagation within gate-level circuits. The accuracy of the result depends on the level of detail with which circuit activity is modeled. However, the combinatorial blowup in the size and complexity of the problem is the main bottleneck in any detailed modeling. The proposed technique overcomes this problem by an efficient SAT modeling of events at the nodes of the circuit which scales very smoothly with increase in size of the circuit without sacrificing on accuracy even with industry standard gate delays of 0.01ns granularity. This improvement in performance enables the modeling of more complex gate delay models like the rise/fall delay model which can simulate circuit activity more realistically than the fixed gate delay model.

Fast Monte Carlo Estimation of Timing Yield With Importance Sampling and Transistor-Level Circuit Simulation

Considerable effort has been expended in the electronic design automation community in trying to cope with the statistical timing problem. Most of this effort has been aimed at generalizing the static timing analyzers to the statistical case. On the other hand, detailed transistor-level simulations of the critical paths in a circuit are usually performed at the final stage of performance verification. We describe a transistor-level Monte Carlo (MC) technique which makes final transistor-level timing verification practically feasible. The MC method is used as a golden reference in assessing the accuracy of other timing yield estimation techniques. However, it is generally believed that it can not be used in practice as it requires too many costly transistor-level simulations. We present a novel approach to constructing an improved MC estimator for timing yield which provides the same accuracy as standard MC but at a cost of much fewer transistor-level simulations. This improved estimator is based on a unique combination of a variance reduction technique, importance sampling, and a cheap but approximate gate delay model. The results we present demonstrate that our improved yield estimator achieves the same accuracy as standard MC at a cost reduction reaching several orders of magnitude.

Nested Sparse-grid Stochastic Collocation Method and Its Application to Gate Delay Modeling under Process Variations

In this paper,an extended Gaussian quadrature based nested sparse-grid stochastic collocation method(NSSCM) is proposed for further improving the computation accuracy and efficiency of stochastic gate delay modeling considering process variation.Firstly,the orthogonal polynomial bases in the stochastic space of gate parameters are employed in NSSCM to approximate the stochastic gate delay and exponential convergence rate is achieved.Secondly,the proposed NSSCM employs one-dimensional extended Gaussian quadrature points and sparse grid technique to construct the nested multidimensional collocation points.Compared with the existing non-nested sparse-grid stochastic collocation method(SSCM),the nested collocation points used in NSSCM not only maintain the high computation precision of Gaussian quadrature,but also have the nested property to guarantee that gate delays obtained at low order collocation points can be reused in high order quadrature.The reuse of collocation points can remarkably improve the computation accuracy and efficiency of gate delay modeling.Experimental results demonstrated the merits of the proposed method.