Gate-channel Capacitance Research Articles

Novel extraction method for contact resistance and effective mobility in carbon nanotube field-effect transistors using S-parameter measurements

In this paper, a novel method is presented for the accurate extraction of key parameters of carbon nanotube field-effect transistors (CNTFETs) using S-parameter measurements. An equivalent circuit model, which utilizes lumped components based on the physical characteristics of the device, is employed to model the AC behavior (S-parameters) of the CNTFETs. The proposed method extracts the bias-dependent contact resistance, channel resistance, and gate-channel capacitance from the model at each gate voltage, thereby facilitating the extraction of the effective mobility of the CNT channel. At the last part of this paper, this method is used to quantitatively investigate the impact of electrostatic doping on CNTFETs. This new methodology offers an effective approach for characterizing CNTFETs, which is an important indicator for device optimization. Additionally, the proposed method can be easily applied to other types of FETs.

Study of threshold voltage extraction from room temperature down to 4.2 K on 28 nm FD-SOI CMOS technology

This paper aims to benchmark the threshold voltage extraction at cryogenic temperature. It presents two DC and for the first time one RF methods to extract the threshold voltage down to 4.2 K for channel lengths down to 28 nm. Measurements are performed on CMOS transistors integrated in 28 nm Fully Depleted Silicon-On-Insulator (FDSOI). First, two methods based on DC measurement are explained: the constant-current and the second derivative technique. Besides, the gate-channel capacitance derivative method based on RF measurements is presented. Finally, we discuss and compare the advantages and limits of these different methods.

Electrolyte-gated transistors for synaptic electronics, neuromorphic computing, and adaptable biointerfacing

Functional emulation of biological synapses using electronic devices is regarded as the first step toward neuromorphic engineering and artificial neural networks (ANNs). Electrolyte-gated transistors (EGTs) are mixed ionic–electronic conductivity devices capable of efficient gate-channel capacitance coupling, biocompatibility, and flexible architectures. Electrolyte gating offers significant advantages for the realization of neuromorphic devices/architectures, including ultralow-voltage operation and the ability to form parallel-interconnected networks with minimal hardwired connectivity. In this review, the most recent developments in EGT-based electronics are introduced with their synaptic behaviors and detailed mechanisms, including short-/long-term plasticity, global regulation phenomena, lateral coupling between device terminals, and spatiotemporal correlated functions. Analog memory phenomena allow for the implementation of perceptron-based ANNs. Due to their mixed-conductivity phenomena, neuromorphic circuits based on EGTs allow for facile interfacing with biological environments. We also discuss the future challenges in implementing low power, high speed, and reliable neuromorphic computing for large-scale ANNs with these neuromorphic devices. The advancement of neuromorphic devices that rely on EGTs highlights the importance of this field for neuromorphic computing and for novel healthcare technologies in the form of adaptable or trainable biointerfacing.

Quantum-mechanical effect in atomically thin MoS2 FET

Two-dimensional (2D) layered materials-based field-effect transistors (FETs) are promising for ultimate scaled electron device applications because of the improved electrostatics to atomically thin body thickness. However, compared with the typical thickness of ~5 nm for Si-on-insulator (SOI), the advantage of the ultimate thickness limit of monolayer for the device performance has not been fully proved yet, especially for the on-state at the accumulation region. Here, we present much stronger quantum-mechanical effect at the accumulation region based on the C–V analysis for top-gate MoS2 FETs. The self-consistent calculation elucidated that the electrons are confined in the monolayer thickness, unlike in the triangle potential formed by the electric field for SOI, the gate-channel capacitance is ideally maximized to the gate insulator capacitance since the capacitive contribution of the channel can be neglected due to the negligible channel thickness. This quantum-mechanical effect agreed well with the experimental results. Therefore, monolayer 2D channels are suggested to be used to enhance the on-current as well as the gate modulation ability.

Study on effective MOSFET channel length extracted from gate capacitance

The effective channel length (LGCM) of metal–oxide–semiconductor field-effect transistors (MOSFETs) is extracted from the gate capacitances of actual-size MOSFETs, which are measured by charge-injection-induced-error-free charge-based capacitance measurement (CIEF CBCM). To accurately evaluate the capacitances between the gate and the channel of test MOSFETs, the parasitic capacitances are removed by using test MOSFETs having various channel sizes and a source/drain reference device. A strong linear relationship between the gate-channel capacitance and the design channel length is obtained, from which LGCM is extracted. It is found that LGCM is slightly less than the effective channel length (LCRM) extracted from the measured MOSFET drain current. The reason for this is discussed, and it is found that the capacitance between the gate electrode and the source and drain regions affects this extraction.

Terahertz signal detection in a short gate length field-effect transistor with a two-dimensional electron gas

We consider the problem of non-resonant detection of terahertz signals in a short gate length field-effect transistor having a two-dimensional electron channel with zero external bias between the source and the drain. The channel resistance, gate-channel capacitance, and quadratic nonlinearity parameter of the transistor during detection as a function of the gate bias voltage are studied. Characteristics of detection of the transistor connected in an antenna with real impedance are analyzed. The consideration is based on both a simple one-dimensional model of the transistor and allowance for the two-dimensional distribution of the electric field in the transistor structure. The results given by the different models are discussed.

An Improved Virtual-Source-Based Transport Model for Quasi-Ballistic Transistors—Part II: Experimental Verification

In the first part of this two-part paper, a revised MIT virtual-source (MVS)-based transport model, called MVS-2, is presented. The MVS-2 model captures the essential physics of quasi-ballistic nanotransistors by accounting for the effects of: 1) degeneracy on the thermal velocity and the mean free path of the carriers in the channel; 2) nonequilibrium transport conditions on the gate–channel capacitance; and 3) the conduction band nonparabolicity on the effective mass of the carriers. The formulation of the extrinsic device regions as nonlinear current-dependent resistances allows MVS-2 to describe the degradation in the device transconductance under high drain currents as measured experimentally in InGaAs quantum well HEMT devices. In this paper, we test the accuracy of the MVS-2 model by comparing the model results with the measured $I$ – $V$ data of the InGaAs HEMT devices with gate lengths from 30 to 130 nm and Si extremely thin silicon on insulator devices with gate lengths from 30 to 50 nm. We also discuss why at the expense of some physical rigor the basic MVS model can fit more simply the experimental data (except for the degradation in transconductance under high drain currents).

Improvement of S-factor method for evaluation of MOS interface state density

In this paper, the accuracy of the S-factor method for evaluating the energy distribution of density of interface states (Dit) at MOS interfaces is examined by device simulation. Based on the analysis, we propose an improved S-factor method including the accurate depletion layer capacitance (Cd) values as a function of gate voltage, determined by gate–substrate capacitance (Cgb) and gate–channel capacitance (Cgc), and a new term, proportion to S/φs, in the analytical formulation of the relationship between Dit and the S-factor. The accuracy of Dit in this improved method is also quantitatively studied through the simulation. The above modifications for the S-factor method allow us to accurately provide the energy distribution of Dit. It has been found that the accuracy of lower half of 1010 cm−2 eV−1 order can be obtained for Dit extracted by using the improved S-factor method.

Electron mobility extraction in triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5 nm

In this paper, we report the first systematic study on electron mobility extraction in equilateral triangular gate-all-around Si nanowire junctionless nMOSFETs with cross-section down to 5nm. 1×1019cm−3 n-type channel doping, 5–20nm Si nanowire width together with 2nm SiO2 gate oxide thickness were used in the quasistationary TCAD device simulations of 100nm long channel devices (VDS=100mV, T=300K). All the extensive studies were performed in strong accumulation regime, as a first step, using a constant electron mobility model (100cm2/Vs). The effects of non-uniform electron density due to corners and quantum confinement effects are investigated. Suppressing the bias-dependency of various key MOSFET parameters e.g. series resistance, by contact engineering, and the product of channel width and gate-channel capacitance, CWeff, by rounding the sharp corners, to improve the accuracy of mobility extraction in strong accumulation is addressed in details. A significant bias-dependent series resistance modulation is reported in GAA Si nanowire junctionless nMOSFETs, leading to a significant electron mobility extraction inaccuracy of ∼50% in strong accumulation regime.

Self-Induced Gate Dielectric for Graphene Field-Effect Transistor

We report the electronic characteristics of an avant-garde graphene-field-effect transistor (G-FETs) based on ZnO microwire as top-gate electrode with self-induced dielectric layer. Surface-adsorbed oxygen is wrapped up the ZnO microwire to provide high electrostatic gate-channel capacitance. This nonconventional device structure yields an on-current of 175 μA, on/off current ratio of 55, and a device mobility exceeding 1630 cm(2)/(V s) for holes and 1240 cm(2)/(V s) for electrons at room temperature. Self-induced gate dielectric process prevents G-FETs from impurity doping and defect formation in graphene lattice and facilitates the lithographic process. Performance degradation of G-FETs can be overcome by this avant-garde device structure.

Side-gate graphene field-effect transistors with high transconductance

We have fabricated epitaxial side-gate graphene field-effect transistors (FETs) with high transconductance. A side-gate graphene FET with 55 × 60 nm2 active channel dimensions and a lateral gate-channel separation of 95 nm showing a high transconductance of 590 mS/mm is presented. An estimation of the electrostatic gate-channel capacitance of epitaxial side-gate graphene FETs shows that it is in the same order as the electrostatic gate capacitance of common top-gate graphene MOSFETs justifying the high transconductances of our devices. The results of the present paper demonstrate the potential of the side-gate architecture for graphene transistors.

AlGaN/GaN Microwave Switch With Hybrid Slow and Fast Gate Design

We present a novel approach to reduce the off-state capacitance of microwave transistor switches. The new design includes a “slow gate” layer, which allows for complete depletion of the channel in the source-drain region, thus reducing the gate-channel capacitance. Due to very high impedance at high frequencies, the “slow gate” shunting effect and its own capacitance contributions are negligibly small. This novel approach is validated by demonstrating an AlGaN/GaN single-pole double-throw switch with the “slow gate” layer formed by InGaN film. The new gate design decreases the insertion loss of the fabricated switch by approximately 0.5 dB and increases the isolation by approximately 5 dB.

Impact of New Approach to Improve MOSFETs Performance with Ultrathin Gate Insulator

In this study, we focus on the difference behavior of the gate-channel capacitance (Cgc) characteristics in the inversion-mode (IM) and the accumulation-mode (AM) SOI MOSFETs. We experimentally demonstrate that the gate-channel capacitance in the AM MOS device is obviously larger than that in IM MOS device using the same gate insulator on the same wafer. The increase of the Cgc in AM MOSFETs is much more remarkable as downscaling the gate insulator due to the different inversion and accumulation layer quantization effect and poly-Si gate depletion effect. As the result, the current drivability has been obviously improved in the AM MOSFETs resulted from its vastly increased gate-channel capacitance, especially in the MOSFETs with the ultrathin gate insulator.

Parasitic Effects in Multi-Gate MOSFETs

In this paper, we have systematically investigated parasitic effects due to the gate and source-drain engineering in multi-gate transistors. The potential impact of high-K dielectrics on multi-gate MOSFETs (MuGFETs), such as FinFET, is evaluated through 2D and 3D device simulations over a wide range of proposed dielectric values. It is observed that introduction of high-K dielectrics will significantly degrade the short channel effects (SCEs), however a combination of oxide and high-K stack can effectively control this degradation. The degradation is mainly due to the increase in the internal fringe capacitance coupled with the decrease in gate-channel capacitance. From the circuit perspective, an optimum K value has been identified through mixed mode simulations. Further, as a part of this work, the importance of optimization of the shape of the spacer region is highlighted through full 3D simulations.

Inherent linearity in carbon nanotube field-effect transistors

The authors consider the suitability of carbon nanotubes for use in analog rf amplifiers, where the linearity of the device is critical. They show that in the limit of large electrostatic gate-channel capacitance, their theory predicts that an Ohmically contacted, ballistic carbon-nanotube-based field-effect transistor is inherently linear. While they have not achieved this limit in their experimental work, they compare the theory to experiment in the limit of small electrostatic gate-channel capacitance and find excellent agreement at virtually all bias conditions.

Hall Effect in the Accumulation Layers on the Surface of Organic Semiconductors

We have observed the Hall effect in the field-induced accumulation layer on the surface of single-crystal samples of a small-molecule organic semiconductor rubrene. The Hall mobility muH increases with decreasing temperature in both the intrinsic (high-temperature) and trap-dominated (low-temperature) conduction regimes. In the intrinsic regime, the density of mobile field-induced charge carriers extracted from the Hall measurements, nH, coincides with the density n calculated using the gate-channel capacitance and becomes smaller than n in the trap-dominated regime. The Hall data are consistent with the diffusive bandlike motion of field-induced charge carriers between trapping events.

Modeling the uniform transport in thin film SOI MOSFETs with a Monte-Carlo simulator for the 2D electron gas

In this paper, we present simulations of some of the most relevant transport properties of the inversion layer of ultra-thin film SOI devices with a self-consistent Monte-Carlo transport code for a confined electron gas. We show that size induced quantization not only decreases the low-field mobility (as experimentally found in [Uchida K, Koga J, Ohba R, Numata T, Takagi S. Experimental eidences of quantum-mechanical effects on low-field mobility, gate-channel capacitance and threshold voltage of ultrathin body SOI MOSFETs, IEEE IEDM Tech Dig 2001;633–6; Esseni D, Mastrapasqua M, Celler GK, Fiegna C, Selmi L, Sangiorgi E. Low field electron and hole mobility of SOI transistors fabricated on ultra-thin silicon films for deep sub-micron technology application. IEEE Trans Electron Dev 2001;48(12):2842–50; Esseni D, Mastrapasqua M, Celler GK, Fiegna C, Selmi L, Sangiorgi E, An experimental study of mobility enhancement in ultra-thin SOI transistors operated in double-gate mode, IEEE Trans Electron Dev 2003;50(3):802–8. [1–3]]), but also the electron saturation velocity and the carrier heating depend on the subband structure, and thus on the silicon film thickness.

Monte Carlo Simulation of Nanoscale SOI MOSFETs

A comparative review is presented of the current research on the quantum-mechanical and classical Monte Carlo simulation of SOI MOSFETs. A quantum-mechanical simulation method is proposed whereby the energy of transverse channel quantization is represented by a correction term. A newly developed simulation program, called BALSOI, is outlined. A comparison is made between the results of a 2D classical Monte Carlo simulation and those obtained by the quantum-mechanical method. It is observed that the differences are much smaller than what one might expect. This finding is explained as due to the considerable effect of the space charge, which is mainly governed by the classical, longitudinal motion of carriers through the channel. An analytical formula is derived for the effect of channel quantization on the gate–channel capacitance. The strength of tunneling current through a short-channel transistor in the off state is considered.

INSULATED GATE III-N HETEROSTRUCTURE FIELD-EFFECT TRANSISTORS

Unique materials properties of GaN -based semiconductors that make them promising for high-power high-temperature applications are high electron mobility and saturation velocity, high sheet carrier concentration at heterojunction interfaces, high breakdown field, and low thermal impedance (when grown over SiC or bulk AlN substrates). The chemical inertness of nitrides is another key property. An AlGaN / GaN Heterostructure Field Effect Transistor (HFET) has been a topic of intensive investigations since the first report in 1991 [1]. Several groups demonstrated high power operation of AlGaN / GaN HFETs at microwave frequencies [2,3,4], including a 100 W output power single chip amplifier developed by Cree, Inc. and devices with 100 GHz cut-off frequency reported in [5]. However, in spite of impressive achievements, the potential of nitride based HFETs has not been fully realized as yet. The RF powers expected from the fundamental properties of nitride based materials significantly exceed the experimental data. One of the key problems limiting the HFETs RF characteristics is high gate leakage currents causing DC and RF parameter degradation. When the gate voltage goes positive the forward leakage current shunts the gate-channel capacitance and thus limits the maximum device current. When the gate voltage is negative, high voltage drop between the gate and the drain causes premature breakdown and thus limits maximum applied drain voltage. In addition, gate leakage currents increase the device sub-threshold currents, which decrease the achievable amplitude of the RF output. These limitations become even more severe at high ambient temperatures. The characteristics of III-N HFETs can be considerably improved by implementing a new approach, which results from the demonstration of good quality of SiO 2/ AlGaN and Si 3 N 4/ AlGaN interfaces. This approach opens up a way to fabricate insulated gate heterostructure field-effect transistors (IGHFETs), which have the gate leakage currents several orders of magnitude below those of regular HFETs, and exhibit better linearity and higher channel saturation currents. In this chapter, we describe design, characterization and applications of these novel devices.

Gate-channel capacitance characteristics in the fully-depleted SOI MOSFET

A gate-channel capacitance minimum occurs in the capacitance-voltage (C-V) curve of a fully-depleted SOI MOSFET, when the front silicon surface is biased into accumulation while the back surface is maintained in strong inversion. This observation is explained in terms of a model based on the depletion width of the silicon film, taking into account the small accumulation and inversion layer thickness. A simple method is proposed to determine the flat-band potential in the SOI MOSFET.