Study of threshold voltage extraction from room temperature down to 4.2 K on 28 nm FD-SOI CMOS technology

Abstract

This paper aims to benchmark the threshold voltage extraction at cryogenic temperature. It presents two DC and for the first time one RF methods to extract the threshold voltage down to 4.2 K for channel lengths down to 28 nm. Measurements are performed on CMOS transistors integrated in 28 nm Fully Depleted Silicon-On-Insulator (FDSOI). First, two methods based on DC measurement are explained: the constant-current and the second derivative technique. Besides, the gate-channel capacitance derivative method based on RF measurements is presented. Finally, we discuss and compare the advantages and limits of these different methods.