Gate Bias Vg Research Articles

Spintronic device in SWCNT-FET configuration based on chromium oxides thin films consisting of half-metallic ferromagnetic CrO2

Spintronic device architectures consisting of ferromagnetic chromium oxide electrodes in single-walled carbon nanotubes field effect transistor (SWCNT-FET) configuration have been fabricated to act as strategic building blocks for next generation super-compact high-speed nanoelectronic devices for logic and memory operations. Stable thin films of chromium oxides consisting of half-metallic ferromagnetic chromium-di-oxide (CrO2) were pulsed laser deposited (PLD) over lattice-matched rutile-type-tetragonal intermediate TiO2 thin layers over thermally oxidized Si substrates for engineering of the spintronic device structure. Focused ion beam (FIB) milling was applied to the ferromagnetic chromium oxide thin films for patterning of the source (S) and (D) electrodes. Typical electrical characteristics derived by lnρ vs. T−1/2 plots confirmed spin-dependent transport (SDT) as the dominant mechanism of electrical conduction upto temperatures of ∼280 K along with negative magnetoresistance (MR) of ∼30 % at 278 K. Electrical characteristics (output and transfer) of the spintronic device structure were drawn under application of magnetic field (H) in out-of-plane geometry at the temperatures of 5.6 K, 250 K & 300 K. Drain current (Id) is demonstrated to be controlled effectively as a function of gate bias (Vg) for different fixed Vd-biases at all the device operating temperatures. Change in %MR as a function of gate voltage (Vg) was acquired at T = 250 &T = 300 K that displayed higher %MR change under out-of-plane geometry of applied field of 0.75 T of the spintronic device operation.

Record-Low Subthreshold-Swing Negative-Capacitance 2D Field-Effect Transistors.

Power consumption is one of the most challenging bottlenecks for complementary metal-oxide-semiconductor integration. Negative-capacitance field-effect transistors (NC-FETs) offer a promising platform to break the thermionic limit defined by the Boltzmann tyranny and architect energy-efficient devices. However, it is a great challenge to achieving ultralow-subthreshold-swing (SS) (10mV dec-1 ) and small-hysteresis NC-FETs simultaneously at room temperature, which has only been reported using the hafnium zirconium oxide system. Here, based on a ferroelectric LiNbO3 thin film with great spontaneous polarization, an ultralow-SS NC-FET with small hysteresis is designed. The LiNbO3 NC-FET platform exhibits a record-low SS of 4.97mV dec-1 with great repeatability due to the superior capacitance matching characteristic as evidenced by the negative differential resistance phenomenon. By modulating the structure and operating parameters (such as channel length (Lch ), drain-sourse bias (Vds ), and gate bias (Vg )) of devices, an optimized SS from ≈40 to ≈10mV dec-1 and hysteresis from ≈900 to ≈60mV are achieved simultaneously. The results provide a new potential method for future highly integrated electronic and optical integrated energy-efficient devices.

Gate‐Induced Massive and Reversible Phase Transition of VO2 Channels Using Solid‐State Proton Electrolytes

AbstractThe use of gate bias to control electronic phases in VO2, an archetypical correlated oxide, offers a powerful method to probe their underlying physics, as well as for the potential to develop novel electronic devices. Up to date, purely electrostatic gating in 3‐terminal devices with correlated channel shows the limited electrostatic gating efficiency due to insufficiently induced carrier density and short electrostatic screening length. Here massive and reversible conductance modulation is shown in a VO2 channel by applying gate bias VG at low voltage by a solid‐state proton (H+) conductor. By using porous silica to modulate H+ concentration in VO2, gate‐induced reversible insulator‐to‐metal (I‐to‐M) phase transition at low voltage, and unprecedented two‐step insulator‐to‐metal‐to‐insulator (I‐to‐M‐to‐I) phase transition at high voltage are shown. VG strongly and efficiently injects H+ into the VO2 channel without creating oxygen deficiencies; this H+‐induced electronic phase transition occurs by giant modulation (≈7%) of out‐of‐plane lattice parameters as a result of H+‐induced chemical expansion. The results clarify the role of H+ on the electronic state of the correlated phases, and demonstrate the potentials for electronic devices that use ionic/electronic coupling.

Modulation of Minority Carriers in the C-V Characteristics of MIS Tunneling Diode by Surrounding MOS Capacitor

From previous studies on MIS tunneling diode (MIS TD) with surrounding MOS capacitor devices, I-V characteristics of MIS TD changed when various gate voltages of surrounding device were applied. [1] [2] However, the C-V behavior hadn’t been discussed before. In this work, in order to understand the mechanism of carrier transportation, C-V measurement on MIS TD under low to high frequencies was practiced in the meantime of I-V measurement. From the different response of inversion charge to gate voltages and to frequencies, a new vision of minority carrier modulation by surrounding device is proposed in this letter. The device set under study is shown in Fig. 1, composed of an inner round-shaped MIS TD, and an outer circle of MOS capacitor device which fully surrounds the inner MIS TD; in addition to substrate, there were three terminals for each device set. The inner MIS TD was designed with a gate area of ~2.2x104 μm2 (radius 83.6 μm), and the spacing to the outer gate is 12.6 μm, which is defined by lithography and wet etch. With an equivalent oxide thicknesses (EOT) of 32A, the gate dielectric of inner and outer devices was both made of SiO2grown by anodized oxidation process at the same time on a P-type substrate. [3] In Fig. 2a and 2b show the I-V and C-V (at AC 1 kHz) characteristics of the inner MIS TD respectively (ITD-VTD and CTD-VTD), under various outer gate bias (Vg). Firstly, when Vg was biased at flat-band voltage of the outer device (black lines, Vg=VFB= -0.9V), the ITD saturated at ~5pA at positive VTD, because the substrate depleted and the minority carriers were limited due to absence of supply of electrons, also reflected in the low CTD at inversion side. As Vg changing to >VFB (-0.3V~+1V), the ITD at positive VTD increased significantly (~1000X of Vg= -0.9V at VTD 1.5V), and unlike the saturation behavior when Vg= -0.9V, ITD exponentially increased with greater VTD. Meanwhile, CTD-VTD of Fig. 2b showed more capacitance response at inversion side (blue line). These changes in I-V and C-V characteristics were explained by the appearance of excess minority carriers, which are believed to be supplied from the inversion layer under the outer gate (Vg > VFB). From multiple-frequency CTD-VTD in Fig. 2c, it was learned that enough time is still required for the minority carriers to response to VTD. Another device set with a thinner EOT of 22A was studied through similar I-V and C-V analyses. As Fig. 3b shows, unlike the device set with EOT 32A, the CTD-VTD response at inversion side for Vg>VFB disappeared. After checking the current flows among inner gate, outer gate and substrate, much greater gate leakage at outer device was found. The model proposed was that most of the electrons preferred directly tunneling through outer gate instead of diffusing to neighboring inner gate. As a result, a much less ITD change (~7X) as Vg switched from -0.9V to 0V than the device set with an EOT of 32A (~1000X), as shown in Fig. 3a. Moreover, even lower ITDat greater Vg= 1V also indicated that more serious direct tunneling at outer gate was taking away the supply of minority for inner MIS TD. In this work, the mechanism of Vg influence on ITD-VTD was modeled by the modulation of minority carriers through C-V and I-V analyses. To achieve higher ITDOn/Off ratio, besides the supply of minority carriers, the prevention of minority carriers leaking through the outer gate is essential as well. This work was supported by the Ministry of Science and Technology of Taiwan, ROC, under Contract No. MOST 105-2221-E-002-180-MY3.

Low frequency noise in tunneling field effect transistors

An analytical model is developed for the fluctuation of the electrostatic potential induced by a charged trap in the gate oxide in tunneling field effect transistor (TFET). The model is applied to get the fluctuation of the drain current induced by an interface trap in TFET. A low frequency noise model based on the current transportation through the tunneling and the channel is proposed. The dependency of the normalized power spectra SId/Id2 on the frequency f and the gate bias Vg for TFET is obtained. The noise spectra in TFET are found to be very different from those of conventional MOSFETs, and have the superposition of Lorentzian and 1/f lineshapes with the former associated with tunneling and the later with channel transportation. The potential and current models are compared with TCAD simulation. The calculated IdVg and the noise spectra are also compared with our experimental observations. The results show that the normalized spectra of the current noise due to the tunneling are more significantly affected by Vg than that due to the transportation through the channel. The results also show that the noise from the channel is dominated by the mobility fluctuation rather than the carrier number fluctuation.

Control of Grain Boundary Depletion Layer and Capacitance in ZnO Thin Film by a Gate with Electric Double Layer Dielectric

We report a comprehensive investigation of the impedance spectroscopy of nanostructured ZnO films with different morphologies used as channels in Thin Film Transistor configuration with a gate of Electric Double Layer dielectric. The different morphologies (achieved by growth on different types of substrates) range from films with grains of random orientations (grown on Si/SiO2) to films with nanocrystallites with strong texturing (grown on R-Sapphire and Kapton). The polymer electrolyte gate dielectric used enables a large carrier density at the ZnO interface in excess of 1013/cm2 even at a gate bias of 1 V. It has been shown that even with a moderate gate bias (Vg) of +3 V, the complex impedance can be severely suppressed, and the frequency characteristics of the impedance curves can be changed. Application of a negative gate bias similarly enhances the complex impedance. The observed data were explained as arising from control of the grain boundary depletion layer and the associated grain boundary capacitance (CGB) as well as the grain boundary potential barrier (φGB) by the field induced large charge density. We show that CGB can vary from a small value (large depletion width) when a negative Vg is applied to a large value (small depletion width) when the large majority charge density is induced by a positive gate bias.

Charge Saturation and Intrinsic Doping in Electrolyte-Gated Organic Semiconductors.

Electrolyte gating enables low voltage operation of organic thin film transistors, but little is known about the nature of the electrolyte/organic interface. Here we apply charge-modulation Fourier transform infrared spectroscopy, in conjunction with electrical measurements, on a model electrolyte gated organic semiconductor interface: single crystal rubrene/ion-gel. We provide spectroscopic signature for free-hole like carriers in the organic semiconductor and unambiguously show the presence of a high density of intrinsic doping of the free holes upon formation of the rubrene/ion-gel interface, without gate bias (Vg = 0 V). We explain this intrinsic doping as resulting from a thermodynamic driving force for the stabilization of free holes in the organic semiconductor by anions in the ion-gel. Spectroscopy also reveals the saturation of free-hole like carrier density at the rubrene/ion-gel interface at Vg < -0.5 V, which is commensurate with the negative transconductance seen in transistor measurements.

Electrical Properties of Solution Processed In-Ga-ZnO Thin Film Transistors with Multi-Stacked Active Layer.

In this study, we prepared solution-based In-Ga-ZnO thin film transistors (IGZO TFTs) having a multistacked active layer. The solution was prepared using an In:Zn = 1:1 mole ratio with variation in Ga content, and the TFTs were fabricated by stacking layers from the prepared solutions. After we measured the mobility of each stacked layer, the saturation mobility showed values of 0.8, 0.6 and 0.4 (cm2/Vs), with an overall decrease in electrical properties. The interface formed between the each layers affected the current path, resulting in reduced electrical performance. However, when the gate bias VG = 10 V was applied for 1500 s, the threshold voltage shift decreased in the stack. The uniformity of the active layer was improved in the stacked active layer by filling the hole formed during pre-baking, resulting in improved device stability. Also, the indium ratio was increased to enhance the mobility from 0.86 to 3.47. These results suggest high mobility and high stability devices can be produced with multistacked active layers.

Strong correlations elucidate the electronic structure and phase diagram of LaAlO3/SrTiO3 interface.

The interface between the two band insulators SrTiO3 and LaAlO3 has the unexpected properties of a two-dimensional electron gas. It is even superconducting with a transition temperature, Tc, that can be tuned using gate bias Vg, which controls the number of electrons added or removed from the interface. The gate bias–temperature (Vg, T) phase diagram is characterized by a dome-shaped region where superconductivity occurs, that is, Tc has a non-monotonic dependence on Vg, similar to many unconventional superconductors. Here, we report, the frequency of the quantum resistance-oscillations versus inverse magnetic field for various Vg. This frequency follows the same non-monotonic behaviour as Tc; a similar trend is seen in the low field limit of the Hall coefficient. We theoretically show that electronic correlations result in a non-monotonic population of the mobile band, which can account for the experimental behaviour of the normal transport properties and the superconducting dome.

Modulation of transport properties of optimally doped La1.85 Sr0.15 CuO4 thin films via electric field modification of the grain boundaries

Modulation of the transport properties of a superconducting La1.85Sr0.15CuO4-based ionic-liquid gated transistor has been achieved. For an applied gate bias Vg ≥ 2 V, the characteristic sheet resistivity vs. temperature (Rs–T) curves exhibit a fully reversible foot feature below the superconducting transition temperature (Tc). In contrast to the behaviour expected from the large charge carrier density of this high-Tc superconductor material, the normal state conductance above Tc also exhibits a large modulation, indicating a larger charge screening length than that predicted from a simple Thomas–Fermi model. We regard these changes as due to electrostatic modification of the charge density at structural imperfections such as grain boundaries present within the sample. Such modification alters the coupling between superconducting domains and dictates the overall Rs–T trend of the gated film. To explain our findings, we employ Mannhart's model of electronic band bending at the grain boundaries and propose that this band bending can be modulated by large electric fields resulting in the observed modulation of the transport properties of the device.

Fabrication and Characterisation of 1200V 4H-SiC VJFET

Results are presented for the silicon carbide (SiC) vertical channel junction field effect transistor (VJFET) fabricated based on in-house SiC epitaxial wafer suitable for power devices. We have demonstrated continuous improvement in blocking voltage, forward drain current under high temperature. The SiC VJFET device’s current density is 360 A/cm2 and current is 11 A at VG= 3 V and VD = 2 V, with related specific on-resistance 5.5 mΩ·cm2. The device exceeds 1200 V at gate bias VG = -10V. The current of the SiC VJFET device is 4 A and the reverse voltage is 1200V at the 200 °C high temperature.

Impact of substrate injected hot electrons on hot carrier degradation in a 180-nm NMOSFET

Although hot carriers induced degradation of NMOSFETs has been studied for decades, the role of hot electron in this process is still debated. In this paper, the additional substrate hot electrons have been intentionally injected into the oxide layer to analyze the role of hot electron in hot carrier degradation. The enhanced degradation and the decreased time exponent appear with the injected hot electrons increasing, the degradation increases from 21.80% to 62.00% and the time exponent decreases from 0.59 to 0.27 with Vb decreasing from 0 V to −4 V, at the same time, the recovery also becomes remarkable and which strongly depends on the post stress gate bias Vg. Based on the experimental results, more unrecovered interface traps are created by the additional injected hot electron from the breaking Si–H bond, but the oxide trapped negative charges do not increase after a rapid recovery.

Profiling of Border Traps at GeSn and High-K Oxide Interface

GeSn has emerged as an interesting channel material for beyond 14 nm node devices, in CMOS as well as TFET configurations [1-3]. However, the advantages of sub-60mV/decade subthreshold swing (SS) due to the increased band to band tunneling in small direct-bandgap tensile-strained GeSn and higher carrier mobilities are dwarfed by the presence of traps in the gate stack. For GeSn devices, Al or Hf based high-k dielectrics have been recognized as candidates for advanced gate stacks [4-6], where the presence of the interlayer oxide (IL) has shown to decrease the interface state density, Dit [7]. However, the border traps, known to be present in the vicinity of the GeSn/Oxide interface within a few nm, can exchange charge carriers with the underlying GeSn epitaxial layer via direct tunneling of injected charge, [8-9] thus reducing the mobility and increasing SS. A detailed characterization of these border traps has not been reported so far for GeSn gate stacks. In this work, two techniques, Fourier transform deep level transient spectroscopy (FT-DLTS) and temperature derivative admittance spectroscopy (TDAS) have been used to investigate the distribution of border traps in GeSn MOS capacitors.A 40 nm nominally thick compressively strained, un-intentionally doped Ge0.092Sn0.08 layer is grown using chemical vapor deposition on a thick Ge buffer layer on Si. The GeSn surface is baked at 5000C for 30 min to remove native oxide. A complete de-oxidation is confirmed by RHEED analysis. Plasma oxidation at 1500C is then carried out for 1 nm of GeSnOx IL formation, followed by 9 nm of Al2O3 deposition at -500C. Ni dots are deposited for gate contact, followed by forming gas anneal.A broad peak at higher temperatures (~235 K) was observed in conventional FT-DLTS measurements, when MOS capacitors are pulsed from depletion (Ur=2V) to accumulation (Up=-1.5V) as shown in Figure 1a. This peak originates from traps present at the oxide interface and is absent when the device is pulsed from deep depletion to depletion (positive pulse bias). The peak corresponds to a maximum in energetic distribution of border traps, found to be present at (ΔEa = 0.36± 0.02 eV) from the valence band edge (figure 1b). The capture kinetics is studied by means of pulse filling measurement using isothermal DLTS, which exhibits an s-shaped profile. A capture cross-section, σp of ~5e-17 /cm2 is estimated. With an assumption of all states being unoccupied or occupied at the beginning of the trap filling process, the density of border trap, the tunneling depth of the traps in the oxide and the trap energy are determined. Similar results are obtained for Al2O3/GeO2/GeSn capacitors.Figure 1: (a) Conventional FT-DLTS Spectrum at quiescent reverse bias (Ur) of 2 V, trap filling pulse duration (Tp) of 100 µs, emission period width (Tw) of 51.2 ms and varying filling pulse amplitude(Up). The solid curve shows de-convoluted peaks with a Gaussian distribution for the curve corresponding to Up = -1 V. The peak at ~235K corresponds to border traps with a background distribution. The peaks at lower temperature represent bulk traps in GeSn/Ge epitaxial layers[10]. (b) Temperature derivative Admittance spectrum [11], at gate bias(Vg) of -1V. An Arrhenius plot of ln(ωpeak/T2) vs 1/kT is used to obtain activation energy of 0.36 eV from the valence band edge where ωpeak is the frequency at peak position and k is the Boltzmann constant. In conclusion, FT-DLTS and TDAS of MOS capacitors on GeSn epitaxial layers are used to study the frequency and temperature dispersion observed in the accumulation region of capacitance curves. The results are described by means of the assumption of spatially and energetically distributed states, present in the depth of the oxide which interact by tunneling and thermally activated transitions of carriers.[1] S. Wirths et al., Appl. Phys. Lett. 102, 192103(2013). [2] S. Gupta et al., VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012.[3] Y. Yang et al., Electron Devices Meeting (IEDM), 2012 IEEE International. IEEE, 2012.[4] Y. Yang et al., Electron Devices, IEEE Transactions on 60.12 (2013): 4048-4056.[5] S. Gupta et al., Electron Devices Meeting (IEDM), 2012 IEEE International. IEEE, 2012.[6] X. Gong et al., VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012.[7] M. Zhao et al., Appl. Phys. Lett., APL 102.14 (2013): 142906.[8] H. D. Lakhdari et al., Physical Review B, 38.18 (1988): 13124.[9] P. Van Staa et al., J. Appl. Phys., JAP 54.7 (1983): 4014-4021.[10] S. Gupta et al., ECS Transactions 53.1 (2013): 251-258.[11] V. Jian Li et al., J. Appl. Phys., JAP 109.8 (2011): 083701.

Low-frequency noise in amorphous indium–gallium–zinc oxide thin-film transistors with an inverse staggered structure and an SiO2 gate insulator

We report the low-frequency noise (LFN) behavior of amorphous indium–gallium–zinc oxide thin-film transistors with an inverse staggered structure and an SiO2 gate insulator. The normalized noise power spectral density depended on channel length, L, with the form 1/L2, and on the gate bias voltage, VG, and threshold voltage, VTH, with the form 1/(VG − VTH)β where 1.5 < β < 2.1. In addition, the scattering constant α was less than 105 Ω. These results suggest that the contact resistance has a significant role in the LFN behavior and the charge-carrier density fluctuation is the dominant origin of LFN.

Simulation, Fabrication and Characterization of 4500V 4H-SiC Normally-Off VJFET

Simulation, Fabrication and characteristics of high voltage, normally-off JFETs in 4H-SiC are presented. The devices were built on ND= 1.01015 cm-3 doped 50μm thick n-type epilayer grown on a n+ 4H-SiC. Parameters of edge termination have been optimized by simulations. Its blocking voltage exceeds 4500V at gate bias VG = -6V and forward drain current is in excess of 3A at gate bias VG = 3V and drain bias VD = 5V corresponding a current density of 80A/cm2.

Characteristics of gate-modulated generation current under the reverse substrate bias in nano-nMOSFET

The characteristics of gate-modulated generation (GMG) current IGMG in nano-scale LDD nMOSFET under the reverse substrate bias VB are investigated. It is found that the rising and falling edges of IGMG curve shift rightwards as |VB| increases. On the basis of experimental and theoretical analysis, the physical mechanism behind this shift phenomenon is attained. The shift phenomenon is ascribed from the fact that VB modulates the proportion of surface potential φs in the gate bias VG. φs decreases with |VB| increasing under a certain VG, and consequently the maximum generation factor of the rising edge (gr) diminishes and that of the falling edge (gf) augments. Further, it is found that the transconductance peaks of the rising edge (GMR) and falling edge (GMF) increase with |VB| increasing. Moreover, GMR and GMF both have the linear relationship with VB in log coordinate. Due to the different roles of drain bias VD on the rising and falling edge of IGMG curve, GMR keeps constant but GMF varies under different values of VD. Increasing VD can enhance the change of gf with VG, there by increasing GMF under a given VB. Also, this results in the fact that the trend of GMF increasing with |VB| increasing slows down under a larger VD: the slop of GMF-VB curve decreases from 0.09 to 0.03 as VD increases from 0.2 to 0.6 V.

Progress of High Voltage Trenched and Implanted 4H-SiC Vertical JFET

A silicon carbide (SiC) vertical channel junction field effect transistor (VJFET) was fabricated based on in-house SiC epitaxial wafer with trenched and implanted method. Its forward drain current is in excess of 3.12 A (170 W/cm2) with a current gain of ID/IG = 19746 at gate bias VG = 3 V and drain bias VD = 5.5 V. The SiC VJFET device’s related specific on-resistance 54 mΩ·cm2. The BV gain is 250 V with Vg from -10 V to -4 V and is 350 V with Vg from -4 V to -2 V. Self-aligned floating guard rings provide edge termination that blocks 3180V at a gate bias of ?14 V and a drain-current density of 1.53 mA/cm2.

5A 1300V Trenched and Implanted 4H-SiC Vertical JFET

A silicon carbide (SiC) vertical channel junction field effect transistor (VJFET) was fabricated based on in-house SiC epitaxial wafer with lift-off trenched and implanted method. Its blocking voltage exceeds 1300V at gate bias VG = -6V and forward drain current is in excess of 5A at gate bias VG = 3V and drain bias VD = 3V. The SiC VJFET device’s current density is 240A/cm2 at VG= 3V and VD = 3V, with related specific on-resistance 8.9mΩ•cm2. Further analysis reveals that the on-resistance depends greatly on ohmic contact resistance and the bonding spun gold. The specific on-resistance can be further reduced by improving the doping concentration of SiC channel epilayer and the device’s ohmic contact.

Analysis of Resistance Asymmetry Due to p-n Junctions in Graphene FETs

AbstractFor graphene FETs, asymmetry in the drain current transfer characteristics has been observed. It has been proposed that asymmetry is due to additional resistances from p-n transition regions along the channel [1,2]. Calculations of the additional resistance have been received attention for small p-n transition lengths [3,4]. In this paper, we analyze the resistance of graphene FETs with p-n junctions when transition lengths are long compared with energy and momentum relaxation lengths, as is found in many experimental FETs. We employ a two dimensional device simulator to determine the electric field and channel conductivity variations in the vicinity of the FET gate, assuming rapid electron/hole equilibration. The simulations show added resistances in the range of 50-500 Ω μm p-n junction. We also extract the additional p-n resistance ΔR from experimental results by plots of Vd/Id vs. 1/|Vg-Vt|. Values of ΔR of order 450 Ω μm were extracted from FET results reported in [2]. Epitaxial graphene FETs fabricated on a SiC substrate [5] gives additional resistance of 620 Ωum. Both results are in reasonable agreement with the simulations.The physically-based device simulator Atlas of Silvaco with parameters modified for graphene was used to obtain carrier distributions. A graphene FET on SiO2 substrate with a global back gate and 0.3μm gate/drain and gate/source gaps was studied. The carrier density in the gap region was controlled by back gate bias (Vbg) while the channel region under the top gate was modulated by top and back gate simultaneously. A long channel device at Vds=10mV was used to minimize the lateral electric field effect.From the simulated carrier distribution, we can obtain the resistivity along the channel by ρ=1/[qμ(n+p)]. Mobility is assumed to be equal for electrons and holes, and depends on carrier concentration Ns, μ=μ0 (N0/Ns)1/2 where N0 and μ0 are intrinsic carrier concentration and peak mobility, respectively. Under positive Vbg, the graphene layer becomes n-type in the gap region and channel region. Proper top gate bias (Vg) may be applied to make channel region intrinsic, p-type or n-type. Therefore, various configurations along the channel such as npn or nnn structures may be created. In the p-n transition region, the total number of carriers reduces to N0 and resistivity shows a peak. The additional resistance of a p-n junction can be calculated by integrating the difference of the resistivity vs. channel position for the nnn and npn structures. The integrated resistance value is impacted by the peak height and peak width. The peak height is controlled by Vg-Vt; the resistivity reaches a maximum at the threshold condition, where the electron and hole densities reach their intrinsic levels. The peak width is also controlled by Vg, via fringing field of the gate.

Actions of negative bias temperature instability (NBTI) and hot carriers in ultra-deep submicron p-channel metal–oxide–semiconductor field-effect transistors (PMOSFETs)

Hot carrier injection (HCI) at high temperatures and different values of gate bias Vg has been performed in order to study the actions of negative bias temperature instability (NBTI) and hot carriers. Hot-carrier-stress-induced damage at Vg = Vd, where Vd is the voltage of the transistor drain, increases as temperature rises, contrary to conventional hot carrier behaviour, which is identified as being related to the NBTI. A comparison between the actions of NBTI and hot carriers at low and high gate voltages shows that the damage behaviours are quite different: the low gate voltage stress results in an increase in transconductance, while the NBTI-dominated high gate voltage and high temperature stress causes a decrease in transconductance. It is concluded that this can be a major source of hot carrier damage at elevated temperatures and high gate voltage stressing of p-channel metal–oxide–semiconductor field-effect transistors (PMOSFETs). We demonstrate a novel mode of NBTI-enhanced hot carrier degradation in PMOSFETs. A novel method to decouple the actions of NBTI from that of hot carriers is also presented.