Abstract
Simulation, Fabrication and characteristics of high voltage, normally-off JFETs in 4H-SiC are presented. The devices were built on ND= 1.01015 cm-3 doped 50μm thick n-type epilayer grown on a n+ 4H-SiC. Parameters of edge termination have been optimized by simulations. Its blocking voltage exceeds 4500V at gate bias VG = -6V and forward drain current is in excess of 3A at gate bias VG = 3V and drain bias VD = 5V corresponding a current density of 80A/cm2.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
