Abstract
Simulation, Fabrication and characteristics of high voltage, normally-off JFETs in 4H-SiC are presented. The devices were built on ND= 1.01015 cm-3 doped 50μm thick n-type epilayer grown on a n+ 4H-SiC. Parameters of edge termination have been optimized by simulations. Its blocking voltage exceeds 4500V at gate bias VG = -6V and forward drain current is in excess of 3A at gate bias VG = 3V and drain bias VD = 5V corresponding a current density of 80A/cm2.
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