Gate Bias Conditions Research Articles

Study of Organic Thin-Film Transistors Under Electrostatic Discharge Stresses

Low-voltage pentacene-based organic thin-film transistors (OTFTs) are characterized for the first time under the electrostatic discharge (ESD) stresses. The measurements are conducted using the transmission line pulsing (TLP) tester which generates the human body model equivalent pulses. The ESD behaviors and tolerances of OTFTs having different dimensions and gate biasing conditions are investigated. OTFT's failure mechanism and dc performance degradation due to the ESD stresses are also studied.

Split-Gate-Structure 1T DRAM for Retention Characteristic Improvement

As the feature size of the conventional 1T-1C DRAM scales down, difficulties of the fabrication process are increasing and it is becoming harder to keep a constant capacitance value for data storage. Capacitor-less 1T DRAM is a promising candidate for the substitution of the conventional 1T-1C DRAM, but its poor retention time is one of the critical issues in its commercialization. In the selection of a bias condition for 1T DRAM, however, it is impossible to choose a gate bias condition that is suitable for both the "1" and "0" hold state data. In this paper, a split gate structure and hold bias scheme are proposed for the simultaneous improvement of the "1" and "0" data retention characteristics. It was confirmed through numerical simulation that this structure has a more than 3 sec retention time. A vertical gate-all-around split-gate structure and its fabrication method are also suggested to achieve high density, low cost, a higher sensing margin, and a longer retention time.

Characteristics of Schottky barrier silicon nanocluster floating gate flash memory

The silicon nanocluster floating gate memory device based on the Schottky barrier metal-oxide-semiconductor field effect transistor (SB-MOSFET) was proposed. The silicon nanoclusters were formed via the digital gas-feeding low pressure chemical vapor deposition. Erbium silicide process was used to form the Schottky junctions at the source/drain. In addition to the SB-MOSFET operation, the program/erase times of the nonvolatile memory device were determined to be 10 ms and 100 ms under the + 18 and − 18 V gate bias conditions, respectively. Maximum memory window was 5.5 V and the charge retention characteristics were maintained with a memory window of 0.5 V at 10 6 s.

Novel Multiple-Channel Polycrystalline Silicon Thin-Film Transistors Employing Asymmetric Spacing

A novel multiple-channel structure that improves the reliability of polycrystalline silicon thin-film transistors (poly-Si TFTs) employing the sequential lateral solidification (SLS) process under high gate and drain bias stress was proposed and fabricated without any additional processes. It was successfully verified that the proposed asymmetric-spacing (AS) multiple-channel TFT effectively suppressed the threshold voltage shift by about 47% and reduced the mobility variation of the poly-Si TFT by about 3% compared with those of a conventional device by using a larger spacing in the central region of the channel area. This is possibly due to the emission of induced heat inside the device during operation. Our experimental results show that the proposed AS multiple-channel TFT has more stable electrical characteristics than the conventional-structure TFT under a high gate and drain bias condition.

Diamond MOSFET: An innovative layout to improve performance of ICs

A new planar MOSFET structure is proposed through a simple layout change, which modifies the gate geometric shape from rectangular to hexagonal in order to use the “corner effect concept” to enhance the resultant longitudinal (parallel) electric field, drift velocity of mobile carriers in the channel, drain current, transconductance, Early voltage and on-resistance in comparison to the equivalent conventional parameters. This paper is conceptual and performs a comparative analyzes between conventional and Diamond Partially-Depleted SOI nMOSFETs by 3D numerical simulations to understand the advantages and disadvantages of this innovative device compared to the conventional counterpart, keeping the same gate area, geometric factor and bias conditions. A simple analytical model for the drain current was proposed and tested for the Diamond transistor. Since we found better results of the Diamond SOI nMOSFETs we believe that, this innovative layout can be a new alternative for analog and digital integrated circuit applications for whatever area it may be needed, without any extra burden to the current technology. This layout approach can also be applied for any planar or 3D transistors technologies.

Optoelectronic Mixer Based on Composite Transparent Gate InAlAs–InGaAs Metamorphic HEMTs

In this study, sputtered indium-tin-oxide (ITO) formed ITO/Au/ITO was used to form composite transparent gate InAlAs-InGaAs metamorphic HEMTs (CTG-MHEMT), with an optoelectronic mixer significantly markedly improved front-side optical coupling efficiency. The proposed CTG-MHEMT exhibits a high responsivity (λ = 1310 nm) of 1.71 A/W under optimal bias conditions. A -3 dB electrical bandwidth of 400 MHz is produced by the photovoltaic effect and dominated by the long lifetime of the excess holes. The -3 dB electrical bandwidth associated with the photoconductive effect is 2.3 GHz, and is determined mainly by the short electron life time. A power gain cut-off frequency (fmax) of CTG-MHEMT of 18.2 GHz was achieved. This value, is much larger than that of TG-MHEMT (14.6 GHz) because Au nano particles improved the gate resistance. The optoelectronic mixing efficiency was enhanced by tuning the gate bias conditions. The CTG-MHEMT optoelectronic mixer is a cost-effective device, and based on the optical and electrical characteristics, is a promising candidate for simplifying the system architecture in fiber-optic microwave transmission applications.

Reduction of RTS Noise in Small-Area MOSFETs Under Switched Bias Conditions and Forward Substrate Bias

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Low-frequency noise in small-area MOSFETs is dominated by random telegraph signal noise associated to the capture and emission of charge carriers by a single trap located in the gate dielectric. RTS noise degrades the performance of analog, digital, and memory circuits. In this paper, we present measurements and simulations of RTS noise in small-area MOSFETs under constant bias and switched gate bias conditions in order to investigate the impact of substrate bias on RTS noise. Our results show that a strong reduction of RTS noise under switching bias conditions is obtained when a forward substrate bias is applied during the device <emphasis emphasistype="smcaps"> off</emphasis>-state. Measurement of RTS mean emission and capture times proves that such a reduction of RTS noise is caused by a significant decrease in emission time constant occurring when a low gate voltage and a positive substrate voltage are simultaneously applied in the frame of a switching bias scheme. </para>

Modeling of hetero-interface potential and threshold voltage for tied and separate nanoscale InAlAs– InGaAs symmetric double-gate HEMT

This paper presents an approximate solution of a 2-D Poisson’s equation in the channel region, based on physical correspondence between MOSFET and HEMT, with the approximation that the vertical channel potential distribution is a cubic function of position to study not only tied gate but separate gate bias conditions as well. An analytical expression for both front and back heterointerface potential is derived and threshold voltage is obtained iteratively from the proposed potential model. The threshold voltage behavior for tied and separated double-gate HEMT is investigated for various device dimensions. The back gate effect of the separated double gate HEMT is investigated for the depleted back channel only. The results obtained are verified by comparing them with simulated and experimental results.

Reduction of the Gate Leakage Current in Binary-trench-insulatedGate AlGaN/GaN High-electron-mobility Transistors

We propose a binary-trench-insulated (BTI) gate structure for reducing the gate leakage current without sacrifice of the transconductance in GaN high-electron-mobility transistors (HEMTs), and its physics-based simulation results are compared with conventional GaN HEMTs and metalinsulator-semiconductor high-electron-mobility-transistors (MIS-HEMTs) with Si3N4 insulators. The gate insulator of AlGaN/GaN BTI-HEMTs consists of two laterally contacting materials with dierent dielectric constants. The two parallel trench-insulators are composed of oxide and high-k dielectric materials of the same thickness and located within the AlGaN barrier layer. Simulation results clearly indicate that the gate leakage current in the proposed BTI-HEMT is significantly decreased by about two and six orders of magnitude compared to that of the conventional HEMT and MIS-HEMTs. In addition, we observe approximately 57.7% and 15.6% improvements in the maximum drain current density (ID,max) and 40.8% and 65.4% improvements in the maximum transconductance (gm,max) at zero gate bias condition, respectively, as compared to those of the conventional-HEMTs and MIS-HEMTs.

Noise Reduction in CMOS Circuits Through Switched Gate and Forward Substrate Bias

A new concept of noise reduction in CMOS circuits is presented taking advantage of a strong reduction of MOSFET low-frequency noise occurring under switched gate bias conditions and forward substrate bias. The effect of forward substrate bias on noise reduction is significantly larger in switched compared to constant gate bias conditions. Experimental results reveal that forward substrate bias is most effective when applied during the off-state of the transistor. A bias scheme adopting forward substrate bias only during the transistor off-state is suggested by the measurement results of transconductance efficiency gm/Id and intrinsic voltage gain gm/gds showing that these figures of merit are degraded when a forward substrate bias is applied during the on-state. As a first example exploiting the found noise reduction on circuit level, a 14 GHz pMOS VCO is presented. Our results show a significant reduction of close to carrier phase noise when a forward substrate bias is applied to the MOSFETs providing the negative conductance stage for the oscillation of the VCO. The outlined principles can be extended to other circuits and motivate new topologies and biasing schemes for analog and radio frequency CMOS circuits.

A comparison of ionizing radiation damage in CMOS devices from 60Co gamma rays, electrons and protons

Radiation hardened CC4007RH and non-radiation hardened CC4011 devices were irradiated using 60Co gamma rays, 1 MeV electrons and 1–9 MeV protons to compare the ionizing radiation damage of the gamma rays with the charged particles. For all devices examined, with experimental uncertainty, the radiation induced threshold voltage shifts (ΔVth) generated by 60Co gamma rays are equal to that of 1 MeV electron and 1–7 MeV proton radiation under 0 gate bias condition. Under 5 V gate bias condition, the distinction of threshold voltage shifts (ΔVth) generated by 60Co gamma rays and 1 MeV electrons irradiation are not large, and the radiation damage for protons below 9 MeV is always less than that of 60Co gamma rays. The lower energy the proton has, the less serious the radiation damage becomes.

FinFET domino logic with independent gate keepers

Scaling of single-gate MOSFET faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the sub-threshold and gate-oxide leakage currents. Double-gate FinFET technology mitigates these limitations by the excellent control over a thin silicon body by two electrically coupled gates. In this paper a variable threshold voltage keeper circuit technique using independent-gate FinFET technology is proposed for simultaneous power reduction and speed enhancement in domino logic circuits. The threshold voltage of a keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The optimum independent-gate keeper gate bias conditions are identified for achieving maximum savings in delay and power while maintaining identical noise immunity as compared to the standard tied-gate FinFET domino circuits. With the variable threshold voltage double-gate keeper circuit technique the evaluation speed is enhanced by up to 49% and the power consumption is reduced by up to 46% as compared to the standard domino logic circuits designed for similar noise margin in a 32nm FinFET technology.

Progressive degradation of TiN∕SiON and TiN∕HfO2 gate stack triple gate SOI nFinFETs subjected to electrical stress

In this contribution, the authors analyze first results about the impact of electrical stress on triple gate SOI nFinFETs with metal gate (TiN) and SiON or HfO2 gate dielectrics, with particular emphasis on the roles of fin width and back gate polarization. A similar progressive degradation of the characteristics is observed for both types of gate dielectric devices. An increasing degradation with reducing fin width is observed for a certain range of wide fin devices (between about 3μm and 130nm), which could be attributed to a higher contribution of corner effects or lower quality side surfaces. However, the narrowest triple gate FinFETs with geometries around the nominal values of this technology (70nm long and 30nm wide fins) show reduced degradation with electrical stress. Under the studied experimental conditions, no clear impact on device degradation is observed for different back gate bias conditions applied during electrical stress. A typical dielectric breakdown mode characterized by a sudden decrease in drain current, accompanied by a significant increase in front gate current, is observed quite often in devices subjected to strong or long stress conditions. From the analysis of the encountered postbreakdown source/drain asymmetries, it is inferred that most of such catastrophic failures under VFG=VD stress regime may correspond to gate-to-source dielectric breakdown.

A 1680-V (at 1 $\hbox{mA/cm}^{2}$) 54-A (at 780 $\hbox{W/cm}^{2}$) Normally ON 4H-SiC JFET With 0.143- $\hbox{cm}^{2}$ Active Area

A high-voltage normally ON 4H-SiC vertical junction field-effect transistor (VJFET) of 0.143- cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area was manufactured in seven photolithographic levels with no epitaxial regrowth and with a single masked ion-implantation event. The VJFET exhibits low gate-to-source p-n-junction leakage current with relatively sharp onset of breakdown. At a drain-current density of 1 mA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the VJFET blocks 1680 V at a gate bias of -24 V. A self-aligned floating guard-ring structure provides edge termination that blocks 77% of the 11.8-mum SiC drift layer's limit. At a gate bias of 2.5 V and a corresponding gate current of 2 mA, the VJFET outputs 53.6 A (375 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) at a forward drain voltage drop of 2.08 V (780 W/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ). The transistor current gain is <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ID</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IG</i> = 26 800, and the specific on-state resistance is 5.5 mOmegamiddotcm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . To our best knowledge, this is the largest area SiC vertical-channel JFET reported to date and outputs more drain current than any 1200-V class vertical-channel JFET under identical heat-load and gate biasing conditions.

트렌치 구조의 소스와 드레인 구조를 갖는 AlGaN/GaN HEMT의 DC 출력특성 전산모사

We present simulation results on DC characteristics of AlGaN/GaN HEMTs having trench shaped source/drain Ohmic electrodes. In order to reduce the contact resistance in the source and drain region of the conventional AlGaN/GaN HEMTs and thereby to increase their DC output power, we applied narrow-shaped-trench electrode schemes whose size varies from to to the standard AlGaN/GaN HEMT structure. As a result, we found that the drain current was increased by 13 % at the same gate bias condition and the transconductance (gm) was improved by 11 % for the proposed AlGaN/GaN HEMT, compared with those of the conventional AlGaN/GaN HEMTs.

Gate induced floating body effects in TiN/SiON and TiN/HfO 2 gate stack triple gate SOI nFinFETs

In this paper, the appearance of gate induced floating body effects in triple gate SOI nFinFETs with TiN/SiON and TiN/HfO 2 gate stacks is investigated. Different floating body effects (FBEs) are found to appear under moderate accumulation back gate bias ( V BG) conditions in devices with wide and long enough geometries. In particular, a second peak in the linear transconductance ( g mf), associated with electron valence band (EVB) direct tunneling, is observed in TiN/SiON devices for front gate voltages ( V FG) around 0.8 V. Interestingly, in spite of showing about two orders of magnitude lower total gate current, a second peak in g mf is also found in TiN/HfO 2 devices for V FG around 1.1 V. Under the accumulation V BG conditions in which FBEs are observed, front gate switch drain current ( I D) transients are also appreciated. Interestingly, a change in the shape of I D transients is observed for V FG conditions in which EVB majority carriers are injected into the floating fin. The I D transients, as well as the second peak of g mf and other FBEs, are found to gradually diminish for strong accumulation V BG conditions or reduced geometry dimensions.

A $\delta$-Doped InGaP/InGaAs pHEMT With Different Doping Profiles for Device-Linearity Improvement

In this paper, delta-doped InGaP/InGaAs pseudomorphic high-electron-mobility transistors (pHEMTs) with doping-profile modifications are investigated in order to improve the device linearity. The proposed modification was based on the third-order intermodulation distortion (IM3) and the third-order intercept point (IP3) analysis using a simple equivalent circuit of the devices. The correlations of the extrinsic transconductance (Gm) with IM3 and IP3 indicate that the flatness of Gm, as a function of gate-bias causes a lower IM3 level. On the other hand, a high Gm with a flatter Gm distribution results in higher IP3 value for the device. Therefore, doping modifications that improve the flatness of the Gm distribution will also improve the device linearity. Doping modifications in the Schottky layer (Schottky layer doped) and in the channel layer (channel doped) of the conventional delta-doped InGaP/InGaAs pHEMT were investigated. It was also found that extra doping, either in the channel region or in the Schottky layer, improved the flatness of the Gm distribution under different gate-bias conditions. This achieved a lower IM3 and a higher IP3 with a small sacrifice in the peak Gm value. The power performances of these devices were tested at different drain biases. Even though it had the lowest electron mobility among the three different types of devices studied, the channel-doped device demonstrated the best overall linearity performance, the highest IP3 value, the lowest IM3 level, and the best adjacent-channel power ratio under code-division multiple-access modulation.

Electrical stress on irradiated thin gate oxide partially depleted SOI nMOSFETs

The effect of hot-carrier stress on 60 MeV proton irradiated thin gate oxide partially depleted SOI nMOSFETs has been studied. The results are compared with those from the electrical stress of non-irradiated devices. Whereas no significant differences are observed for the front channel degradation, hot-electron trapping in the buried oxide is found to be enhanced in the irradiated devices. This hot-electron trapping leads to a compensation or neutralization of the effects caused by the radiation-induced positive trapped charges. It is shown that a similar hot-electron trapping enhancement can be achieved in non-irradiated devices stressed under certain back gate bias conditions.

NEGATIVE BIAS TEMPERATURE INSTABILITY IN TIN/HF-SILICATE BASED GATE STACKS

This work studies the effects of negative bias temperature instability (NBTI) on p-channel MOSFETS with TiN/HfSi x O y (20% SiO 2 based high-κ gate stacks under different gate bias and elevated temperature conditions. For low bias conditions, threshold voltage shift (ΔVT) is most probably due to the mixed degradation within the bulk high-κ. For moderately high bias conditions, H-species dissociation in the presence of holes and subsequent diffusion may be initially responsible for interface state and positively charged bulk trap generation. Initial time, temperature and oxide electric field dependence of ΔVT in our devices shows an excellent match with that of SiO 2 based devices, which is explained by reaction-diffusion (R-D) model of NBTI. Under high bias condition at elevated temperatures, due to higher Si - H bond-annealing/bond-breaking ratio, the experimentally observed absence of the impact ionization induced hot holes at the interfacial layer (IL)/ Si interface probably limits the interface state generation and ΔVT as they quickly reach saturation.

NBTI Effects in pMOSFETS with TiN/Hf-Silicate Based Gate Stacks

Effects of negative bias temperature instability (NBTI) on p-channel MOSFETS with TiN/HfSixOy (20% SiO2) based high-k gate stacks are studied under different gate bias and elevated temperature conditions. For low bias conditions, threshold voltage shift (Delta VT) is most probably due to the mixed degradation within the bulk high-k. For moderately high bias conditions, H-species dissociation in the presence of holes and subsequent diffusion may be initially responsible for interface state and positively charged bulk trap generation. Initial time, temperature and oxide electric field dependence of Delta VT in our devices conform to SiO2 based reaction-diffusion (R- D) model of NBTI. Under high bias condition at elevated temperatures higher Si-H bond-annealing/bond-breaking ratio, due to the experimentally observed absence of the impact ionization induced hot holes at the interracial layer (IL)/Si interface, probably limits the interface state generation and Delta VT as they quickly tend to saturate.