Gap-filling Capability Research Articles

Synthesis of Dilute Phosphorous-Embedded Co Alloy Films on a NiSi Substrate with a Superior Gap-Filling Capability for Nanoscale Interconnects

Nanoscale cobalt interconnection wire has a lower mean free path of electrons to reduce the electrical resistivity, therefore it has been increasingly studied as a promising interconnect material to replace the conventionally used copper in state-of-the-art nanoscale devices. This process further limits the space for barrier/seed layer deposition to conformally fill the narrow trenches/contact holes in nanoscale devices. Thus, an electrochemical approach not involving a conventional high-resistivity barrier is presented to study the gap-filling capability and properties of Co(P) films with a controlled composition on a NiSi substrate. Examining electrodeposited Co(P) films reveals that the composition is determined mainly by the deposition potential instead of the amount of NaH2PO2 in the electrolytes, yielding a film with a phosphorous concentration lower than 2.62 at.%. The lightly doped Co(P) film has an hexagonal close-packed Co structure with phosphorous atoms at the interstitial lattice site. A chronoamperometry study on the current transient during the electrochemical deposition indicates that NaH2PO2 addition can enhance the deposition of the Co(P) films. Hence, the Co(P) film developed here is capable of gap filling nanoscale trenches up to an aspect ratio of 5 and is practical as a contact plug material for NiSi in nanoscale devices.

A New Alternative Electrochemical Process for a Pre-Deposited UPD-Mn Mediated the Growth of Cu(Mn) Film by Controlling the Time during the Cu-SLRR

A layer-by-layer deposition is essential for fabricating the Cu interconnects in a nanoscale-sized microelectronics because the gap-filling capability limits the film deposition step coverage on trenches/vias. Conventional layer-by-layer electrochemical deposition of Cu typically works by using two electrolytes, i.e., a sacrificial Pb electrolyte and a Cu electrolyte. However, the use of a Pb electrolyte is known to cause environmental issues. This study presents an Mn monolayer, which mediated the electrochemical growth of Cu(Mn) film through a sequence of alternating an underpotential deposition (UPD) of Mn, replacing the conventionally used UPD-Pb, with a surface-limited redox replacement (SLRR) of Cu. The use of the sacrificial Mn monolayer uniquely provides redox replacement by Cu2+ owing to the standard reductive potential differences. Repeating the sequence of the UPD-Mn followed by the SLRR-Cu enables Cu(Mn) film growth in an atomic layer growth manner. Further, controlling the time of open circuit potential (OCP) during the Cu-SLRR yields a technique to control the content of the resultant Cu(Mn) film. A longer OCP time caused more replacement of the UPD-Mn by the Cu2+, thus resulting in a Cu(Mn) film with a higher Cu concentration. The proposed layer-by-layer growth method offers a wet, chemistry-based deposition capable of fabricating Cu interconnects without the use of the barrier layer and can be of interest in microelectronics.

Fast and scalable phase change materials Ti–Sb–Te deposited by plasma-enhanced atomic layer deposition

Current features of phase change memory (PCM) based on Ge2Sb2Te5 (GST) as a non-volatile memory is insufficient to meet the needs of storage class memory (SCM) such as extremely high-density, ultra-fast operating speed and long life cycle. In this study, Ti0.28Sb2Te3 (TST) device was fabricated based on atomic layer deposition (ALD) method and used as a phase change material. Due to the fast crystallization and low melting temperature of TST, the set speed can be reduced to 6 ns while the reset voltage can be decreased by 20% compared with GST-based device with the same cell structure. In addition, the ALD-deposited TST alloy showed a good gap-fill capability. These results indicate that the ALD-deposited TST film is a fast and scalable phase-change material applied to SCM.

Enhancing SWOT discharge assimilation through spatiotemporal correlations

The highly intermittent and sparse nature of the Surface Water and Ocean Topography (SWOT) river observations in both space and time poses a major challenge to users for most applications. While interpolation/assimilation efforts exist to assemble discrete SWOT river observations into a spatially complete and temporally continuous record, the efficacy of such efforts is severely compromised by large observation gaps. In this study, we introduced spatiotemporal error correlations in runoff fields into the Inverse Streamflow Routing (ISR) model to improve the gap-filling capability for creating continuous daily discharge. This enhanced ISR model was first investigated in the Ohio River basin, which showed very significant improvements with better reproduced spatial and temporal dynamics of the runoff fields and the discharge time series. Results using 25 validation gauges showed a more concentrated Kling-Gupta Efficiency distribution, where the median was improved from 0.494 to 0.750. The enhanced ISR model was further tested over 16 representative global river basins to verify the effectiveness and robustness of the proposed method. The best fitted e-fold correlation length and time leading to the greatest improvements varied largely among the 16 basins. While all basins benefitted from the spatiotemporal correlations in the SWOT gap-filling, basins suffering from poorer initial guess and fewer SWOT observations, such as the Dnieper, Kolyma and Murray basins, showed larger performance gains than others. Although the experiments were idealized and did not reflect all potential errors that may be present in a real-world application, we demonstrate that the utility of SWOT river products and their value in hydrologic sciences may be boosted by expanding a local/intermittent observation platform into a far-reaching source of hydrologic information through both river hydrodynamics in channel networks and spatiotemporal coherence of runoff errors.

Pattern Collapse-Free Drying with Sacrificial Gap Fill Polymers

This work discusses pattern collapse-free drying by application of a sacrificial polymer during the semiconductor wafer cleaning process. The sacrificial polymer is dispensed onto the wafer, displacing the rinse liquid and subsequently dried to form a solid polymer fill within the patterned structure, providing both mechanical support and a means for dry polymer removal by either plasma or thermal exposure. Polymer film thickness, gap fill capability and removal rate are explored for plasma ashable and thermally removable polymer families.

The improvement of MOSFET performance by the optimization of STI HDP-CVD integration process

The integration process of shallow trench isolation (STI) deposition was systematically investigated by using high-density plasma chemical vapor deposition (HDP-CVD). Two sputtering agents, Ar and H2, were utilized with various plasma RF power conditions. The STI HDP-CVD process consisted of two steps, including liner oxide and main gap-fill depositions. For the liner oxide deposition, the usage of Ar plasma was more favorable than H2 plasma because the drift of hydrogen-ions was detrimental for the electrical property of gate oxide. In the gap-fill process, H2 plasma with high bias RF power efficiently reduced plasma charging damage (PCD) on gate oxide due to its low sputtering rate and densely filled STI. The gap-fill capability and PCD were improved by the optimized condition of STI HDP-CVD process.

CHOOSING AN ADHESIVE FOR EXTERIOR WOODWORK THROUGH MECHANICAL TESTING

Through mechanical testing, an appropriate adhesive was found for reuniting the fragments of exterior wooden capitals. The adhesive needed to have superior weather resistance, flexibility, gap-filling capability, reversibility, longevity, and workability. From four different adhesive classes, a candidate adhesive was chosen for testing: Butvar B98 with granulated cork, ConServ Flexible Epoxy Patch 200, 3M Marine Adhesive Sealant 5200, DAP Dynaflex 230, and Dow Corning 738 Silicone Rubber with microballoons. The test program included cyclical tensile and compression tests, a uniaxial tensile test, and accelerated weathering. The Epoxy proved to be the most brittle, Butvar showed fatigue until failure, while 3M had excellent properties such as a low elastic modulus (high ductility), (visco)elastic behavior, and longevity. Both DAP and Dow Corning developed fissures in the paint prematurely and were eliminated from extensive cycling tests.

A Proprietary Chemical Bath Life Study in MHM ULK Scheme Wet Cleaning

As technology evolves to 45nm and beyond, IC companies adopt TiN metal hardmask instead of PR (photo resist) to gain better etching profile, CD uniformity and less low-k material damage. To improve Cu gap fill capability, an in situ TiN pull back is needed in the subsequential wet clean step. This pullback can be done by mixing some additive with clean media, like H2O2. But H2O2 tends to decompose along the time, it also bring the challenges to the wet clean media stability. In this paper, we study a proprietary wet clean chemical behavior with pH, Cu ion concentration, H2O2 additive and bath lifetime. Cu ions content is demonstrated critical to the mixture instability when H2O2 presents. Chemical degradation mechanism is also discussed.

PVD Copper Seed Queue Time Extension for 200mm TSV Application

This work studied queue time between PVD and ECD in a 200mm TSV application. The proposed new PVD condition successfully extended queue time from the original 2-4 hours to at least two weeks. The original PVD condition was found to produce a Cu seed orientation of primarily (200) Cu. This produced a very rough post-plating surface when post-PVD queue time exceeded four hours. The orientation (200) appears to affect gap-fill capability when queue time exceeded four hours. With the new PVD condition, Cu seed orientation was optimized to be primarily (111) Cu, which created a shiny and clear post-plating surface. As a result, the vias could be filled well as long as two weeks after PVD. Copper seed recrystallization and post-plating morphology were found to be sensitive to nitrogen content in the barrier and to the bias power during Cu seed formation.

Effective Approach for TSV Cu Plating Gap Fill Improvement

TSV (Through Silicon Via) is a new method for 3D technology (IC integration). Different chips can be connected with the Cu line through silicon substrate. Via area is so deep (usually 100-300um) that we need thicker barrier and seed layer. The Cu plating is the key step in TSV flow. But we suffered TSV void issue in TSV ECD (Electro Chemical Deposition ) process for TSV seed layer poor condition impact .It is important to understand how to improve TSV Cu plating gap fill capability in order to develop TSV technology. In this paper, the barrier and seed layer performance improvement in TSV Cu plating is introduced, and then an effective approach to improve the TSV plating gap fill capability is demonstrated.

Advanced PVD TiN for Metal Gate Application

High-κ metal gate is widely used for 32nm and beyond to enable scaling down of MOSFET geometry while improving device speed and gate leakage. This structure requires a good work function metal to tune Vt as well as a stable metal barrier to control inter-diffusion and interaction between the multiple metal gate layers. To meet the integration requirements of metal gate, it is very important to choose the proper metal thin film process. Its stability and excellent integration performance make TiN a good option for metal gate application, but the traditional PVD (physical vapor deposition) TiN process still faces issues, such as plasma damage and poor gap-fill capability. RFPVD (radio frequency physical vapor deposition) TiN has been developed for metal gate application. This paper presents studies of the film texture, density, and inter-diffusion base on different metal gate layers. MOSCAP (metal oxide silicon capacitor) tests showed that RF PVD TiN exhibits low Dit and device leakage. To meet the strict gap-fill requirement of the gate-last scheme, physical gap-fill performance of the high-pressure RF TiN process was checked. It achieved more than 60% bottom coverage and minimal sidewall coverage, allowing the electrode gap-fill window to be effectively enlarged.

Nano-scale gap filling and mechanism of deposit—etch—deposit process for phase-change material

Ge2Sb2Te5 gap filling is one of the key processes for phase-change random access memory manufacture. Physical vapor deposition is the mainstream method of Ge2Sb2Te5 film deposition due to its advantages of film quality, purity, and accurate composition control. However, the conventional physical vapor deposition process cannot meet the gap-filling requirement with the critical device dimension scaling down to 90 nm or below. In this study, we find that the deposit—etch—deposit process shows better gap-filling capability and scalability than the single-step deposition process, especially at the nano-scale critical dimension. The gap-filling mechanism of the deposit—etch—deposit process was briefly discussed. We also find that re-deposition of phase-change material from via the sidewall to via the bottom by argon ion bombardment during the etch step was a key ingredient for the final good gap filling. We achieve void-free gap filling of phase-change material on the 45-nm via the two-cycle deposit—etch—deposit process. We gain a rather comprehensive insight into the mechanism of deposit-etch-deposit process and propose a potential gap-filling solution for over 45-nm technology nodes for phase-change random access memory.

Filling of nanoscale holes with high aspect ratio by Cu electroplating using suspension of supercritical carbon dioxide in electrolyte with Cu particles

We reported filling of nanoscale holes with high aspect ratio by Cu electroplating with a supercritical carbon dioxide suspension (EP-SCS). The Cu film electrodeposited by the EP-SCS was smooth. The nanoscale holes with 70nm in diameter and aspect ratio of 2 and 5 can be filled by electrodeposited Cu with no voids and pinholes by the EP-SCS. Gap-filling capability of the EP-SCS is high for the nanoscale holes with high aspect ratio even when using Cu electrolyte originally designed to fill holes with 70nm diameter and aspect ratio 1 by conventional method.

Device Characteristics of a Ge-doped SbTe alloy for High-speed Phase-change Random Access Memory

We investigated the influence of phase-change materials on the device performance for low-power and high-speed phase-change random access memory (PCRAM). The Ge-doped SbTe (Ge-ST) alloy was used as a phase-change material and was compared with the conventional Ge2Sb2Te5 (GST225) alloy. An as-deposited Ge-ST film grown by using chemical vapor deposition had an amorphous phase which showed the superior gap-fill capability compared to as-deposited crystalline GST225. The crystallization time for the set operation was decreased to 80 ns, and the reset current reduced to 0.16 mA when Ge-ST was introduced in sub-40 nm a PCRAM. In addition, the Ge-ST alloy showed a good data retention property of 10 years guaranteed at 100 ◦C. These results will enable us to realize low-power and high-speed PCRAM devices beyond the sub-40 nm design rule.

Advanced HDP STI Gap-Fill Development in 65nm Logic Device

High density plasma chemical vapor deposition (HDP-CVD) has been proven to be a sucessful process for shallow trench isolation (STI) gap fill in advanced CMOS device fabrication. As CMOS technology nodes continue to shrink, STI gap-fill requirement become more and more challenging. To keep pace with the stringent requirements, a novel HDP gap-fill process - Integrated Proess Modulation (IPM) has been developed to fill these aggressive structures. IPM process, which is extending from Deposition - Etch - Deposition (DED) process, is made of a serial of deposition/etch cycles, which is one of techniques to keep trench open by using NF3-based plasma dry etch before the trench nearly closed by film deposition. Based on this process model, HDP gap-fill capability has been greatly extended to 65nm and beyond. This paper summarizes the STI gap-fill development and optimization work of IPM processes

Complete filling of 41 nm trench pattern using Cu seed layer deposited by SAM-modified electroless plating and electron-beam evaporation

To overcome the limitation of the sputtered Cu seed layer in electroplating of Cu interconnects imposed by the shadow effect, a new method for depositing a Cu seed layer on a 41 nm trench pattern based on combination of electroless plating (ELP) and electron-beam (E-Beam) evaporation was developed. A Cu seed layer formed by ELP alone was too thin to be used for electroplating due to its high resistivity. To solve this problem, an additional Cu layer was deposited on top of the trench by E-Beam evaporator to enhance the electrical conductivity of the Cu seed layer. The electrical resistivity of the resulting Cu layer was reduced to 4.8 μΩ cm, which was sufficient for the conductive seed layer for electroplating the 41 nm trench pattern. The gap-filling capability also improved and there were no voids or seams in the 41 nm trench pattern. The proposed method can be an effective solution for fabrication of a conductive seed layer to fill a 41 nm trench pattern by electroplating.

Competitive Adsorption Between Bis(3-sodiumsulfopropyl disulfide) and Polyalkylene Glycols on Copper Electroplating

In semiconductor copper (Cu) metallization, external organic additives including bis(3-sodiumsulfopropyl disulfide) (SPS) and polyalkylene glycols (PAG) are necessary and widely used to improve the gap-fill capability of Cu electroplating for high-aspect-ratio features. In this study, the interaction of SPS and PAG (SPS–PAG) in the electrolytes was investigated. The results not only show the antisuppression effects of SPS in the presence of PAG, but also indicate the competitive adsorption between SPS and PAG. The proposed mechanism is that when SPS–PAG are added to a plating bath, the Cu-electroplating rate is influenced by competing adsorptions of SPS–PAG and SPS, which disperses PAG species far away from the Cu surface to enhance electroplating rates. The elements (charge-transfer resistance, adsorption-layer resistance, and inductance) of the equivalent circuit simulated using the electrochemistry-impedance spectroscopy data also demonstrate the behavior of SPS–PAG competing reactions.

Investigation of Bis-(3-sodiumsulfopropyl disulfide) (SPS) Decomposition in a Copper-Electroplating Bath Using Mass Spectroscopy

Bis-(3-sodiumsulfopropyl disulfide) (SPS) is a well-known accelerator used to promote “bottom-up filling” in the semiconductor copper (Cu) electroplating process. However, the gap-filling capability and the defect performance of Cu electroplating are impacted as the SPS molecules are decomposed or oxidized. In this study, by-products generated from SPS decomposition and oxidation were identified and quantized using mass spectroscopy. It was found that 1,3-propanedisulfonic acid (PDS) was the most stable species among the SPS by-products. The PDS concentration increased with the increasing surface area of immersed Cu metals. The relationship between the consumption rate of SPS and the generation rate of PDS with different surface areas of Cu metals was particularly investigated. Furthermore, an equivalent circuit was developed and then examined using electrochemical impedance spectroscopy to characterize the properties of the aged bath with the decomposition of SPS.

Effect of bis-(3-sodiumsulfopropyl disulfide) byproducts on copper defects after chemical mechanical polishing

In the semiconductor metallization process, the superior gap-fill capability of copper (Cu) electroplating is mainly due to external additives, such as bis-(3-sodiumsulfopropyl disulfide) (SPS), which is used as an accelerator. This study demonstrates that the byproducts of SPS induced Cu defects after a chemical-mechanical-polishing (CMP) process. In conventional cyclic-voltammetric-stripping analysis, the byproducts generated from organic additives are very difficult to quantify. In this study, the authors used mass-spectrum analysis to quantify SPS byproducts and found that the SPS byproduct, 1,3-propanedisulfonic acid, correlated with the formation of Cu defects because it influenced the properties of electroplated Cu films and the chemical corrosion rate, then induced defects after the CMP process.

Low Temperature Silicon Nitride Deposition by Inductively Coupled Plasma CVD for GaAs Applications

In order to take advantage of silicon nitride films as an ILD layer on GaAs devices, the ICP CVD silicon nitride films were investigated by parametric study of effects of deposition parameters on the physical properties of silicon nitride film deposited in the range of 50 ~ 200oC temperature. Good quality of films could be achieved, including low moisture absorption, low H content (<15 at.%), good resistance to BOE etching (<50 Aå/min), smooth film surface (2.0 nm roughness), and reasonable film stress, as compared to the conventional PECVD nitride film, while the process temperature is much lower than the conventional PECVD process. This silicon nitride film was applied to the GaAs HBT device structure and showed very promising results of the gap-filling capability and planarization for next level of metallization. These results indicate the possibility of using the ICP CVD silicon nitride films as an ILD layer in the GaAs devices instead of polymer type dielectrics, which typically require a long cure time at high temperature of 300oC or higher.