GaN Metal-oxide-semiconductor Field-effect Transistors Research Articles

Extraction of gap states in AlSiO/AlN/GaN metal-oxide-semiconductor field-effect transistors using the multi-terminal capacitance–voltage method

Direct extraction of gap states from a metal-oxide-semiconductor field-effect transistor (MOSFET) in which inversion electrons and holes in a p-type body coexist is challenging. We demonstrate gap-state extraction in lateral-type GaN MOSFETs with high channel mobilities using multi-terminal capacitance–voltage (C–V) methods. The gate stack of the MOSFET was composed of AlSiO/AlN/p-type GaN formed on a p+/n+ GaN tunnel junction structure. The substrate electrode was short-circuited to a p-type body layer through the tunnel junction. The MOSFET was equipped with gate, source, drain, body, and substrate electrodes. When the gate was the high side and the other electrodes were the low side in the AC circuit, a V-shaped C–V curve was obtained because of electron inversion and hole accumulation. When the body/substrate electrodes were connected to the ground level (i.e., split C–V method), the inversion electrons between the gate and source/drain electrodes could be evaluated. We proposed a “reverse” split C–V method in which the source/drain electrodes are grounded and the body/substrate electrodes are connected to the low side. This method enabled extraction of gap states near the valence-band maximum of GaN, with exclusion of the overlap capacitance and the capacitance due to inversion electrons. The proposed method demonstrated overall gap states in the GaN MOSFET with a wide bandgap. The results suggest that hole traps with discrete energy levels caused negative bias instability (NBI) in the GaN MOSFET. Furthermore, NBI and discrete gap states were consistently suppressed by Mg doping at >1018 cm−3 into a p-type body.

(Invited) Characteristics of GaN/High-k Capacitors Under Positive Bias Stress

Vertical GaN-based trench gate metal-oxide-semiconductor field-effect transistors (MOSFETs) have been widely investigated to suppress leakage currents for applications associated with high power and high frequency. Various materials with high dielectric constant (High-k) such as Al2O3, HfO2, AlSiO x , HfSiO x , and HfAlOx have been studied as gate insulator to obtain high gm value of GaN MOSFET [1-6]. The structure of High-k gate insulator and interface between GaN and High-k is well known to affect characteristics of GaN MOS capacitor. An amorphous HfAlOx film could be fabricated by forming (HfO2)/(Al2O3) nanolaminate films via plasma-enhanced atomic layer deposition and post-deposition annealing at 800°C. Al2O3 and HfAlOx gate insulators with an amorphous structure found to exhibit superior fundamental electrical properties including no frequency dispersion, a high breakdown voltage and a low interface state density [3,5,6]. However, reliability characteristics under high voltage sweep and positive bias stress (PBS) conditions are not currently well understood.In this paper, we investigate flatband voltage (Vfb) shift of the Al2O3 and HfAlOx capacitors by varying effective electric field (Eeff) from Vfb under PBS. We also compare Vfb shift behavior among Al2O3, HfAlOx and reported High-k gate insulators.Here, to understand influence of the thermal budget at 800°C on electrical property, two n-GaN/Al2O3(10nm)/Pt MOS capacitors were prepared: One was fabricated by thermal budget at 300°C (AlO). The other was fabricated by the same capacitor fabrication process, with the GaN substrate annealed at 800°C before Al2O3 film deposition (Pre800C-AlO). To examine interface properties of the n-GaN/HfAlOx, n-GaN/interfacial layer (IL)/HfAlOx(10nm)/Pt capacitor with a 0.5nm-thick-Al2O3-IL (AlO/HfAlO) and a 0.5nm-thick-HfO2-IL (HfO/HfAlO) and without IL (HfAlO) were prepared.All High-k gate insulators had an amorphous structure. The k-values of Al2O3 and HfAlOx gate insulators estimated from C-V measurement were 8 and 17.2, respectively [3,6]. All capacitors exhibited the smooth J-Eeff properties due to an amorphous structure regardless of the 800°C pre-annealing of the GaN substrate and IL of HfAlOx case. All capacitors also exhibited no frequency dispersion in the range of 1k-1MHz. However, the Pre800C-AlO capacitor showed a large hump due to the electrical defects in the C-V curve. The Vfb shift behavior of the capacitor was examined by varing Eeff from Vfb of PBS. The Eeff was estimated from the applied voltage divided by capacitanc equivalent thickness. The Eeff from Vfb of Al2O3 and HfAlOx capacitors were varied from 4.1-8.7 and 6.5-15.4MVcm-1, respectively. The stress time was varied from 0 to 300s . The sweep voltage range of C-V measurement for obtaining Vfb in each stress time was always applied smaller than the PBS voltage. The positive Vfb shift was observed in all capacitors after PBS, indicating the presence of some electron trapping sites. The positive Vfb increased siginificantly up to a stress time of 10s, gradually increased up to 200s, and saturated above 200s in all Eeff from Vfb regions. The positive Vfb value of all capacitors reached to around 0.2V when the Eeff from Vfb was applied to 6.5MVcm-1 at 300s. Above 6.5MVcm-1, different Vfb shift profiles were observed for two Al2O3 and three HfAlOx capacitors. The positive Vfb value of the Al2O3 capacitors increased drastically to 0.5V as the Eeff from Vfb increased from 6.5 to 8.7MVcm-1. Furthermore, the Pre800C-AlO capacitor became larger Vfb shift than the AlO capacitor because the Pre800C-AlO capacitor is due to the introduction of some defects on the GaN surface by pre-annealing at 800°C. On the other hand, for the HfAlO, AlO/HfAlO and HfO/HfAlO capacitors, the positive Vfb shift value was suppressed to 0.3V even when the Eeff from Vfb was applied to 15.4 MVcm-1. Furthermore the Vfb shift showed similar behavior regardless of Al2O3- and HfO2-IL. Based on these experimental data, we conclude that the HfAlOx capacitors have a high reliability under PBS condition.This work was supported by the MEXT Program for Creation of Innovative Core Technology for Power Electronics Grant Number JPJ009777. This work was supported in part by JSPS KAKENHI Grant No. JP20H02189.[1] J. T. Asubar et al., J. Appl. Phys. 129, 121102 (2021). [2] Y. Ando et al., Appl. Phys. Lett. 117, 102102 (2020). [3] K. Yuge et al., Semicond. Sci. Technol. 34, 034001 (2019). [4] D. Kikuta et al., Appl. Phys. Express 13, 026504 (2020). [5] T. Nabatame et al., Appl. Phys. Express 12, 011009 (2019). [6] T. Nabatame et al., ECS Trans. 104 113 (2021).

Scaling limits of monolayer AlN and GaN MOSFETs

The shrinking of transistors to ultra-scale limits is in great demand to extend Moore’s law, where the search for proper alternative channel materials is significant. The III-V group compounds are regarded as post-Si candidates for their high electron mobility. Herein, we simulate the monolayer (ML) AlN and GaN metal–oxidesemiconductor field-effect transistors (MOSFETs) with ab initio quantum transport simulation to evaluate their scale limit. The ML AlN and GaN MOSFETs exhibit much better n-type performances than their p-type counterparts, and the n-type ML AlN (GaN) MOSFETs can surpass the International Roadmap for Device and Systems (IRDS, 2022 version) lower-power (LP) and high-performance (HP) target for the year 2028 even at gate length (Lg) of 3 and 2 nm, respectively. Encouragingly, the optimal n-type ML AlN (GaN) MOSFETs possess the highest (second-highest) Ion against all studied n-type ML MOSFETs and propel the Lg limit that outperforms the International Technology Roadmap for Semiconductors (ITRS, 2013 version) LP and HP targets to 2 and 1 (2) nm, respectively.

Ballistic transport in sub-10 nm monolayer planar GaN transistors for high-performance and low-power applications

With the constant scaling down of transistors, “More Moore” has put forward requirements for channel materials. Two-dimensional materials are considered as potential next-generation channel materials due to their unique physical properties. Herein, we study the ballistic transport characteristics of sub-10 nm monolayer (ML) planar GaN metal–oxide–semiconductor field-effect transistors (MOSFETs) based on density functional theory and the non-equilibrium Green's function method. The calculation results indicate that n-type ML planar GaN MOSFETs with gate lengths not less than 5 nm exhibit excellent subthreshold characteristics, fast switching speeds, and low switching energies, and the corresponding parameters (off-current, on-current, delay time, and power-delay product) can simultaneously meet the requirements of the International Roadmap for Devices and Systems for the 2028 horizon for high-performance and low-power applications. Therefore, ML planar GaN is predicted to be a reliable next-generation channel material to extend Moore's law.

Defect-free interface between amorphous (Al2O3)1−x(SiO2)x and GaN(0001) revealed by first-principles simulated annealing technique

We report first-principles molecular dynamics (MD) simulations that unveil the interface structures of amorphous mixed oxide (Al2O3)1−x(SiO2)x and GaN polar surfaces. The MD allows us to perform the melt and quench (simulated annealing) simulations to forge distinct amorphous samples. We find that the dangling bonds are completely absent at all the obtained interfaces. This annihilation is due to the diffusion of appropriate species, O for (Al2O3)1−x(SiO2)x/GaN(0001) and Al and Si for (Al2O3)1−x(SiO2)x/GaN(0001¯), from the amorphous to the interface and the subsequent formation of strong bonds with both ionicity and covalency at the interface. This absence of the dangling bond indicates the superiority of (Al2O3)1−x(SiO2)x films to Al2O3 or SiO2 as a gate oxide for the GaN–metal–oxide–semiconductor field effect transistor.

Investigation on threshold voltage of p-channel GaN MOSFETs based on p-GaN/AlGaN/GaN heterostructure* *Project supported by the Key-Area Research and Development Program of Guangdong Province, China (Grant Nos. 2020B010174001 and 2020B010171002), the Ningbo Science and Technology Innovation Program 2025 (Grant No. 2019B10123), and the National Natural Science Foundation of China (Grant No. 62074122).

The threshold voltage (V th) of the p-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) is investigated via Silvaco-Atlas simulations. The main factors which influence the threshold voltage of p-channel GaN MOSFETs are barrier height Φ 1,p, polarization charge density σ b, and equivalent unite capacitance C oc. It is found that the thinner thickness of p-GaN layer and oxide layer will acquire the more negative threshold voltage V th, and threshold voltage |V th| increases with the reduction in p-GaN doping concentration and the work-function of gate metal. Meanwhile, the increase in gate dielectric relative permittivity may cause the increase in threshold voltage |V th|. Additionally, the parameter influencing output current most is the p-GaN doping concentration, and the maximum current density is 9.5 mA/mm with p-type doping concentration of 9.5 × 1016 cm−3 at V GS = –12 V and V DS = –10 V.

Mobility Fluctuations in a Normally-Off GaN MOSFET Using Tetramethylammonium Hydroxide Wet Etching

Low-frequency noise (LFN) performances are investigated in a normally-off GaN metal-oxide-semiconductor field-effect transistor (MOSFET) fabricated by utilizing the tetramethylammonium hydroxide (TMAH) wet etching. The normalized power spectral densities (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Id</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) are measured and perfectly matched with both the correlated mobility fluctuations (CMF) and Hooge mobility fluctuations (HMF) noise models. From the curves of (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Id</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) dependent on the gate overdrive voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> - V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> , it is also confirmed that the mobility fluctuations prevail in the fabricated GaN device. The calculated Hooge constants (α <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</sub> ) according to the (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> - V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) are obtained to be 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> ~ 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> . The reason for the dominance of the mobility fluctuations and the relatively low α <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</sub> is attributed that the TMAH wet etching effectively removes the plasma etching damage and fully recovers the crystal quality of GaN channel.

Suppression of short-channel effects in normally-off GaN MOSFETs with deep recessed-gate structures

We have demonstrated the suppression of short-channel effects (SCEs) in normally-off GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) with deep recessed-gate structures. TCAD simulation results show that the electric field concentration is effectively reduced at the recessed edge of MOSFETs with deeper recessed-gate structures. To demonstrate suppression of SCEs, MOSFET gate structures with recess depths ranging from 45 to 165 nm were fabricated and evaluated. Experimental results show that deeper recessed-gate structures are highly effective for suppressing drain-induced barrier lowering and improving subthreshold swing and threshold voltage roll-off.

Extraction of the active acceptor concentration in (pseudo-) vertical GaN MOSFETs using the body-bias effect

We report and discuss the performance of an enhancement mode n-channel pseudo-vertical GaN metal oxide semiconductor field effect transistor (MOSFET). The trench gate structure of the MOSFET is uniformly covered with an Al2O3 dielectric and TiN electrode material, both deposited by atomic layer deposition (ALD). Normally-off device operation is demonstrated in the transfer characteristics. Special attention is given to the estimation of the active acceptor concentration in the Mg doped body layer of the device, which is crucial for the prediction of the threshold voltage in terms of device design. A method to estimate the electrically active dopant concentration by applying a body bias is presented. The method can be used for both pseudo-vertical and truly vertical devices.Since it does not depend on fixed charges near the channel region, this method is advantageous compared to the estimation of the active doping concentration from the absolute value of the threshold voltage.

Impacts of Al2O3/GaN interface properties on the screening effect and carrier mobility in an inversion layer

The impact of Al2O3/GaN interface properties with a large surface potential fluctuation (σs) and acceptor nature of interface traps on the screening effect of interface charges due to inversion carriers in a metal-oxide-semiconductor field-effect transistor (MOSFET) were systematically investigated. Also, the impact of the large σs on the inversion layer mobility (μeff) in the MOSFET was investigated using a model with one-dimensional surface potential fluctuation. It was found that charges of the interface traps at the Al2O3/GaN interfaces are not screened enough by the inversion carriers due to the acceptor nature of the traps, and that μeff strongly depends on the σs values. Consequently, we found that a large σs of around 8 for the Al2O3/GaN interface significantly degrades the GaN MOSFET performance.

High-blocking-voltage UMOSFETs with reformed electric field distribution

A high-performance vertical GaN metal–oxide–semiconductor field-effect transistor (MOSFET) with a U-shaped gate (UMOSFET) and high blocking voltage is proposed. The main concept behind this work is to reform the electric field distribution to achieve high blocking voltage. The proposed structure includes p-regions in the drift region, which we call reformed electric field (REF) regions. Simulations using the two-dimensional SILVACO simulator reveal the optimum doping concentration, and width and height of the REF regions to achieve the maximum depletion region at the breakdown voltage in the drift region. Also, the electric field distribution in the REF-UMOSFET is reformed by producing additional peaks, which decreases the common peaks under the gate trench. We discuss herein the impact of the height, width, and doping concentration of the REF regions on the ON-resistance (RON) and blocking voltage. The blocking voltage, specific ON-resistance, and figure of merit $$ \left( {{\text{FOM}} = \frac{{V_{{{\text{BR}}}}^{2} }}{{R_{{{\text{ON}}}} }}} \right) $$ are 1140 V, 0.587 mΩ cm2 (VGS = 15 V, VDS = 1 V), and 2.214 GW/cm2, respectively. The blocking voltage and FOM are increased by about 72 % and 171 % in comparison with a conventional UMOSFET (C-UMOSFET).

(Invited) Achieving Vertical Trench-Gate GaN MOSFETs via Process Optimization

Gallium nitride is a strong candidate material for advanced power electronics that exceed the capabilities of current Si and SiC technologies. The ideal device structure for GaN power switches is the vertical metal-oxide-semiconductor field effect transistor (MOSFET). Current vertical GaN MOSFETs have not reached theoretical performance limits. Optimization of these devices is required to improve their performance, particularly with respect to the dielectric/semiconductor interface along the device active regions, and processing used to fabricate the vertical channel regions. We have studied two atomic layer deposition precursor systems for ZrO2 dielectrics on both as-grown and plasma-etched c-plane GaN. Piranha etching of GaN surfaces before ALD improved the capacitance-voltage response of the deposited ZrO2. 5-10 µm deep trenches in GaN substrates have also been fabricated, to allow more detailed study of the trench sidewalls and dielectric interfaces on the etched surfaces before and after hydroxide-based wet etching.

(Invited) Threshold Voltage Modulation By Interface Charge Engineering for High Performance Enhancement-Mode Al2O3/GaN Power Mosfets

III-Nitride metal-oxide-semiconductor field effect transistors (MOSFETs) have great potential for next generation energy-efficient power switching. Due to the fail-safe consideration, the enhancement-mode (E-mode) operation is highly desirable for GaN MOSFETs in power electronics. Furthermore, in high frequency switching applications, devices with high V TH (e.g. V TH>6 V) and large gate swing (e.g. >10 V) are required to prevent them from faulty turn-on due to the gate driver failure or electromagnetic interference. Many approaches have been demonstrated in pushing the V TH more positive [1], [2]. However, achieving high V TH and good performance simultaneously remains a major challenge due to positive interface fixed charges [3], [4]. In this paper, the presence of positive interface fixed charges (Q it~1.44×1013 cm-2) at the ALD-Al2O3/GaN interface was found in the fully recessed Al2O3/GaN MOSFETs. The origin of the interface charges is proposed to be the Ga-O bond and metal Ga dangling bond (DB) at the Al2O3/GaN interface generated in the gate recessing process and Al2O3 deposition, respectively. An efficient approach to engineer the interface positive fixed charges was demonstrated by post-dielectric annealing (PDA) in N2, resulting in a reduction of Q it from 1.44×1013 to 3×1012 cm-2. The reduction of Q it leads to a significant positive shift in V TH and an increase of electron mobility that enabling the E-mode operation of Al2O3/GaN MOSFETs with a uniquely high V TH of +7.6 V and drive current as high as 355 mA/mm. The interface charge engineering method demonstrated in this work is promising to fabricate E-mode GaN devices with uniquely higher V TH and low on-resistance.

New Material Transistor with Record-High Field-Effect Mobility among Wide-Band-Gap Semiconductors.

At an ultrathin 5 nm, we report a new high-mobility tin oxide (SnO2) metal-oxide-semiconductor field-effect transistor (MOSFET) exhibiting extremely high field-effect mobility values of 279 and 255 cm(2)/V-s at 145 and 205 °C, respectively. These values are the highest reported mobility values among all wide-band-gap semiconductors of GaN, SiC, and metal-oxide MOSFETs, and they also exceed those of silicon devices at the aforementioned elevated temperatures. For the first time among existing semiconductor transistors, a new device physical phenomenon of a higher mobility value was measured at 45-205 °C than at 25 °C, which is due to the lower optical phonon scattering by the large SnO2 phonon energy. Moreover, the high on-current/off-current of 4 × 10(6) and the positive threshold voltage of 0.14 V at 25 °C are significantly better than those of a graphene transistor. This wide-band-gap SnO2 MOSFET exhibits high mobility in a 25-205 °C temperature range, a wide operating voltage of 1.5-20 V, and the ability to form on an amorphous substrate, rendering it an ideal candidate for multifunctional low-power integrated circuit (IC), display, and brain-mimicking three-dimensional IC applications.

Normally‐off vertical‐type mesa‐gate GaN MOSFET

A vertical-type mesa-gate GaN metal–oxide semiconductor field-effect transistor (MOSFET) has been fabricated. The mesa-gate structure can be easily achieved by a single deep etch to the n+-GaN which is the drain of the device, whereas the trench-gate structure, the commonly used structure for the vertical-type MOSFETs, requires an additional etching process to define the gate region. The mesa-gate GaN MOSFET exhibited a normally-off operation with the threshold voltage of 3 V, a normalised drain current of ∼ 55 mA/mm and a high on/off current ratio of 108.

Process dependency on threshold voltage of GaN MOSFET on AlGaN/GaN heterostructure

GaN metal–oxide–semiconductor field-effect transistors (MOSFETs) with recessed gate on AlGaN/GaN heterostructure are reported in which the drain and source ohmic contacts were fabricated on the AlGaN/GaN heterostructure and the electron channel was formed on the GaN buffer layer by removing the AlGaN barrier layer. Negative threshold voltages were commonly observed in all devices. To investigate the reasons of the negative threshold voltages, different oxide thickness, etching gas and bias power of inductively-coupled plasma (ICP) system were utilized in the fabrication process of the GaN MOSFETs. It is found that positive charges of around 1×1012q/cm2 exist near the interface at the just threshold condition in both silane- and tetraethylorthosilicate (TEOS)-based devices. It is also found that the threshold voltages do not obviously change with the different etching gas (SiCl4, BCl3 and two-step etching of SiCl4/Cl2) at the same ICP bias power level (20–25W) and will become deeper when higher bias power is used in the dry recess process which may be related to the much serious ion bombardment damage. Furthermore, X-ray photoelectron spectroscopy (XPS) experiments were done to investigate the surface conditions. It is found that N 1s peaks become lower with higher bias power of the dry etching process. Also, silicon contamination was found and could be removed by HNO3/HF solution. It indicates that the nitrogen vacancies are mainly responsible for the negative threshold voltages rather than the silicon contamination. It demonstrates that optimization of the ICP recess conditions and improvement of the surface condition are still necessary to realize enhancement-mode GaN MOSFETs on AlGaN/GaN heterostructure.

Field isolation for GaN MOSFETs on AlGaN/GaN heterostructure with boron ion implantation

We report the investigation of boron ion implantation as a device field isolation process for GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) on AlGaN/GaN heterostructure. In the mesa isolation region of a bar-type MOSFET, a parasitic MOS-channel existed and widened the designed channel width, which would result in an overestimated mobility compared with a ring-type MOSFET. After boron ions implantation in the isolation region, the overestimation of field-effect mobility of bar-type MOSFETs was eliminated. The sub-threshold characteristics and on-state drain current of the bar-type MOSFETs coincide with the ring-type devices. Long-channel ring-type MOSFETs, with and without ion implantation, were fabricated on the recess region to evaluate the sub-threshold characteristics. The MOSFETs with boron ions implanted into the recess region showed a low drain current up to the gate bias of 10V. The result indicated that boron ion implantation prevented the formation of parasitic MOS-channel in the isolation region and achieved field isolation. The current–voltage characteristics of MOSFETs with the normal recess condition demonstrated no degradation of device performance after boron ions implanted into the isolation region. Boron ion implantation by further optimization can be a field isolation method for GaN MOSFETs.

GaN MOSFET with Boron Trichloride-Based Dry Recess Process

The dry recessed-gate GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) on AlGaN/GaN heterostructure using boron trichloride (BCl3) as etching gas were fabricated and characterized. Etching with different etching power was conducted. Devices with silicon tetrachloride (SiCl4) etching gas were also prepared for comparison. Field-effect mobility and interface state density were extracted from current-voltage (I-V) characteristics. GaN MOSFETs on AlGaN/GaN heterostructure with BCl3 based dry recess achieved a high maximum electron mobility of 141.5 cm2V−1s−1 and a low interface state density.

Performance of GaN Metal–Oxide–Semiconductor Field-Effect Transistor with Regrown n+-Source/Drain on a Selectively Etched GaN

We proposed and fabricated normally off GaN MOSFETs with an epitaxially regrown n+ GaN source/drain after a short period of dry etching on a sapphire substrate. The regrown S/D MOSFET after dry etching (MOSFET A) exhibited enhanced performance in terms of current drivability and access resistance compared with the same MOSFET without the surface etching before the regrowth (MOSFET B). While MOSFET A has a saturation drain current of 10 mA/mm at VG = 8 V, a field-effect mobility of 22 cm2 V-1 s-1, and a series resistance RSD of 0.57 kΩ, MOSFET B has 3 mA/mm, 12 cm2 V-1 s-1, and 0.93 kΩ, respectively. The electrical characteristic of MOSFET A was also much more improved than that of MOSFET B at low temperatures. Mobility degradation at low temperatures was related to the effect of impurity scattering caused by crystal defects generated during the metal organic chemical vapor deposition (MOCVD) growth.

High Quality SiO2/Al2O3 Gate Stack for GaN Metal–Oxide–Semiconductor Field-Effect Transistor

High quality SiO2/Al2O3 gate stack has been demonstrated for GaN metal–oxide–semiconductor (MOS) transistor. We confirmed that Al2O3 could realize a low interface-state density between Al2O3 and GaN, however, the breakdown field was low. By incorporating the merits of both Al2O3 and SiO2, which has a high breakdown field and a large charge-to-breakdown, SiO2/Al2O3 gate stack structure has been employed in GaN MOS devices. The structure shows a low interface state density between gate insulator and GaN, a high breakdown field, and a large charge-to-breakdown. The SiO2/Al2O3 gate stack has also been applied to AlGaN/GaN hybrid MOS heterojunction field-effect transistor (HFET). The MOS-HFET shows excellent properties with the threshold voltage of 4.2 V and the maximum field-effect mobility of 192 cm2 V-1 s-1.