GaN High Electron Mobility Transistors Research Articles

Reduction of interface defects in gate-recessed GaN HEMTs by neutral beam etching

This study investigates and compares the impact of different etching techniques on the fabrication of GaN high electron mobility transistors (HEMTs) between the inductively coupled plasma reactive ion etching (ICP-RIE) and the neutral beam etching (NBE) for the gate recess. By conducting direct current analysis, it was found that devices manufactured using the NBE exhibited superior electrical performance as compared with those produced using the ICP-RIE. These enhanced electrical characteristics include a transconductance of up to 100.4 mS/mm, a threshold voltage (Vth) of −2.3 V, an on/off current ratio of 1.1 × 109, a subthreshold swing (S.S.) of 99.63 mV/dec, and a remarkably low gate leakage current. Additionally, we noted varying degrees of hysteresis in the I–V characteristics were related to process disparities possibly leading to interface defects. Multi-frequency capacitance-voltage (C–V) measurements were used to identify the interface defects at the oxide/AlGaN interface of the gate. The results revealed that devices fabricated using the NBE exhibited a lower interface defect density as compared with those fabricated using the ICP-RIE, thereby elucidating the reduced hysteresis observed in the I–V characteristics. These findings indicated the significant advantages of the NBE process in the fabrication of GaN HEMTs.

Correlation of heat transport mechanism and structural properties of GaN high electron mobility transistors

Grain sizes, impurities, and layer thicknesses in the nm-range affect the heat transport and, hence, hinder proper heat dissipation of GaN-based devices. To obtain a clear picture of heat dissipation, the mechanisms of heat transport must be linked to the structural properties of the nitride-based materials in the device. In this paper, a systematic investigation of the typical layers of GaN high-electron mobility transistor stacks was conducted by time-domain thermoreflectance analysis and Raman measurements. The analyzed layers are the AlN nucleation layer, the Al0.3Ga0.7N transition layer, the AlGaN/AlN superlattice, the C-doped GaN back-barrier, and the uid GaN layer. The results were interpreted using the Born–van Karman model, including the suppression function approach to describe the governing heat transport mechanisms. Investigation of this AlN nucleation layer showed that its phonon scattering is dominated by impurity and grain boundary scattering. The Al0.3Ga0.7N transition layer was shown to have a reduced thermal conductivity not only due to alloy scattering but also because of grain boundary scattering. The AlGaN/AlN superlattice showed a thermal conductivity lower than the Al0.3Ga0.7N transition layer, especially at higher temperatures (7.2 ± 0.2 W/mK vs 14.1 ± 0.4 W/mK at 300 °C). Caused by the enhanced AlGaN/AlN interface density, the thermal conductance was found to be 2 GW/m2 K. The AlGaN/AlN superlattice indicated an anisotropic thermal transport with a factor of ∼1.5. The C-doped GaN layers were analyzed in terms of their size-dictated thermal conductivity, resulting in a reduction of ∼66% from 1 μm to 250 nm at 30 °C. Raman spectroscopy revealed that the thicker the GaN layer, the higher the compressive stress in GaN, which additionally results in a higher thermal transport. The investigations of the heat transport depending on the structural properties enabled an accurate determination of the thermal conductivity of the layer stack. These thermal conductivities served as input parameters for 3D simulation to extract the temperature, in terms of the thermal resistance, of such high-electron mobility transistor stacks. This simulation shows the importance of the GaN layer in terms of thermal management. This work uncovers the thermal transport in GaN-based transistor stacks with the aim to improving the thermal design.

Breakdown voltage enhancement and specific on-resistance reduction in depletion-mode GaN HEMTs by co-modulating electric field

In this letter, a depletion-mode GaN high electron mobility transistors (GaN HEMTs) with high breakdown voltage and low on-resistance are designed and experimentally demonstrated. It combines the gate field plate and partial unintentionally doped GaN (u-GaN) cap layer (gate field plate and partial u-GaN cap HEMTs: GPU-HEMTs) to co-modulate the surface electric field distribution, which results in the electric field peak being far away from the gate edge, thus improving the breakdown voltage and decreasing the on-resistance. The optimized GPU-HEMTs exhibit a larger output current (I DS) of 495 mA mm−1 and a correspondingly smaller specific on-resistance of 4.26 mΩ·cm2. Meanwhile, a high breakdown voltage of 1044 V at I DS = 1 mA mm−1 compared to the conventional GaN HEMTs of 633 V was obtained. This approach is highly effective in simultaneously optimizing the breakdown voltage and the specific on-resistance of GaN HEMTs, while maintaining a large output current.

Solid-mechanics analysis and modeling of the alloyed ohmic contact proximity in GaN HEMTs using µRaman spectroscopy

This study explores the impact of alloyed ohmic contact separation on ungated GaN high electron mobility transistors (HEMTs) lattice stress by employing Raman spectroscopy and solid mechanics simulations for comprehensive analysis. Focusing on the substantial stresses exerted by ohmic contacts, our research introduces a novel mechanical calibration procedure. The proposed procedure demonstrates that the stress in the GaN buffer can be precisely modelled using Raman measurements taken from patterns of varying length, which in return reveals the impact of ohmic contacts on stress. We show that this technique shows a good alignment to the Raman measurement results. Moreover, we identify ohmic contact edges as potential sites for defect generation due to the accumulation of substantial elastic energy, a finding supported by experimental observations of crack formations in related studies. Our calibrated mechanical model not only enhances the understanding of stress distributions within GaN HEMTs but also lays the groundwork for future improvements in electro-thermo-mechanical simulations.

Degradation analysis of GaN-based high–electron-mobility transistors under different stresses in semi-on state conditions

The large numbers of high-energy carriers that occur in semiconductor devices under semi-on state conditions can cause significant device degradation. The effects of different stresses on the electrical and trapping characteristics of GaN-based high-electron-mobility transistors (HEMTs) are investigated. Test results for GaN HEMTs under semi-on state conditions show that the electrical characteristics of these devices degrade to a certain extent after they are subjected to electrical pulse stress cycles with different drain voltage, frequencies, and duty cycles; a degree of degradation also occurs in the electrical characteristics of the devices when they are subjected to direct current electrical stresses. After electrical stress is applied, the absolute amplitude of the traps in the device increases, thus indicating an increase in the trap density. The results show that voltage is the main driver for device damage, with the current playing an accelerating role through its effects on device temperature or by supplying hot electrons; therefore, the drain voltage has the most significant effect on device degradation, which is mainly due to channel high-energy hot electron injection.

Millimeter-Wave GaN High-Power Amplifier MMIC Design Guideline Considering a Source via Effect

A millimeter-wave (mmWave) gallium nitride (GaN) high-power amplifier (HPA) monolithic microwave-integrated circuit (MMIC) was implemented, considering a source via effect. In this paper, we introduce guidelines for designing GaN HPA MMICs, from device sizing to meeting high-power specifications, power matching considering source via effects, schematic design of three-stage amplifier structures, and electromagnetic (EM) simulation. Based on the results of load pull simulation and small-signal maximum stable gain (MSG) simulation, the GaN high-electron-mobility transistor (HEMT) size was selected to be 8 × 70 μm. However, since the source via model provided by the foundry was significantly different from the EM results, it was necessary to readjust the power matching considering this. Additionally, when selecting the source via size, the larger the size, the easier the matching, but since the layout of the peripheral bias circuit is not possible, a compromise was required considering the actual layout. To prevent in-band oscillation, an RC parallel circuit was added to the input matching circuit, and low-frequency oscillation was solved by adding a gate resistor on the PCB module. The proposed PA was fabricated with a commercial 0.1 μm GaN HEMT MMIC process. It exhibited 38.56 to 39.71 dBm output power (Pout), 14.2 to 16.7 dB linear gain, and 14.1% to 18.2% power-added efficiency (PAE) in the upper Ka band. The fabricated GaN power amplifier MMIC shows competitive Pout in the upper Ka band above 33 GHz.

Effect of Acceptor Traps in GaN Buffer Layer on Source/Drain Contact Resistance in AlGaN/GaN High Electron Mobility Transistors

As‐grown GaN buffer layers have a significant electron concentration, which causes an increase in leakage current and a decrease in the breakdown voltage, VBR, of GaN High Electron Mobility Transistors (HEMTs). To prevent this, deep acceptor traps of density, NAT, are added to the GaN layer during growth. While a study on the effect of NAT on VBR is available in the literature, that on the effect of NAT on contact resistance, Rc, of source/drain contacts is lacking. Herein, the following is established using technology computer‐aided design simulations calibrated with measured current–voltage characteristics of ungated AlGaN/GaN structures: 1) Rc increases significantly with NAT and with the depth of the trap level from the conduction band. For trap level 2.5 eV below the conduction band, Rc doubles for an increase in NAT from 1 × 1016 to 5 × 1017 cm−3. 2) The variation of Rc with temperature is non‐monotonic. Over a temperature range of 300–450 K, Rc is nearly constant with temperature for NAT = 1 × 1016 cm−3 and decreases by 20% for NAT = 5 × 1017 cm−3, when traps are 2.5 eV below the conduction band. Also, the degradation of the transfer and output characteristics of GaN HEMTs due to a notable increase in Rc due to NAT is investigated.

Comprehensive empirical modeling of ScAlN/AlGaN/GaN ferroelectric HEMT

This correspondence introduces a concise depiction of a high electron mobility transistor (HEMT) utilizing a model that incorporates the effect of ferroelectric (FE) polarization on the empirical expression for drain current. This is accomplished by modifying the basic Shockley equation (S.E) for MESFET. The model employed in this investigation is particularly geared towards investigating the impact of the counterclockwise hysteresis effect due to the use of dielectric ScAlN on the transfer characteristics ( Id−Vgs ), which is mainly attributed to trapping and de-trapping of charge carriers at the dielectric/semiconductor interface. Modifying the S.E. made it possible to replicate the behavior observed in experimental HEMT accurately. We reported the modified drain current empirical expressions for the ScAlN/AlGaN/GaN HEMT that considers the FE polarization. The results of this study showed good agreement between the Id−Vgs characteristics obtained from the analytical and experimental data, with a root mean square deviation (RMSD) error of 0.97% and a mean squared error error of 0.94%. This analytical drain current model, presented herein for the first time, incorporates a limited number of fitting parameters. Therefore, enhancing the computational efficiency to assess the performance of FE GaN HEMTs for usage in wide-area electronics.

Multiphysics simulation study of thermal stress effects in nanoscale FinFETs heterogeneously integrated with GaN high-power device on silicon substrate

Heterogeneous integration enables high-density integration to improve system functionality, but meanwhile brings reliability concerns due to the intensification of temperature and thermal stress. However, research on thermal stress effects in nanoscale transistors within heterogeneous integrated circuit is still very limited up to now. Multiphysics computation for the heterogeneous integration of nanoscale p-FinFET with GaN high electron mobility transistor (HEMT) on silicon substrate is performed. Firstly, self-heating of GaN HEMT induced thermal stress is simulated. Then, thermal stress effects induced by the GaN HEMT on quantum transport in the FinFET at different locations are compared and analyzed, including the hole effective mass, hole average velocity, on/off-state current, and on-off ratio. Moreover, the impacts of crystal orientation configurations are further discussed. Simulation results show that the impact of thermal stress on FinFET is highly dependent on the Si crystal orientation and its location relative to GaN HEMT. Taking the FinFET with (001)/[110] confinement/transport orientation, which is at a distance of RFET and an angle of φ from the GaN HEMT as an example, thermal stress induces the significant reductions in Ion and Ioff of FinFET at φ = π/2 and φ = 3π/2, and the increases of Ion and Ioff in FinFET at φ = 0 and φ = π, but has small impact on FinFETs located diagonally to the GaN HEMT.

Dual-Module Ultrawide Dynamic-Range High-Power Rectifier for WPT Systems

Rectifier plays a pivotal role in wireless power transfer systems. While numerous studies have concentrated on enhancing efficiency and bandwidth at specific high-power levels, practical scenarios often involve unpredictable power inputs. Consequently, a distinct need arises for a rectifier that demonstrates superior efficiency across a broad range of input power levels. This paper introduces a high-power RF-to-DC rectifier designed for WPT applications, featuring an ultrawide dynamic range of input power. The rectification process leverages a GaN (gallium nitride) high electron mobility transistor (HEMT) to efficiently handle high power levels up to 12.6 W. The matching circuit was designed to ensure that the rectifier will operate in class-F mode. A Schottky diode is incorporated into the design for relatively lower-power rectification. Seamless switching between the rectification modes of the two circuits is accomplished through the integration of a circulator. The proposed rectifier exhibits a 27.5 dB dynamic range, achieving an efficiency exceeding 55% at 2.4 GHz. Substantial improvement in power handling and dynamic range over traditional rectifiers is demonstrated.

Study on irradiation effect and damage mechanism in cascode GaN HEMT irradiated by 10 MeV electron

This study investigated the irradiation effect of cascode-structure GaN HEMT (High Electron Mobility Transistor) devices, employing high-energy electrons with an energy of 10 MeV and irradiation doses ranging from 5 to 80 Mrad(Si). The variation of electrical properties of the device under annealing condition was analyzed. Geant4 and TCAD simulations were used to analyze the irradiation effect and damage mechanisms. The results show that the threshold voltage has obvious negative drift and the drain current increases after irradiation. The threshold voltage deviation amplitude of the device increases with the increase of irradiation dose, and the maximum deviation is 1.41V. Annealing at high temperatures (80 °C, 120 °C and 145 °C) partially restores the electrical properties, with a 0.49 V restoration in threshold voltage at 145 °C. Geant4 simulations reveal that enhanced Si MOSFET is more susceptible to total dose effects. TCAD simulations of enhanced Si MOSFET devices demonstrate an increase in electric field intensity, trapped electron concentration, and hole concentration in Si and SiO2 layers with the increase of irradiation dose. These findings can provide support for the space application and irradiation hardening of cascode GaN HEMT devices.

A novel field plate with arcuate end for improving GaN HEMTs

AbstractA new field plate (FP) is proposed for gallium nitride high‐electron‐mobility transistors (HEMTs). It features an innovative arcuate end (AE), which allows the induced charges that originally gathered at the FP end to diffuse over a wider area. Hence, not only is the electric field in the channel at the gate edge alleviated due to the induced charges, but also that concentrated at the FP end is reduced by means of AE. The simulation results indicate that by upgrading a source FP with AE, HEMT gains a 99% increase in breakdown voltage while remaining unaltered in specific on‐resistance. It also gets a 43.41% decrease in power loss during one cycle while maintaining the same breakdown voltage, which greatly contributes to enhance the efficiency of power electronic circuits.

GaN HEMT for High-performance Applications: A Revolutionary Technology

Background: The upsurge in the field of radio frequency power electronics has led to the involvement of wide bandgap semiconductor materials because of their potential characteristics in achieving high breakdown voltage, output power density, and frequency. III-V group materials of the periodic table have proven to be the best candidates for achieving this goal. Among all the available combinations of group III-V semiconductor materials, gallium nitride (GaN), having a band gap of 3.4eV, has gradually started gaining the confidence to become the next-generation material to fulfill these requirements. Objective: Considering the various advantages provided by GaN, it is widely used in AlGaN/GaN HEMTs (High Electron Mobility Transistors) as their fundamental materials. This work aimed to review the structure, operation, and polarization mechanisms influencing the HEMT device, different types of GaN HEMT, and the various process technologies for developing the device. Methods: Various available methods to obtain an enhancement type GaN HEMT are discussed in the study. It also covers the recent developments and various techniques to improve the performance and device linearity of GaN HEMT. Conclusion: Despite the advantages and continuous improvement exhibited by the GaN HEMT technology, it faces several reliability issues, leading to degradation of device performance. In this study, we review various reliability issues and ways to mitigate them. Moreover, several application domains are also discussed, where GaN HEMTs have proven their capability. It also focuses on reviewing and compiling the various aspects related to the GaN HEMT, thus providing all necessary information.

Enhanced Performance of GaN HEMTs in X‐band Applications Using SixN/Si3N4 Bilayer Passivation Technique

In order to achieve high‐performance gallium nitride (GaN) high‐electron‐mobility‐transistors (HEMTs) capable of operating in the X‐band, a bilayer passivation technique is employed. The technique involves creating a stacked passivation layer consisting of a 20‐nm Si‐rich silicon nitride (SixN) passivation layer and a 100‐nm N‐rich silicon nitride (Si3N4) passivation layer. This effectively reduces radio frequency scattering in GaN HEMTs without compromising the breakdown voltage (BV). On the one hand, the SixN passivation layer effectively suppresses the surface states of devices, resulting in low current collapse. On the other hand, the Si3N4 passivation layer can effectively reduce gate leakage caused by the SixN passivation layer, allowing the device to reliably operate at higher voltages. Consequently, a GaN HEMTs with SixN/Si3N4 bilayer passivation achieve a low current collapse of 5% and a high BV of 157 V. The device features a current gain cutoff frequency (fT) and maximum oscillation frequency (fmax) of 57.9 and 96.8 GHz, respectively. Additionally, it exhibits excellent radio frequency performance in the X‐band, with an output power density (Pout) of 13.7 W mm−1 and power added efficiency of 60.8% at a drain voltage (VD) bias of 50 V.

GaN HEMT and Air Core Magnetics based Power Converters Evaluations at Cryogenic Temperature

Cryogenic power electronics is both advantageous and indispensable in many applications, like deep space probe, military electric vehicle, magnetic resonance imaging etc. Among different semiconductors, the gallium nitride (GaN) high electron mobility transistor (HEMT) is the most promising candidate for cryogenic applications with significant conduction loss and switching loss reductions. Moreover, there is no carrier freeze out effect for the GaN HEMTs, which is applicable in extreme low temperature operating conditions. In this work, the efficiency of GaN HEMTs based power converters with different power levels (from several Watts to several kiloWatts) are evaluated at cryogenic temperature. Three different commercial GaN HEMTs are used in these power converters, including the Texas Instruments LMG5200 80 V GaN half-bridge power stage with integrated gate driver, the GaN Systems 650 V bottomcooled GaN HEMT GS66516B, and the 650 V top-cooled GaN HEMT GS66516T from GaN Systems. Moreover, two different cryogenic power converter evaluation methods (cryogenic chamber and liquid nitrogen channeled through cold plate) are investigated. Three of these power converters are evaluated by using a cryogenic chamber and such that the converter operating environment temperature can be regulated. One of the power converters is evaluated by using liquid nitrogen (LN2) channeled through a cold plate, where the gate driver can be designed to operate at non-cryogenic temperatures to ensure the safe operation of the system. Due to the degraded performance of conventional magnetic components, air core magnetics are used in these power converters to improve the converter efficiency. Efficiency improvements at cryogenic temperature are observed for all the GaN HEMTs and air core magnetics based power converters, which are promising for cryogenic power electronics applications.

Novel Temperature Calibration Method of E-Mode and D-Mode GaN Power Modules Considering Dynamic ON-Resistance

This paper presents a method for measuring temperature using the temperature sensitive parameter (TSP) of a GaN power module. Current collapse occurs in GaN high electron mobility transistors (HEMTs). This results in dynamic on-resistance because of trapped electrons. Thus, dynamic conditions should be considered to accurately measure thermal characteristics. GaN HEMTs are operated in the enhanced mode (E-mode) and depletion mode (D-mode). In this study, E-mode and D-mode GaN power modules are designed to compare their thermal characteristics. Among three common temperature-measurement methods, this work employs the TSP-based approach in consideration of the device operation, instead of those using thermo-sensitive optical or material properties. The calibration is conducted in steady-state and dynamic-state. The ambient temperature is estimated using steady-state calibration data. Power cycling is examined for considering dynamic conditions. It is confirmed that dynamic on-resistance changes according to the cycle period, on time, and number of cycles. Experiments are conducted using different values of these parameters. Finally, an equation for temperature is obtained from the experimental results. The equation precisely estimates temperature with an error of 0.7%.

Study of MoN gate impact on GaN high electron mobility transistor

AbstractIn this letter, molybdenum nitride (MoN) gate AlGaN/GaN HEMT has been investigated with MoN developed in various physical vapour deposition (PVD) conditions. The Schottky gate is studied through forward and reverse characteristics with different processed MoN, which is compared with the standard Ni gate. Similar DC and radio frequency (RF) performances are obtained with MoN and Ni gate, while MoN demonstrated higher reliability than Ni gate through RF aging test.

A novel small-signal equivalent circuit model for GaN HEMTs incorporating a dual-field-plate

An accurate and novel small-signal equivalent circuit model for GaN high-electron-mobility transistors (HEMTs) is proposed, which considers a dual-field-plate (FP) made up of a gate-FP and a source-FP. The equivalent circuit of the overall model is composed of parasitic elements, intrinsic transistors, gate-FP, and source-FP networks. The equivalent circuit of the gate-FP is identical to that of the intrinsic transistor. In order to simplify the complexity of the model, a series combination of a resistor and a capacitor is employed to represent the source-FP. The analytical extraction procedure of the model parameters is presented based on the proposed equivalent circuit. The verification is carried out on a 4 × 250 μm GaN HEMT device with a gate-FP and a source-FP in a 0.45 μm technology. Compared with the classic model, the proposed novel small-signal model shows closer agreement with measured S-parameters in the range of 1.0 to 18.0 GHz.

Current collapse suppression in AlGaInN/GaN HEMTs with thin unintentionally doped GaN channel and AlN back barrier grown on single-crystal AlN substrate

A high-electron-mobility transistor (HEMT) structure consisting of a 15-nm-thick quaternary AlGaInN top barrier layer, a thin 200-nm-thick unintentionally doped (UID) GaN channel layer, and an AlN back barrier was grown on a single-crystal AlN substrate by metal–organic chemical vapor deposition. The HEMTs fabricated on the grown heterostructure exhibited DC pinch-off characteristics with no large negative resistance owing to the high thermal conductivity of the AlN substrate. The 2-μm-gate-length devices showed the maximum current density of 500 mA/mm and the peak transconductance of 120 mS/mm with the threshold voltage of approximately −4 V. The off-state leakage was less than 30 μA/mm thanks to the thin UID-GaN channel with good crystal quality. The pulsed I–V characteristics for the fabricated HEMTs showed much smaller drain current decreasing compared to the same structured HEMTs with a C-doped GaN back barrier on a SiC substrate. This indicates that the UID-GaN channel grown on the AlN substrate had no harmful impurity levels that cause the current collapse phenomenon. The above-mentioned results demonstrate that the combination of the thin UID-GaN channel and the AlN back barrier works effectively in GaN HEMTs, and it will contribute to the device design and fabrication for future high-power/high-frequency applications.

Temperature-induced degradation of GaN HEMT: An in situ heating study

High-power electronics, such as GaN high electron mobility transistors (HEMTs), are expected to perform reliably in high-temperature conditions. This study aims to gain an understanding of the microscopic origin of both material and device vulnerabilities to high temperatures by real-time monitoring of the onset of structural degradation under varying temperature conditions. This is achieved by operating GaN HEMT devices in situ inside a transmission electron microscope (TEM). Electron-transparent specimens are prepared from a bulk device and heated up to 800 °C. High-resolution TEM (HRTEM), scanning TEM (STEM), energy-dispersive x-ray spectroscopy (EDS), and geometric phase analysis (GPA) are performed to evaluate crystal quality, material diffusion, and strain propagation in the sample before and after heating. Gate contact area reduction is visible from 470 °C accompanied by Ni/Au intermixing near the gate/AlGaN interface. Elevated temperatures induce significant out-of-plane lattice expansion at the SiNx/GaN/AlGaN interface, as revealed by geometry-phase GPA strain maps, while in-plane strains remain relatively consistent. Exposure to temperatures exceeding 500 °C leads to almost two orders of magnitude increase in leakage current in bulk devices in this study, which complements the results from our TEM experiment. The findings of this study offer real-time visual insights into identifying the initial location of degradation and highlight the impact of temperature on the bulk device’s structure, electrical properties, and material degradation.