GaN-based Heterojunction Field Effect Transistors Research Articles

Detection of lead ions with enhancement-mode GaN-based heterojunction field-effect transistors

Detection of lead ions with enhancement-mode GaN-based heterojunction field-effect transistors

Evaluation of Pulsed I–V Analysis as Validation Tool of Nonlinear RF Models of GaN-Based HFETs

This paper evaluates the applicability of pulsed I – V measurements as a tool for accurately extracting nonlinear gallium nitride (GaN)-based heterojunction field-effect transistor (HFET) models. Two wafers with the identical layer structure but different growth conditions have been investigated. A series of I – V measurements was performed under dc and pulsed conditions demonstrating a dramatic difference in the kink effect and current collapse (knee walkout) suggesting different trapping behaviors. However, when radio frequency (RF) I – V waveform measurements, utilizing active harmonic load–pull, were used to study the impact of these traps on the RF performance, both wafers gave good overall RF performance with no significant difference observed. This absence of correlation between pulsed I – V measurement results and RF performance raises a question about the applicability of pulsed I – V measurements alone as a tool for extracting nonlinear device models in the case of GaN HFETs.

NiO gate GaN-based enhancement-mode hetrojunction field-effect transistor with extremely low on-resistance using metal organic chemical vapor deposition regrown Ge-doped layer

In this paper, we present a normally-off GaN-based transistor with an extremely low on-resistance (Ron) fabricated by using a Ge-doped n++-GaN layer for ohmic contacts. We developed a novel GaN regrowth technique using Ge as a dopant, which achieved an extremely high doping concentration of 1 × 1020 cm−3, and thereby the lowest specific contact resistance of 1.5 × 10−6 Ω·cm2. The NiO gate fabricated using an atomic layer deposition technique reduced the spacing between the source and drain electrodes. The fabricated device showed the record-breaking Ron of 0.95 Ω·mm with the maximum drain current and transconductance of 1.1 A/mm and 490 mS/mm, respectively. Note that the obtained threshold voltage was 0.55 V. This extremely low Ron characteristic indicates the great potential of NiO-gate GaN-based heterojunction field-effect transistors.

GaN Power Transistor Modeling for High-Speed Converter Circuit Design

A circuit simulator has been developed to design power losses of high-frequency power converters using GaN-based heterojunction field-effect transistors (GaN-HFETs). The simulator is based on a high-accuracy equivalent model of GaN-HFETs with peculiar device physics and high-speed loss calculation methods. The simulated power losses were consistent with measured results in dc-dc converters constructed by a GaN-HFET and a SiC Schottky diode with more than 93% accuracy. By utilizing the developed simulator, key requirements in heat-dissipation technologies, circuit parasitic inductances, and gate-drive technologies for next-generation converters are discussed.

Status of Reliability of GaN-Based Heterojunction Field Effect Transistors

GaN-based heterojunction field effect transistors (HFETs) will play major roles in the high-power, high-frequency military and commercial arenas for microwave and millimeter wave transmitters and receivers used in communications and radar devices. In fact, devices operative in the X-band (7-12.5 GHz) and beyond are already at market and boast quite impressive performances. Having improved the crystal quality now to levels where the reliability [expressed as mean time to failure (MTTF)] is claimed to exceed ten million hours, the work now needs to focus on which of the physical mechanisms responsible for degradation are the most important, and how the existing degradation accelerates subsequent degradation, ultimately resulting in device failure. Available data show that not all devices from the same wafer show similar longevity and the wide spread of activation energies reported for three-temperature extrapolation-based predictions of the lifetime are troubling. If we hope to make consistent, reliable predictions of device lifetimes, particularly when the devices are being pushed in radio-frequency (RF) operation to near their limits, more work will need to be done in characterizing the long term stability of the devices, and new physical models for the failure mechanisms will have to be developed.

Insulating substrates for cubic GaN-based HFETs

The growth of cubic group III-nitrides is a direct way to eliminate polarization effects, which inherently limits the fabrication of normally off heterojunction field-effect transistors (HFETs) in the GaN technology. However, for the achievement of electronic devices with cubic nitrides an important precondition is the availability of a high-resistive substrate or GaN buffer layer with zinc-blende crystal structure. We investigated the applicability of carbonized high resistance Si (0 0 1)-substrates and thick conductive free-standing 3C-SiC (1 0 0) substrates with an Ar +-ion-damaged surface layer for this purpose and studied the use of carbon-doped GaN buffer layers for electrical insulation. We found that Ar-implantation of 3C-SiC is an appropriate alternative to fabricate insulation layer for cubic GaN (c-GaN) growth and that C-doped GaN buffers introduce non-linear I– V characteristics. The structural properties of c-GaN on Ar-implanted 3C-SiC are comparable to GaN on untreated 3C-SiC whereas on carbonized Si substrates an increase of dislocation density and surface roughness is observed.

C-doped semi-insulating GaN HFETs on sapphire substrates with a high breakdown voltage and low specific on-resistance

High breakdown voltage (BV) AlGaN∕GaN heterojunction field effect transistors (HFETs) with a low specific on-resistance (ARDS(on)) were successfully fabricated using intentionally C-doped semi-insulating GaN buffers with a high resistivity on sapphire substrates. With the improvement of not only the resistivity of a C-doped GaN buffer but also the layout design near the gate feeding region, the fabricated devices exhibited a high BV of ∼1600V and low ARDS(on) of 3.9mΩcm2. This result even reaches the 4H-SiC theoretical limit and the best ever reported for the high-power GaN-based HFETs realized on sapphire substrates to the best of our knowledge.

High breakdown voltage C-doped GaN-on-sapphire HFETs with a low specific on-resistance

High-quality C-doped GaN buffers grown on sapphire substrates were employed for the fabrication of high-power AlGaN/GaN heterojunction field effect transistors (HFETs). The fabricated device exhibited a very high breakdown voltage (BV) over 1350 V and low specific on-resistance (ARDS(ON)) of 3.4 mΩ cm2. This result is very close to the 4H-SiC limit and a record achievement for GaN-based HFETs realized on sapphire substrates, to the best of our knowledge.

Fabrication and characterization of high breakdown voltage AlGaN∕GaN heterojunction field effect transistors on sapphire substrates

High-quality C-doped GaN buffers with a very low doping concentration were grown on 2in. c-plane sapphire substrates, and high-power AlGaN∕GaN heterojunction field effect transistors (HFETs) on sapphire substrates for high-power switching applications were fabricated using a self-align process. The fabricated devices with gate-drain spacing (Lgd) of 16μm exhibited a high breakdown voltage (BV) over 1100V and low specific on resistance (ARDS(on)) of 4.2mΩcm2, with no additional photolithography process for a field plate design. This result approaches the SiC theoretical limit and is a record achievement for GaN-based HFETs on sapphire substrates, to the best of our knowledge. Based on the investigation of the influence of Lgd on device characteristics, it was shown that Lgd had a strong effect on ARDS(on) and BV while no noticeable change in maximum transconductance (gm,max) and maximum drain current (IDS,max) was observed when Lgd was varied. The ARDS(on) of a device [1.5μm gate length (Lg)] with Lgd>7μm was mainly determined by the gate-drain channel resistance. For a device (1.5μmLg)with Lgd<7μm, on the other hand, the ARDS(on) should be optimized by considering other important resistance components. The measured BVs increased with Lgd, suggesting that the actual device breakdown was determined by the gate-drain breakdown. The trend of the BV-ARDS(on) performance showed a clearly linear relation, suggesting that the device performance is very predictable with the variation of Lgd. As a result, with improvements in the material quality of a GaN buffer on sapphire substrate, the off-state BV and ARDS(on) were all enhanced to the point that high-power AlGaN∕GaN HFETs on sapphire substrates are now strong competitors for high-power switching applications.

At bias extraction of parasitic source and drain resistances in AlGaN/GaN HFETs: bias dependence and implications for device modelling and physics

The behaviour and performance of GaN-based heterojunction field-effect transistors (HFETs) strongly depends on the parasitic resistances. This is especially true for AlGaN/GaN -based HFETs which often suffer from a current collapse here shown to be characterized by bias-dependent parasitics. In this work, we extract the source and drain resistances from S-parameter measurements under active operating biases. The bias dependence of the drain resistance supports the virtual gate hypothesis which attributes current collapse to a decreased 2DEG concentration in the gate-drain access region. Additionally, the bias dependence of the source resistance indicates a source-side resistance modulation at high gate biases. Extraction of the equivalent circuit from hot S-parameters yields better matching to measured data compared to more conventional ColdFET extraction. Using the intrinsic circuit parameters for the hot extraction, the average electron velocity was determined to be 1.9 × 107 cm/s. (© 2006 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Analysis of active matrix GaN-based HFET switch circuits integrated with GaN LED micro-displays

We demonstrate a novel GaN-based heterojunction field effect transistor (HFET) active-matrix circuit for an light-emitting diode (LED) microdisplay. Simulation results are shown with basic and improved circuits. Variations of process and material growth conditions are discussed by correlating device parameters with LED flow currents in this circuit. It shows that the HFET-LED control circuit approach provides a stability path to mitigate variations of LED currents during operations.

High-resistivity GaN buffer templates and their optimization for GaN-based HFETs

High-resistance (HR) GaN templates for AlGaN/GaN heterojunction field effect transistor (HFET) applications were grown using organometallic vapor phase epitaxy. The GaN sheet resistance was tuned using final nucleation layer (NL) annealing temperature and NL thickness. Using an annealing temperature of 1033 °C and NL thickness of 26 nm, GaN with sheet resistance of 10 10 Ω/sq was achieved, comparable to that of Fe-doped GaN. Material characterization results show that the high-resistance GaN is achieved due to compensating acceptor levels that may be introduced through edge-type threading dislocations. Optimization of annealing temperature and NL thickness provided a means to maximize GaN sheet resistance without significantly degrading material quality. In situ laser reflectance was used to correlate the NL properties to sheet resistance and material quality, providing a figure of merit for expected sheet resistance. AlGaN/GaN HFET layers grown using HR GaN templates with R s of 10 10 Ω/sq gave surface and interface roughness of 14 and 7 Å, respectively. The 2DEG Hall mobility and sheet charge of HFETs grown using HR GaN templates was comparable to similar layers grown using unintentionally doped (UID) GaN templates.

573 K operation AlGaN/GaN HFET with enhancement operation on Si substrate

A normally-off FET is necessary for switching devices. We report on the enhancement operation GaN-based heterojunction field effect transistors (HFETs). The AlGaN/AlN/GaN heterostructure on a Si (111) substrate was grown using a metalorganic chemical vapor deposition (MOCVD). The HFET for a normally-off operation was fabricated using the AlGaN/C-GaN heterostructure. As a result, the HFET was operated at the condition of the positive gate bias. The breakdown voltage of FET was over 350 V. The on-state resistance (Ron) was about 10 mohmcm2. The maximum operation current of the FET was over 10 A. We also confirmed that the normally-off HFET was operated at 573 K. The normally-off operation of AlGaN/GaN HFETs on the Si substrate was thus confirmed for the first time. (© 2005 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

High-performance normally off FET using an AlGaN/GaN heterostructure on Si substrate

We report on novel normally off GaN-based heterojunction field effect transistors (HFETs). An AlGaN/AlN/GaN heterostructure on a Si (1 1 1) substrate was grown using metalorganic chemical vapor deposition (MOCVD). The optimum growth condition of an Al X Ga 1− X N buffer for the formation of a thin homogeneous GaN layer on a Si (1 1 1) substrate was confirmed, and a high-quality AlGaN/GaN heterostructure for fabricating the HFET could be grown. It was suggested that an AlGaN buffer of Al incorporation replaced by Ga has an important role for obtaining a smooth surface. An AlGaN/C-doped GaN heterostructure was applied for an HFET with normally off operation for the first time. As a result, the HFET was operated under the condition of a positive gate bias. The breakdown voltage of the FET was over 300 V. The normally off HFET operation at 573 K was also evaluated. The normally off operation of GaN-based HFETs on a Si substrate was thus successfully confirmed.

Normally-off operation GaN HFET using a thin AlGaN layer for low loss switching devices

ABSTRACTWe report on the novel normally-off GaN-based heterojunction field effect transistors (HFETs) on a Si substrate. The AlGaN/AlN/GaN heterostructure was grown using a metalorganic chemical vapor deposition (MOCVD). The HFET for a normally-off operation was fabricated using a precisely controlled thin-AlGaN layer as an electron supply layer. As a result, the HFET was operated at the condition of the positive gate bias. We also characterized the enlarged gate-width devices. The breakdown voltage of FET was over 300 V. A normally-off operation using GaN based HFETs with a thin-AlGaN/AlN/GaN heterostructure on the silicon substrate were thus confirmed for the first time.

Thermal modeling and measurement of GaN-based HFET devices

In this letter, we present our thermal study results of GaN-based heterojunction field effect transistors (HFETs). In thermal computation, PAMICE code was used to calculate temperatures in a three-dimension (3-D) model. In the thermal measurement, nematic liquid crystal thermography was employed to determine the peak temperature on the surface of the device chip. The calculated and directly measured temperatures agree well. These methods are valuable in predicting the thermal performance of GaN-based HFET devices, in particular the power devices.