GaN High Electron Mobility Transistors Research Articles

AI‐assisted Field Plate Design of GaN HEMT Device

AbstractGaN High Electron Mobility Transistors (HEMTs) plays a vital role in high‐power and high‐frequency electronics. Meeting the demanding performance requirements of these devices without compromising reliability is a challenging endeavor. Field Plates are employed to redistribute the electric field, minimizing the risk of device failure, especially in high‐voltage operations. While machine learning is applied to GaN device design, its application to field plate structures, known for their geometric complexity, is limited. This study introduces a novel approach to streamlining the field plate design process. It transforms complex 2D field plate structures into a concise feature space, reducing data requirements. A machine learning‐assisted design framework is proposed to optimize field plate structures and perform inverse design. This approach is not exclusive to the design of GaN HEMTs and can be extended to various semiconductor devices with field plate structures. The framework combines technology computer‐aided design (TCAD), machine learning, and optimization, streamlining the design process.

Nitride spacer aided 0.15 μm AlGaN/GaN HEMT fabrication with optimized gate patterning process

I-line stepper is widely used in large scale device manufacturing with limited achievable critical dimension by itself. With the aid of the spacer sidewall, the critical dimension can be further shrunk down. Spacer sidewall aided process necessitates an additional deposition-etching process, which inevitably results in process related damage under the gate. This paper proposes an optimized spacer sidewall aided gate patterning procedure for 0.15 μm GaN High Electron Mobility Transistors (HEMTs) fabrication. The process is proved to be effective in improving device performance compared to conventional sidewall process by keeping first Si-rich SiN passivation layer integrity at the gate edge. Interface trap density (Dit) and mobility were extracted for both conventional sidewall process and the optimized one with different passivation layers at the gate edge, demonstrating a lower Dit and higher mobility using the optimized process with enhanced device performances, such as higher current, breakdown voltage, and stress state characteristics, compared to the conventional process, which is promising for mass production of 0.15 μm GaN HEMTs.

ScAlInN/GaN heterostructures grown by molecular beam epitaxy

Rare-earth (RE) elements doped III-nitride semiconductors have garnered attention for their potential in advanced high-frequency and high-power electronic applications. We report on the molecular beam epitaxy of quaternary alloy ScAlInN, which is an encouraging strategy to improve the heterointerface quality when grown at relatively low temperatures. Monocrystalline wurtzite phase and uniform domain structures are achieved in ScAlInN/GaN heterostructures, featuring atomically sharp interface. ScAlInN (the Sc content in the ScAlN fraction is 14%) films with lower In contents (less than 6%) are nearly lattice matched to GaN, exhibiting negligible in-plane strain, which are excellent barrier layer candidates for GaN high electron mobility transistors (HEMTs). Using a 15-nm-thick Sc0.13Al0.83In0.04N as a barrier layer in GaN HEMT, a two-dimensional electron gas density of 4.00 × 1013 cm−2 and a Hall mobility of 928 cm2/V s, with a corresponding sheet resistance of 169 Ω/□, have been achieved. This work underscores the potential of alloy engineering to adjust lattice parameters, bandgap, polarization, interfaces, and strain in emerging RE-III-nitrides, paving the way for their use in next-generation optoelectronic, electronic, acoustic, and ferroelectric applications.

Enhanced device performance of GaN high electron mobility transistors with in situ crystalline SiN cap layer

In this paper, a ∼2 nm in situ SiN cap layer on AlGaN barrier layer is grown, which is revealed to be crystalline using high-resolution cross-sectional transmission electron microscopy. Benefitting from superior interface quality of epitaxial crystalline SiN/AlGaN interface, the gate diodes with in situ SiN cap layer feature lower interface trap state density than that with GaN cap layer. By comparing the GaN high electron mobility transistors (HEMTs) with the conventional GaN cap layer, the GaN HEMTs with in situ SiN cap layer exhibit improved device performance, showing higher electron mobility, higher drain current, larger on/off current ratio, and higher transconductance. For breakdown characteristics, the devices with in situ crystalline SiN cap layer show prominent advantages over the GaN cap layer with a 30% breakdown voltage increase to 810 V.

SPICE Simulation Assisted-Dynamic Rds(on) Characterization in 200V Commercial Schottky p-GaN HEMTs Under Unstable Phases

Abstract This paper presents a comprehensive analysis of dynamic and static RDS(ON) in Schottky p-GaN High Electron Mobility Transistors (HEMTs), highlighting the impact of off-state and hot electron trapping on device performance. The authors observed significant hysteresis in the transfer characteristics of a 200V commercial Schottky p-GaN, attributing this to charge trapping effects. A novel experimental setup, employing a multi-pulse test synchronous buck converter circuit with additional gate control and a clamping circuit, enabled precise characterization of dynamic RDS(ON) under varying conditions, including unstable phases with overcurrent. This method effectively mimics solar PV input scenarios, exposing the device to high dv/dt and di/dt stresses, which are critical for evaluating GaN device stability under transient conditions. This research also reveals that increased gate resistance reduces energy losses, challenging traditional expectations by demonstrating the nuanced gate charge dynamics of GaN HEMTs. This study overall contributes to the understanding of GaN device behavior, offering a novel approach for accurately characterizing dynamic RDS(ON) under unstable stages, furtherly advances the GaN device in complex renewable energy power converter applications.

A highly survivable X‐band low noise amplifier based on GaN HEMT technology and impact of pulse width on recovery time

AbstractGaN high electron mobility transistor (HEMT)‐based low noise amplifiers (LNAs) are an integral part of microwave receiver systems to enhance signal‐to‐noise ratio (SNR). The noise of LNA itself becomes critical for systems requiring high SNR, such as imaging and satellite communication systems. This paper discusses the design of a three‐stage LNA operating at the X‐band in the frequency range of 8.0–12.0 GHz. The amplifier's design and small signal, noise, and linearity characterizations are discussed. Stagewise analysis for gain, noise figure (NF), and matching network losses at the design stage results in achieving promising results. The proposed LNA provides a gain of 23.2 dB with dB gain ripple. Its NF is below 1.5 dB, output power at 1 dB gain compression is 16.4 dBm, and third‐order intercept point is 24.7 dBm at 10 GHz. LNA's survivability is validated to input stress as high as 42 dBm. This LNA is the best reported NF and survivability combination in the 8.0–12.0‐GHz frequency range. The reverse recovery time of LNA is measured under two different pulse conditions, and it has been shown that LNA has better recovery times for lower pulse width signals. This LNA finds its applications in radars and satellite communication systems.

Revisiting the effectiveness of diamond heat spreaders on multi-finger gate GaN HEMT using chip-to-package-level thermal simulation

The study of chip-level and package-level heat transfer in a GaN high electron mobility transistor (HEMT) is often disconnected due to limited resources and tools. In this work, device simulation from Silvaco Victory Device is carried forward to the chip-to-package-level simulation using Icepak to provide a complete picture of the proposed thermal management strategies using polycrystalline diamond (PCD) heat spreaders. The max junction temperature, Tj = 105.8 °C and the relative magnitude of max temperature on the GaN surface, ΔTj = 18 % are recorded for the original Si-GaN-Si3N4 chip inside TO-220 at 6.0 Wmm−1. Replacing the Si3N4 with PCD (thermal conductivity of 500 Wm−1 K−1) results in Tj = 98.2 °C and ΔTj = 8 %, while replacing the Si results in Tj = 97.0 °C and ΔTj = 11 %. The top layer PCD spreads the heat from hotspot regions to the surrounding epoxy, while the bottom layer PCD improves the heat path from the hotspots to the base plate. Therefore, the reduction in Tj by the bottom layer PCD is more important than the reduction in ΔTj by the top layer PCD. Implementing both the top and bottom layers of PCD results in the best offers of Tj = 92.9 °C and ΔTj = 6 %. The performance of PCD as heat spreaders in multi-finger gate GaN HEMT suggested by these chip-to-package-level simulations are more reliable than device simulation alone since they cover the complete heat path from generation, conduction within the package, and convection to the ambient air.

Temperature- and gate voltage-dependent I–V modeling of GaN HEMTs based on ASM-HEMT

Abstract In this paper, a temperature and gate voltage dependent current-voltage (I-V) model for Gallium nitride (GaN) high electron mobility transistors (HEMTs) devices is studied. In order to help researchers and designers simulate devices in the absence of experimental data and improve parameter extraction efficiency, the temperature and gate voltage dependence of mobility are discussed and incorporated into the proposed model which is revised from the standard advanced SPICE model (ASM) for GaN HEMTs. The mobility variations with gate voltage from -2 V to 6 V and temperature from 10 K to 1000 K are analyzed. The simulation results of our model are compared with the standard ASM-HEMT model, and the output and transfer characteristics of the device from 270 K to 420 K are simulated. Thereby, our model may simulate various applications of GaN HEMTs at different gate voltages and temperatures in the early stages of design and research.

Time-dependent conduction mechanisms in reversed stepped superlattice layers of GaN HEMTs on 200 mm engineered substrates

Time-dependent conduction in epitaxial superlattice (SL) strain relief layers of GaN high electron mobility transistors on 200 mm engineered substrates with a poly-AlN core was observed and analyzed. This phenomenon occurs when the devices were operated with substrate bias of ∼−300 V for 101–103 s. The formation of the conduction path is related to trap-assisted leakage through the SLs on the engineered substrates; de-trapped carriers spread out vertically and laterally within a portion of the SLs, leading to a higher electrical field across the rest of the layers. This conduction mechanism may be hidden during the devices' normal operation (target 650–1200 V). It could lead to undesired effects during the operation of the devices, such as a time-dependent dynamic Ron. More resistive SLs will potentially reduce the impact of this phenomenon.

Neuromorphic engineering in GaN HEMTs exploiting dendritic dislocations for neuromodulation behaviors and adaptive intelligent power forecasting systems

Gallium nitride (GaN), a prominent III-V semiconductor, plays a pivotal role in the advancement of sophisticated power systems. This study presents an innovative neuromorphic engineering approach utilizing the unique dendritic dislocations extending from bulk to channel within GaN High Electron Mobility Transistors (HEMTs) for three-dimensional charge modulation. This approach dynamically alters charge states and channel potentials in response to multiple parametric stimuli, effectively mimicking neural processing and transmission functions, as well as emulating direct and indirect neuromodulation behaviors observed in human nervous system. The advanced neuromodulation emulation enhances biomimetic diversity, laying a solid foundation for the design of intelligent systems. Comprehensive material and electrical analyses reveal the charging and discharging behaviors of the defect energy levels, underlying the neuromorphic working mechanisms. Additionally, by incorporating artificial neural network algorithms, an intelligent power forecasting system that leverages the device’s diverse neuromorphic traits is developed for real-time and adaptive power management, optimizing efficiency and accuracy in balancing supply and demand, thereby enhancing the cost-effectiveness and sustainability of power systems. The findings highlight the neuromorphic capabilities of GaN devices and open avenues for further exploration into the intelligent power management.

Thermal analysis of GaN HEMTs using nongray multi-speed phonon lattice Boltzmann method under Joule heating effect

Gallium Nitride (GaN) high electron mobility transistors (HEMTs) exhibit superior electrical properties for power and radio frequency applications, but performance is compromised by localized Joule heating, increasing channel temperatures. Precise thermal analysis during design is essential for optimizing device architecture and management strategies. Traditional methods like the Fourier heat diffusion equation (HDE) and the phonon lattice Boltzmann method (PLBM) with the D2Q8 scheme inadequately model phonon ballistic transport at high Knudsen numbers. This study introduces a nongray multi-speed PLBM integrated with the drift-diffusion model to analyze electro-thermal processes in GaN HEMTs. Validated through simulations of thermal conductivities in two-dimensional GaN thin films, the approach examines internal temperature rise in GaN HEMTs under different gate voltages, comparing results with HDE and gray BTE models, and emphasizing the need for non-Fourier effects in thermal analysis. It also evaluates the impact of GaN layer thickness on temperature distribution, providing a robust solution for thermal analysis in GaN HEMTs and other field-effect transistors.

Reduction of interface defects in gate-recessed GaN HEMTs by neutral beam etching

This study investigates and compares the impact of different etching techniques on the fabrication of GaN high electron mobility transistors (HEMTs) between the inductively coupled plasma reactive ion etching (ICP-RIE) and the neutral beam etching (NBE) for the gate recess. By conducting direct current analysis, it was found that devices manufactured using the NBE exhibited superior electrical performance as compared with those produced using the ICP-RIE. These enhanced electrical characteristics include a transconductance of up to 100.4 mS/mm, a threshold voltage (Vth) of −2.3 V, an on/off current ratio of 1.1 × 109, a subthreshold swing (S.S.) of 99.63 mV/dec, and a remarkably low gate leakage current. Additionally, we noted varying degrees of hysteresis in the I–V characteristics were related to process disparities possibly leading to interface defects. Multi-frequency capacitance-voltage (C–V) measurements were used to identify the interface defects at the oxide/AlGaN interface of the gate. The results revealed that devices fabricated using the NBE exhibited a lower interface defect density as compared with those fabricated using the ICP-RIE, thereby elucidating the reduced hysteresis observed in the I–V characteristics. These findings indicated the significant advantages of the NBE process in the fabrication of GaN HEMTs.

Correlation of heat transport mechanism and structural properties of GaN high electron mobility transistors

Grain sizes, impurities, and layer thicknesses in the nm-range affect the heat transport and, hence, hinder proper heat dissipation of GaN-based devices. To obtain a clear picture of heat dissipation, the mechanisms of heat transport must be linked to the structural properties of the nitride-based materials in the device. In this paper, a systematic investigation of the typical layers of GaN high-electron mobility transistor stacks was conducted by time-domain thermoreflectance analysis and Raman measurements. The analyzed layers are the AlN nucleation layer, the Al0.3Ga0.7N transition layer, the AlGaN/AlN superlattice, the C-doped GaN back-barrier, and the uid GaN layer. The results were interpreted using the Born–van Karman model, including the suppression function approach to describe the governing heat transport mechanisms. Investigation of this AlN nucleation layer showed that its phonon scattering is dominated by impurity and grain boundary scattering. The Al0.3Ga0.7N transition layer was shown to have a reduced thermal conductivity not only due to alloy scattering but also because of grain boundary scattering. The AlGaN/AlN superlattice showed a thermal conductivity lower than the Al0.3Ga0.7N transition layer, especially at higher temperatures (7.2 ± 0.2 W/mK vs 14.1 ± 0.4 W/mK at 300 °C). Caused by the enhanced AlGaN/AlN interface density, the thermal conductance was found to be 2 GW/m2 K. The AlGaN/AlN superlattice indicated an anisotropic thermal transport with a factor of ∼1.5. The C-doped GaN layers were analyzed in terms of their size-dictated thermal conductivity, resulting in a reduction of ∼66% from 1 μm to 250 nm at 30 °C. Raman spectroscopy revealed that the thicker the GaN layer, the higher the compressive stress in GaN, which additionally results in a higher thermal transport. The investigations of the heat transport depending on the structural properties enabled an accurate determination of the thermal conductivity of the layer stack. These thermal conductivities served as input parameters for 3D simulation to extract the temperature, in terms of the thermal resistance, of such high-electron mobility transistor stacks. This simulation shows the importance of the GaN layer in terms of thermal management. This work uncovers the thermal transport in GaN-based transistor stacks with the aim to improving the thermal design.

Breakdown voltage enhancement and specific on-resistance reduction in depletion-mode GaN HEMTs by co-modulating electric field

In this letter, a depletion-mode GaN high electron mobility transistors (GaN HEMTs) with high breakdown voltage and low on-resistance are designed and experimentally demonstrated. It combines the gate field plate and partial unintentionally doped GaN (u-GaN) cap layer (gate field plate and partial u-GaN cap HEMTs: GPU-HEMTs) to co-modulate the surface electric field distribution, which results in the electric field peak being far away from the gate edge, thus improving the breakdown voltage and decreasing the on-resistance. The optimized GPU-HEMTs exhibit a larger output current (I DS) of 495 mA mm−1 and a correspondingly smaller specific on-resistance of 4.26 mΩ·cm2. Meanwhile, a high breakdown voltage of 1044 V at I DS = 1 mA mm−1 compared to the conventional GaN HEMTs of 633 V was obtained. This approach is highly effective in simultaneously optimizing the breakdown voltage and the specific on-resistance of GaN HEMTs, while maintaining a large output current.

Solid-mechanics analysis and modeling of the alloyed ohmic contact proximity in GaN HEMTs using µRaman spectroscopy

This study explores the impact of alloyed ohmic contact separation on ungated GaN high electron mobility transistors (HEMTs) lattice stress by employing Raman spectroscopy and solid mechanics simulations for comprehensive analysis. Focusing on the substantial stresses exerted by ohmic contacts, our research introduces a novel mechanical calibration procedure. The proposed procedure demonstrates that the stress in the GaN buffer can be precisely modelled using Raman measurements taken from patterns of varying length, which in return reveals the impact of ohmic contacts on stress. We show that this technique shows a good alignment to the Raman measurement results. Moreover, we identify ohmic contact edges as potential sites for defect generation due to the accumulation of substantial elastic energy, a finding supported by experimental observations of crack formations in related studies. Our calibrated mechanical model not only enhances the understanding of stress distributions within GaN HEMTs but also lays the groundwork for future improvements in electro-thermo-mechanical simulations.

Degradation analysis of GaN-based high–electron-mobility transistors under different stresses in semi-on state conditions

The large numbers of high-energy carriers that occur in semiconductor devices under semi-on state conditions can cause significant device degradation. The effects of different stresses on the electrical and trapping characteristics of GaN-based high-electron-mobility transistors (HEMTs) are investigated. Test results for GaN HEMTs under semi-on state conditions show that the electrical characteristics of these devices degrade to a certain extent after they are subjected to electrical pulse stress cycles with different drain voltage, frequencies, and duty cycles; a degree of degradation also occurs in the electrical characteristics of the devices when they are subjected to direct current electrical stresses. After electrical stress is applied, the absolute amplitude of the traps in the device increases, thus indicating an increase in the trap density. The results show that voltage is the main driver for device damage, with the current playing an accelerating role through its effects on device temperature or by supplying hot electrons; therefore, the drain voltage has the most significant effect on device degradation, which is mainly due to channel high-energy hot electron injection.

Millimeter-Wave GaN High-Power Amplifier MMIC Design Guideline Considering a Source via Effect

A millimeter-wave (mmWave) gallium nitride (GaN) high-power amplifier (HPA) monolithic microwave-integrated circuit (MMIC) was implemented, considering a source via effect. In this paper, we introduce guidelines for designing GaN HPA MMICs, from device sizing to meeting high-power specifications, power matching considering source via effects, schematic design of three-stage amplifier structures, and electromagnetic (EM) simulation. Based on the results of load pull simulation and small-signal maximum stable gain (MSG) simulation, the GaN high-electron-mobility transistor (HEMT) size was selected to be 8 × 70 μm. However, since the source via model provided by the foundry was significantly different from the EM results, it was necessary to readjust the power matching considering this. Additionally, when selecting the source via size, the larger the size, the easier the matching, but since the layout of the peripheral bias circuit is not possible, a compromise was required considering the actual layout. To prevent in-band oscillation, an RC parallel circuit was added to the input matching circuit, and low-frequency oscillation was solved by adding a gate resistor on the PCB module. The proposed PA was fabricated with a commercial 0.1 μm GaN HEMT MMIC process. It exhibited 38.56 to 39.71 dBm output power (Pout), 14.2 to 16.7 dB linear gain, and 14.1% to 18.2% power-added efficiency (PAE) in the upper Ka band. The fabricated GaN power amplifier MMIC shows competitive Pout in the upper Ka band above 33 GHz.

Effect of Acceptor Traps in GaN Buffer Layer on Source/Drain Contact Resistance in AlGaN/GaN High Electron Mobility Transistors

As‐grown GaN buffer layers have a significant electron concentration, which causes an increase in leakage current and a decrease in the breakdown voltage, VBR, of GaN High Electron Mobility Transistors (HEMTs). To prevent this, deep acceptor traps of density, NAT, are added to the GaN layer during growth. While a study on the effect of NAT on VBR is available in the literature, that on the effect of NAT on contact resistance, Rc, of source/drain contacts is lacking. Herein, the following is established using technology computer‐aided design simulations calibrated with measured current–voltage characteristics of ungated AlGaN/GaN structures: 1) Rc increases significantly with NAT and with the depth of the trap level from the conduction band. For trap level 2.5 eV below the conduction band, Rc doubles for an increase in NAT from 1 × 1016 to 5 × 1017 cm−3. 2) The variation of Rc with temperature is non‐monotonic. Over a temperature range of 300–450 K, Rc is nearly constant with temperature for NAT = 1 × 1016 cm−3 and decreases by 20% for NAT = 5 × 1017 cm−3, when traps are 2.5 eV below the conduction band. Also, the degradation of the transfer and output characteristics of GaN HEMTs due to a notable increase in Rc due to NAT is investigated.

Comprehensive empirical modeling of ScAlN/AlGaN/GaN ferroelectric HEMT

This correspondence introduces a concise depiction of a high electron mobility transistor (HEMT) utilizing a model that incorporates the effect of ferroelectric (FE) polarization on the empirical expression for drain current. This is accomplished by modifying the basic Shockley equation (S.E) for MESFET. The model employed in this investigation is particularly geared towards investigating the impact of the counterclockwise hysteresis effect due to the use of dielectric ScAlN on the transfer characteristics ( Id−Vgs ), which is mainly attributed to trapping and de-trapping of charge carriers at the dielectric/semiconductor interface. Modifying the S.E. made it possible to replicate the behavior observed in experimental HEMT accurately. We reported the modified drain current empirical expressions for the ScAlN/AlGaN/GaN HEMT that considers the FE polarization. The results of this study showed good agreement between the Id−Vgs characteristics obtained from the analytical and experimental data, with a root mean square deviation (RMSD) error of 0.97% and a mean squared error error of 0.94%. This analytical drain current model, presented herein for the first time, incorporates a limited number of fitting parameters. Therefore, enhancing the computational efficiency to assess the performance of FE GaN HEMTs for usage in wide-area electronics.

Multiphysics simulation study of thermal stress effects in nanoscale FinFETs heterogeneously integrated with GaN high-power device on silicon substrate

Heterogeneous integration enables high-density integration to improve system functionality, but meanwhile brings reliability concerns due to the intensification of temperature and thermal stress. However, research on thermal stress effects in nanoscale transistors within heterogeneous integrated circuit is still very limited up to now. Multiphysics computation for the heterogeneous integration of nanoscale p-FinFET with GaN high electron mobility transistor (HEMT) on silicon substrate is performed. Firstly, self-heating of GaN HEMT induced thermal stress is simulated. Then, thermal stress effects induced by the GaN HEMT on quantum transport in the FinFET at different locations are compared and analyzed, including the hole effective mass, hole average velocity, on/off-state current, and on-off ratio. Moreover, the impacts of crystal orientation configurations are further discussed. Simulation results show that the impact of thermal stress on FinFET is highly dependent on the Si crystal orientation and its location relative to GaN HEMT. Taking the FinFET with (001)/[110] confinement/transport orientation, which is at a distance of RFET and an angle of φ from the GaN HEMT as an example, thermal stress induces the significant reductions in Ion and Ioff of FinFET at φ = π/2 and φ = 3π/2, and the increases of Ion and Ioff in FinFET at φ = 0 and φ = π, but has small impact on FinFETs located diagonally to the GaN HEMT.