Gallium Arsenide Field Effect Transistors Research Articles

BJT Based Translinear Implementation of an Evolutionary Optimised Non-Linear Function for Sensor Linearisation

The linear characteristics of temperature sensors are affected by material properties, aging, self-heating, lead resistance, and external interference. This study aims to improve sensor characteristics by overcoming power consumption and response time limitations. An evolutionary optimised log-ratiometric function is implemented for sensor linearisation using a translinear circuit. The differential evolution optimisation strategy is used to find the optimum values of the linearising parameters in the non-linear function. Further, these parameters are applied to the current mode circuit to linearise the selected sensors as an input current source. Due to higher fidelity, better comprehensive dynamic range, and improved linear areas, implementing the non-linear function using the BJT-based current mode circuit results in a better full-scale error reduction capability than MOSFET-based translinear implementation. Furthermore, the devices such as Gallium Arsenide Field-Effect Transistors (GaAsFET) and Modulation-Doped FET (MODFET) could be used in place of BJT in the future for additional error reduction due to rapid response speed, low power consumption, and reduced internal noise. Thus, the translinear implementation of the non-linear function can enhance the sensor characteristics in all aspects.

Design of 2.4 GHz LNA of 400 MHz Bandwidth

Low Noise Amplifier (LNA) is the most important front-end block of the receiver. LNA’s Noise figure (NF) and Scattering Parameters affect the overall performance of the whole receiver circuit. Nowadays in the era of 5G technology, The quality of data that is being transmitted is increased. So there is a need for higher bandwidth to transfer data with higher speed. In such a case, communication blocks need an update. The research is carried out for the advancement of the LNA. The primary goal of LNA design is to lower the Noise Figure and return losses. The paper aims to design a 2.4 GHz LNA having a bandwidth of 400 MHz. The circuit is designed with the help of single-stub microstrip lines. We tried to keep the length of microstrip lines as minimum as possible. The transistor ATF-21170 Gallium Arsenide Field Effect Transistor (GaAs FET) is used in this work. The circuit is simulated in the Keysight Advance Design System (ADS). The amplifier is manually designed using standard methods. LNA is unconditionally stable for the frequency range of 2.2 GHz to 2.6 GHz. To build impedance matching circuits of the amplifier smith chart is used. It is observed that the LNA gain (S21) is greater than 15.3 dB, NF less than 1.2 dB, Input return loss (S11) is less than -13.3 dB, Output return loss (S22) is less than -17.1 dB over the 400 MHz bandwidth ranging from 2.2 to 2.6 GHz. This has, to the best of the authors' knowledge, not been presented in literature before.

Stopping Power and Range of Cesium-137 Gamma Rays in Gallium Arsenide Field Effect Transistor (GaAsFET)

In this paper, the defect generated in the interaction of gamma ray resulting from cesium ion (Cs-137) and GaAs as a main portion of gallium arsenide field effect transistor (GaAsFET) is simulated using SRIM (Stopping and Range of Ions in Matter). The induced defects are in the form of vacancies, defect clusters and dislocations. Besides, the defect is found influencing the kinetic processes that occur both inside and outside the cascade volume. The radiation tolerance between the conventional scale and nanoscale thickness of GaAs layer is also being compared. From the findings, it is observed that when the thickness of GaAs layer is scaled down, defect that induced by the energy deposition of gamma radiation is significantly lesser. This means that nanoscale GaAs layer features improved radiation robustness towards the deposition of energetic ions.

A system for automated noise parameter measurements on MR preamplifiers and application to high B(0) fields.

A noise figure and noise parameter measurement system was developed that consists of a combination spectrum and network analyzer, preamplifier, programmable power supply, noise source, tuning board, and desktop computer. The system uses the Y-factor method for noise figure calculation and allows calibrations to correct for a decrease in excess noise ratio between the noise source and device under test, second stage (system) noise, ambient temperature variations, and available gain of the device under test. Noise parameters are extracted by performing noise figure measurements at several source impedance values obtained by adjusting an electronically controlled tuner. Results for several amplifiers at 128 MHz and 200 MHz agree with independent measurements and with the corresponding datasheets. With some modifications, the system was also used to characterize the noise figure of MRI preamplifiers in strong static magnetic fields up to 9.4 T. In most amplifiers tested the gain was found to be reduced by the magnetic field, while the noise figure increased. These changes are detrimental to signal quality (SNR) and are dependent on the electron mobility and design of the amplifier's semiconductor devices. Consequently, gallium arsenide (GaAs) field-effect transistors are most sensitive to magnetic fields due to their high electron mobility and long, narrow channel, while silicon-germanium (SiGe) bipolar transistor amplifiers are largely immune due to their very thin base.

Numerical simulation of the response of substrate traps to a voltage applied to the gate of a gallium arsenide field effect transistor

We report on a numerical simulation of the response of substrate traps to a voltage applied to the gate of a gallium arsenide field effect transistor (GaAs FET) using proprietary simulation software. The substrate is assumed to contain shallow acceptors compensated by deep levels. The ratio between the densities of deep and shallow levels is considered to be one hundred, which is a typical value for semi-insulating substrates. Although several traps may be present in the substrate but only the most commonly observed ones are considered, namely hole traps related to Cu and Cr, and the familiar native electron trap EL2. The current–voltage characteristics of the GaAs FET are calculated in the absence as well as in the presence of the above mentioned traps. It was found that the hole traps are affected by the gate voltage while the electron trap is not. This effect on the response of hole traps is explained by the fact that the quasi-hole Fermi level in the substrate is dependent on the gate voltage. However, the electron quasi-Fermi level in the substrate is insensitive to the gate voltage and therefore electron traps are not perturbed.

에너지 효율적 차세대 방송망 구축을 위한 증폭기 특성과 신호 모델

최근 지구 온난화에 따른 이산화탄소 배출량 감소 및 에너지 절약을 위하여 방송통신 기술 역시 에너지를 절약을 위한 연구가 시작되고 있다. 특히 방송통신 시스템의 전체 소비 에너지는 기지국에서 87.5%이상 차지하고 있지만 물리계층에서 에너지 효율성에 관한 연구는 전송용량을 총 전력 단일 상수로 나누어 분석하기 때문에 실제적인 에너지 특성을 분석하는데 문제점이 많다. 본 논문은 이와 같은 문제점을 해결하기 위하여 실제 증폭기에 사용되는 트랜지스터의 특성과 신호 모델에 관하여 간략히 소개한다. 이는 에너지 효율적인 방송통신 시스템을 설계하는데 이용 가능한 비선형 증폭기의 신호모델 그리고 증폭기의 특성을 고려한 기지국의 총 전력 사용량까지 포함하여 효율적인 에너지 효율을 계산하는 데 중요한 이해를 제시한다. In this paper, we investigate the characteristics of power amplifiers and simplified memoryless non-linear power amplifier models for energy efficient communication system. First, we present the transfer function of GaAs FET (Gallium Arsenide Field Effect Transistor) that is widely used for high power amplifier. From those investigations, we introduce the instantaneous efficiencies and methods of amplification by assuming that the saturated current is constant, while perfect linearity is exploited under knee voltage. Then, we discuss four non-linear power amplifier models in a baseband signal processing. Finally, we explain the specified total power consumption model in a base station to achieve the resonable analysis for energy efficient communication.

A Highly Integrated GaAs-based Module for DC-DC Regulators

There is a need and desire to push low voltage point-of-load voltage regulators (POL VRs) to higher switching frequencies. The main reason for this is to increase power density. Silicon MOSFET-based solutions are rapidly approaching their technology limits and are not capable of providing multi-MHz switching frequency for high current (>10A) applications. Gallium Arsenide (GaAs) field effect transistors (FETs) can switch much faster, enabling cost-effective, high-current, high switching frequency POL VRs. Recent advances in GaAs technologies have enabled the demonstration of 5MHz VRs and provide a path to even higher frequency (>50MHz) Power Supply in Package (PSiP) solutions. The high-speed GaAs power FETs are the “engine” to enable efficient high switching frequency POL VRs, but certain key elements must be designed appropriately to realize the desired performance. The gate driver and power path impedances must be minimized. To do this, a high level of integration is required, thus packaging is a critical element. New embedded die packaging solutions enable this high level of integration, dramatically reducing key parasitic impedances that can otherwise throttle performance, while also facilitating very compact multi-chip modules.

Indium Gallium Arsenide Based Non-Volatile Memory Devices with Site-Specific Self-Assembled Germanium Quantum Dot Gate

AbstractThis paper presents the implementation of indium gallium arsenide field-effect transistors (InGaAs FETs) as non-volatile memory using lattice-matched II-VI gate insulator and quantum dots of GeOx-cladded Ge as the floating gate. Studies have been done to show the ability of II-VI materials to act as a tunneling gate material for InGaAs based FETs, and GeOx-cladded Ge quantum dots having the ability to store charges in the floating gate of a memory device. Proposed structure of the InGaAs device is presented.

Bandwidth enhancement of a microstrip antenna using negative inductance as impedance matching device

AbstractIn this study, a novel technique for bandwidth enhancement of a microstrip antenna with a floating negative inductor matching network is presented. A compensation network consisting of three gallium‐arsenide field effect transistors is employed at the input of a microstrip antenna operating at 10 GHz. The performance parameters of the designed microstrip antenna with and without compensation network are compared. The simulation results show that compensation network can improve the bandwidth from 17.21% to 32.67%. © 2004 Wiley Periodicals, Inc. Microwave Opt Technol Lett 42: 476–478, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.20342

Highly moisture-resistive silicon nitride films prepared by catalytic chemical vapor deposition and application to gallium arsenide field-effect transistors

Moisture resistivity for silicon nitride (SiNx) films prepared by catalytic chemical vapor deposition (Cat-CVD) was examined. SiNx films prepared by Cat-CVD and those by plasma-enhanced chemical vapor deposition (PECVD) were subjected to the pressure cooker test (PCT) in H2O vapor at 2 atm and 121°C for 96 h. It was confirmed after PCT that the intensity of the signal due to Si–O bonds in Fourier-transform infrared absorption spectra remarkably increases for PECVD films although little increase is observed for Cat-CVD films. Low stress of the order of 10 MPa was also obtained for SiNx films prepared by Cat-CVD. SiNx passivation by Cat-CVD brings about low leakage current and high mutual conductance for gallium arsenide self-align-gate field-effect transistors.

Highly moisture-resistive silicon nitride films prepared by catalytic chemical vapor deposition and application to gallium arsenide field-effect transistors

Moisture resistivity for silicon nitride (SiN x ) films prepared by catalytic chemical vapor deposition (Cat-CVD) was examined. SiN x films prepared by Cat-CVD and those by plasma-enhanced chemical vapor deposition (PECVD) were subjected to the pressure cooker test (PCT) in H 2O vapor at 2 atm and 121°C for 96 h. It was confirmed after PCT that the intensity of the signal due to Si–O bonds in Fourier-transform infrared absorption spectra remarkably increases for PECVD films although little increase is observed for Cat-CVD films. Low stress of the order of 10 MPa was also obtained for SiN x films prepared by Cat-CVD. SiN x passivation by Cat-CVD brings about low leakage current and high mutual conductance for gallium arsenide self-align-gate field-effect transistors.

Bismuth based layered perovskite thin films as a charge storage material for low power nonvolatile gaas memory applications

This work details initial process development and integration of ferroelectric SrBi2Ta2O9 and SrBi2Ta2(1-x)Nb2xO9 for use in low power nonvolatile GaAs memory technology. A spin on process is used to deposit the ferroelectric thin films. Capacitance, hysteresis loop, and switched charge versus time data are presented for metal-ferroelectric-metal capacitors using platinum as the electrode material. Indications are that the substitution of niobium for tantalum in the layered perovskite structure increases both the non-volatile polarization and the coercive field of the material. N-channel transistor characteristics of the low power gallium arsenide field effect transistor contained in the 1T-1C memory bit are also presented. The results presented here imply that these materials warrant further research and process integration studies to realize low power non-volatile GaAs memory technology.

Thermal design of gallium arsenide MESFETs for microwave power amplifiers

In the traditional design of microwave power amplifiers using gallium arsenide field effect transistors, the active devices are mounted onto a thermally conducting heatsink, and matching circuits at the input and output take the form of microstrip, usually using aluminium oxide as the dielectric. The thermal attachment of the transistor is often a problem with this technology and the use of many bond wires can lead to manufacturing problems because of unpredictable phase shifts associated with their variable length. The author describes a number of surface mount alternatives to this technology and assesses the associated thermal implications. Three dielectric alternatives are considered, namely aluminium oxide, aluminium nitride and diamond.

The JILA Penning trap mass spectrometer

A Penning-ion trap mass spectrometer which is designed to make sub ppb mass measurements on ions is described. The spectrometer incorporates an external ion source for the injection of ions to be "weighed" into the trap. Novel features include a nonmagnetic alloy from which the trap electrodes are machined, as well as an ion detection system based on a superconducting inductor and a very low-noise amplifier incorporating a gallium-arsenide field-effect transistor (GaAs FET). Also discussed is a technique to increase the axial resistive damping constant for trapped ions using a regenerative detection circuit.

Residual phase noise measurements of VHF, UHF, and microwave components

The results of residual phase noise measurements on a number of VHF, UHF, and microwave amplifiers, both silicon (Si) bipolar junction transistor (BJT) and gallium arsenide (GaAs) field effect transistor (FET) based, electronic phase shifters, frequency dividers and multipliers, etc., which are commonly used in a wide variety of frequency source and synthesizer applications are presented. The measurement technique has also been used to evaluate feedback oscillator components, such as the loop and buffer amplifiers, which can play important roles in determining an oscillator's output phase noise spectrum (often in very subtle ways). While some information has previously been published related to component residual phase noise properties, it generally focused on the flicker noise levels of the devices under test, for carrier offset frequencies less than 10 kHz. The work reported herein makes use of an extremely low noise, 500 MHz surface acoustic wave resonator oscillator (SAWRO) test source for residual phase noise measurements, both close-to-and far-from-the-carrier. Using this SAWRO-based test source at 500 MHz, we have been able to achieve a measurement system phase noise floor of -184 dBc/Hz, or better, for carrier offset frequencies greater than 10 kHz, and a system flicker phase noise floor of -150 dBc/Hz, or better, at 1 Hz carrier offset. The paper discusses the results of detailed residual phase noise measurements performed on a number of components using this overall system configuration. Several interesting observations related to the residual phase noise properties of moderate to high power RF amplifiers, i.e., amplifiers with 1 dB gain compression points in the range of +20 to +33 dBm, are highlighted.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Thermal resistance of gallium-arsenide field-effect transistors

The paper describes some thermal simulations for heat flow in gallium-arsenide field-effect transistors where the effects of surface metallisation and via holes are modelled. The results were found to be significantly different to those previously published, which were based on simpler physical models. The effects of surface metallisation were found to be important in modelling the thermal resistance but the effects of via holes less so, using current technological limitations.

Gallium arsenide field-effect transistor by close spaced vapor transport epitaxy

For the first time gallium arsenide field-effect transistors have been made using epitaxial layers grown by the close spaced vapor transport technique (CSVT). The layers were unintentionally doped and their free-carrier concentration was adjusted through the growth parameters to around 1017 cm−3. For the growth of the layers, water vapor was used as transporting gas. This transistor confirms the capability of the simplest and most inexpensive epitaxial technique (CSVT) for growing device quality gallium arsenide epitaxial layers.

Optimum noise source impedance determination for GaAs FETs at room and cryogenic temperatures

Abstract An analytical technique is developed to determine the optimum noise source impedance for an extrinsic, or packaged, gallium arsenide field-effect transistor (GaAs FET) using only the small-signal s-parameters and the minimum noise figures available from the manufacturer's data sheet. The procedure is then modified to treat the special case of the intrinsic, or chip, GaAs FET as well. The technique is then extended to determine the optimum noise source impedance and minimum noise figure at cryogenic temperature using the room temperature results. The procedure is used to determine the optimum noise source impedance of a Mitsubishi MGF-1412 and a Mitsubishi MGFC-1412 at room and cryogenic temperature. At room temperature and 4 9 GHz, the technique yields an optimum noise source impedance of 28·4 ft -Ω64·1 Ω for the extrinsic device as compared with the measured optimum noise source impedance of 20 Ω + j55Ω. At cryogenic temperature, the optimum noise source impedance obtained is 21·1 Ω + j70·8 Ω as...

Noise models for gallium arsenide field-effect transistors at room and cryogenic temperatures

An analytical technique is developed to determine the optimum noise source impedance for a chip gallium arsenide field-effect transistor (GaAs FET) using only the small-signal s-parameters and the minimum noise figures available from the manufacturer's data sheet. The technique is then extended to determine the optimum noise source impedance and minimum noise figure at cryogenic temperatures using the room temperature results. The procedure is used to determine the optimum noise source impedance of a Mitsubishi MGFC-1412 at room and cryogenic temperatures. At room temperature, the technique yields an optimum noise source impedance that is 16% in error as compared with the measured optimum noise source impedance. At cryogenic temperatures, the result is in error by 19% for the real part and by 9% for the imaginary part as compared with the available experimental value, and by 7% for the real part and by 12% for the imaginary part as compared with a more rigorous theoretical result.

Capacitance and conductance deep level transient spectroscopy in field-effect transistors

An analysis of conductance transients in field-effect transistors for small values of drain-source voltage is presented which enables absolute values of trap concentration to be evaluated. The relationships use parameters which can be easily measured as distinct from the estimated values of mobility profiles used in previously published calculations. Excellent quantitative agreement between capacitance and conductance results on large area gallium arsenide field-effect transistors has been obtained. In addition, conductance deep level transient studies have demonstrated that the method of measurement and analysis can be used for micron and submicron devices which are much too small for capacitive measurements.