Noise models for gallium arsenide field-effect transistors at room and cryogenic temperatures

Abstract

An analytical technique is developed to determine the optimum noise source impedance for a chip gallium arsenide field-effect transistor (GaAs FET) using only the small-signal s-parameters and the minimum noise figures available from the manufacturer's data sheet. The technique is then extended to determine the optimum noise source impedance and minimum noise figure at cryogenic temperatures using the room temperature results. The procedure is used to determine the optimum noise source impedance of a Mitsubishi MGFC-1412 at room and cryogenic temperatures. At room temperature, the technique yields an optimum noise source impedance that is 16% in error as compared with the measured optimum noise source impedance. At cryogenic temperatures, the result is in error by 19% for the real part and by 9% for the imaginary part as compared with the available experimental value, and by 7% for the real part and by 12% for the imaginary part as compared with a more rigorous theoretical result.