Gain Mismatch Research Articles

Wideband N-Path-Based Phased-Array Receiver With Gain and Phase Mismatch Calibration

Wideband N-Path-Based Phased-Array Receiver With Gain and Phase Mismatch Calibration

Ultrabroad bandwidth of quasi-parametric amplification beyond the phase-matching limit.

Quasi-parametric amplification (QPA), a variant of optical parametric amplification, can release the phase-matching requirement owing to the introduction of idler dissipation, and thus may support ultrabroad bandwidth. Here we establish the gain-dispersion equation for QPA, which reveals the interplay of signal gain, idler dissipation and phase mismatch. The idler dissipation dramatically enhances the gain bandwidth, which breaks the limit set by phase matching. We theoretically demonstrate that QPA with strong dissipation allows high-efficiency few-cycle pulse amplification in those nonlinear crystals without a magic phase-matching solution.

A 0.55-mm2 8-bit 32-GS/s TI-SAR ADC with optimized hierarchical sampling architecture

This paper analyzes the bandwidth of the time-interleaved analog-to-digital converter (TI-ADC) with hierarchical sampling and presents an 8-bit 32-GS/s TI-ADC in 28-nm CMOS. The front-end sampler is implemented by a two-stage hierarchical sampling architecture to extend the analog input bandwidth. The 32-way sub-ADCs are realized with 2b/cycle successive approximation register (SAR) architecture and non-binary search strategy, which meet the requirements of high speed, medium resolution, and strong robustness. Multi-phase low-jitter clock tree is designed based on the delay-locked loop (DLL). Calibration methods for timing skew, offset and gain mismatches are introduced to improve accuracy. The proposed TI-SAR ADC achieves an analog input bandwidth of 23.7 GHz. It occupies an active area of 0.55 mm2 and consumes 356 mW at 1.8/1 V supply.

Identification and Compensation of Gain Mismatches for Whole-Angle Microhemispherical Resonator Gyroscope Based on Modal Reversal

Identification and Compensation of Gain Mismatches for Whole-Angle Microhemispherical Resonator Gyroscope Based on Modal Reversal

Adaptive correcting combiner for arrays of acoustic vector sensors with phase and gain mismatch errors

This paper introduces a method to coherently combine the signals collected by the directional and omnidirectional channels of an Acoustic Vector Sensor array when the supporting frame is introducing a phase and gain mismatch error. The proposed method adaptively estimates the distortion introduced by the supporting frame and corrects the measurements at the sensors before their coherent combination. The paper evaluates the Cramer-Rao Lower Bound for Direction of Arrival estimation and compares the bound with simulated data and real data collected at sea. The proposed method is asymptotically efficient, reaching the lower bound for sufficiently large values of the signal to noise ratio.

A SAR ADC for multichannel synchronous signal acquisition

A synchronous sampling multichannel ADC is proposed to sample several signals at the same time and digitize the sampled signals in sequence. Instead of using multiple ADCs or multiple samplers, a modified SAR ADC with multiple capacitive DACs is applied to largely save area and reduce gain and offset mismatches between channels. A common-mode voltage resampling technique is proposed to reduce crosstalk errors between the multiple input signals below the ADC noise floor. To verify the ADC structure, a 10-bit 4-channel SAR ADC has been prototyped and implemented with a 180-nm CMOS technology. The ADC area is 0.325 mm2 (without PAD). At the sampling frequency of 250 kHz per channel, it uses 62 μW to achieve 9.38 ENOB for four input signals. The resolutions of the four channels are mainly limited by the DAC performances.

Digital Background Calibration Techniques for 2GS/s 12bit Time-Interleaved Pipelined ADC

This paper presents digital background(BG) calibration techniques which are utilized to correct both inter-stage gain error (IGE) and inter-channel mismatches in a 12-bit 2GS/s 4-channel time-interleaved pipeline ADC. The inter-stage gain is mitigated by Least Mean Square (LMS) based calibration with a proposed Pseudo Noise (PN) codes injected into 1.5bit MDAC stages, which has neither input amplitude limitation nor comparator requirement. The inter-channel offset and gain mismatches are eliminated by Modified Moving Average (MMA) and LMS –based calibrations respectively. The inter-channel sampling time mismatch is estimated by correlation function and compensated by digital-controlled delay line. Simulation results in 40nm CMOS show that the presented calibration techniques improve the 2GS/s TI ADC SNDR from 46.2138dB to 6761.49dB 35dB and SFDR from 50.8150.09dB to 82.3574.04dB with a Nyquist input, consuming only 23.3mW power in a 184um*183um area.

Antena Tatasusun Pantulan Boleh Konfigurasi Semula: Latar Belakang, Klasifikasi dan Mekanisme Boleh Konfigurasi

Reflectarray antennas have emerged as one of the most suitable choice for 5G network base station antennas due to their ability to combine the advantages of parabolic reflectors and phased array antennas. These antennas offer a lightweight structure, high gain, and low impedance mismatch losses. High gain and low loss are crucial factors in ensuring the antenna delivers low latency and high-quality 5G radio signals. The application of 5G technology becomes more practical and efficient with the capability to adjust the functionality of a single 5G antenna or enable reconfiguration. This reconfigurable technique simplifies the multi-antenna systems and significantly reduces costs, making it more practical and systematic. Furthermore, this reconfigurability is particularly beneficial for satellite applications, as it allows for the reconfiguration of the signal in the event of satellite movement on the space. This paper aims to discuss the historical development of reconfigurable reflectarray antennas, focusing on the innovations in each configurable mechanism. The paper further explores the classification of configurations employed by this antenna, encompassing frequency configuration, radiation pattern, polarization, and hybrid configurations that integrate multiple existing configuration classifications. Finally, the research paper provides a discussion of the most recent research and innovations in the configurable mechanisms of reflectarray antennas.

An improved wide-range, low-complexity, fully-parallel digital background timing mismatch calibration method for dual-channel TIADC based on perfect reconstruction filter bank

This paper presents a fully-digital background calibration method for calibrating timing mismatch in dual-channel time-interleaved analog-to-digital converter (TIADC). The proposed method estimates timing mismatch by performing correlation calculations on the outputs of sub-channels and corrects this mismatch using the improved perfect reconstruction filter bank (PRFB). The PRFB, which is improved by employing a polynomial fitting method, offers superior performance with fewer filter taps and extends the timing mismatch correction capability to almost the entire sampling clock cycle. The improved PRFB uses only one twentieth of the taps used in the original PRFB, and its dual-channel FIR filters have anti-symmetric taps. To enhance the real-time calibration capability of the system, this paper gives a fully-parallel hardware structure for calibrating offset, gain, bandwidth, and timing mismatches. The effectiveness of the proposed hardware structure is verified through a 10-bit 3GS/s dual-channel TIADC test platform. Simulation and measurement results show that the proposed calibration method significantly improves the signal-to-noise-and-distortion (SNDR) and spurious-free dynamic range (SFDR) of both single-tone and multi-tone input signals, which makes the proposed method a viable solution for practical TIADC applications.

Drift Resilient Frequency-Based Sensor Interface Architectures with Adaptive Clock Frequency

Maintaining the accuracy of a sensor system across various operating conditions has always been a challenge, especially for those operating in harsh surroundings such as a radiation environment. Concerning frequency-based sensor interfaces, supply voltage drifts and gain shift of the voltage-to-frequency converter (VFC) are critical design issues. These manifest as gain, offset, and linearity errors at the system level and therefore require continuous correction mechanisms. In this paper, dynamic gain and offset error-compensated open-loop frequency-based sensor interface architectures with adaptive clock frequency are proposed, which result in a ratiometric digital output. To address the mismatch issue, two architectures, one with periodic swapping of the VFCs’ inputs and outputs, and the other with the use of a single analog-to-digital converter (ADC) as an analog front end, are developed. The concepts were demonstrated with implementations on a Zynq board (ZYBO). The results of the first architecture showed that for a 25% gain mismatch between the VFCs, the output gain error was reduced from around 7.4% to 0.79% and the offset error was reduced from around 11.8% to 0.01%. Additionally, for the second architecture, a maximum of 0.11% gain error and 0.1% offset error were recorded for an emulated ±25% supply drift.

An All-Digital Background Calibration Technique for M-Channel Downsampling Time-Interleaved ADCs Based on Interpolation

An all-digital background calibration technique for gain, timing, and bandwidth mismatches in the time-interleaved analog-to-digital converter (TI-ADC) is presented in this brief. The proposed calibration technique employs an interpolation filter and a Hilbert filter to generate a reference sequence for each sub-ADC. Subsequently, adaptive filters are used to calibrate the mismatch errors, the coefficients of which are updated by the least mean square (LMS) algorithm. The advantage of the technique is that it only requires the output sequence of the TI-ADC without any additional information or extra reference channels. Moreover, it is effective for the M-channel TI-ADC sampling of single-tone, multi-tone, and wideband signals in any Nyquist Band. The frequency shifting is analyzed via filter bank theory, avoiding the complex signal introduction. The simulation for 4-channel TI-ADC with 5 sinusoidal input signals, shows that the proposed technique can improve the SNDR and SFDR by 37 dB and 54 dB, respectively.

A foreground digital calibration algorithm for time-interleaved ADCs with low computational complexity

In front of the offset, gain, timing, and bandwidth mismatch errors, time-interleaved analog-to-digital converters (TIADCs) are usually calibrated to achieve satisfying performance. In this paper, we propose a new digital calibration approach for TIADCs, including the direction-distance search algorithm and multiplier-free gradient descent method. Compared to state-of-the-art multiplication-less techniques, this approach significantly reduces time complexity by minimizing search space dimension, subtracting the number of searches, and varying iteration step size. Notably, no multiplier is needed in the mismatch estimation, resulting in a much lower computational complexity than in previous work. For a 12-bit 4-channel TIADC, simulation results show that the signal-to-noise-and-distortion ratio is improved from 25 dB to 65 dB within the duration of 1600 samples. The proposed calibration circuit is synthesized targeting standard 28-nm technology, occupying the area of 0.014 mm2 and dissipating the power of 19 mW at 2.8 GHz clock frequency.

A Foreground Mismatch and Memory Harmonic Distortion Calibration Algorithm for TIADC

This paper proposes a foreground digital calibration algorithm that estimates and corrects the offset, gain, and time-skew mismatches for time-interleaved analog-to-digital converters (TIADCs) furthermore our algorithm is designed to correct for harmonic distortion introduced by the presence of a nonlinear front-end. We propose a novel simplified non-linear model in place of the more complex conventional Volterra series based structure. The mismatch estimation technique based on the Fast Fourier Transform (FFT) is proposed to estimate the various time-interleaving mismatches simultaneously. A Taylor-based technique is applied to compensate for these mismatches. We also consider the choice of an appropriate time reference for the time-skew correction algorithm by theoretical analysis. The nonlinear distortion correction technique is based on estimating and inverting an assumed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3^{\text {rd}}$ </tex-math></inline-formula> order nonlinearity with a fractional delay. To do this, we design a customized filter in an offline process. Our algorithms are designed to operate in any Nyquist zone. The proposed techniques are verified by a Xilinx Zynq UltraScale+ RFSoC ZCU111 evaluation kit containing a 12-bit, 4.096 GHz TI-ADC with 8 sub-ADCs operating in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2^{\text {nd}}$ </tex-math></inline-formula> Nyquist zone. Accordingly, we observed an improvement in SFDR of 14 dB for mismatch calibration alone and up to another 12 dB with nonlinear correction enabled.

A digital calibration technique for N-channel time-interleaved ADC based on simulated annealing algorithm

This work proposes a digital calibration technique for time-interleaved analog-to-digital converters with any interleaving factor, which can calibrate gain, timing, and bandwidth mismatches. A simulated annealing algorithm is used to search the optimum calibration coefficients for the error correction module, possessing a customizable search range and precision. Furthermore, the calibration technique is effective for the single-tone, and multi-tone input signals in the whole Nyquist frequency. In the case of an 8-channel 12-bit TI-ADC with fixed mismatches, simulations show an SNDR improvement of 46.38 dB for a single-tone input and an SNDR improvement of 29.23 dB for a multi-tone input.

A Fractional-N CP-PLL with fast two-point modulation calibration using duty-cycle and polarity tracking technique in 110-nm CMOS

This article proposes a fractional-N charge pump phase-locked loop (CP-PLL) with fast two-point modulation calibration using Duty-Cycle and Polarity Tracking technique. The proposed calibration method can perform delay and gain calibration within 15 μs, respectively. A DTC-assisted Polarity Detector is used to track and countervail the propagation delay of two modulation paths. A TDC-based Duty-Cycle Detector is used to monitor and compensate the two paths gain mismatch. By comparing the code with the threshold set in the look-up table (LUT), a quick calibration can be achieved. To maintain high out-band phase noise performance and stronger robustness, a Class-C oscillator using Capacitance Desensitization technique and Cross-Bias technique is adopted in the design. The proposed CP-PLL is implemented in a standard 110-nm CMOS technology, occupying 2.7 mm2 silicon area. The post-simulation results show the proposed calibration method can calibrate the delay/gain mismatch within 30 μs. Fast calibration mode supports calibration time within 62.5 ns. The phase noise performance is −91-dBc/Hz@100 kHz, −119-dBc/Hz@1 MHz. The entire CP-PLL dissipates 20.9-mW and achieves an RMS jitter of 6.2 ps, corresponding to a figure of merit (FOM) of −211-dB.

Self-Calibrated Digital Two-Point Modulator for BLE RF Transmitter

In this brief, a self-calibrated two-point delta-sigma modulation technique for a CMOS RF transmitter is proposed for use for a voltage-controlled oscillator (VCO) and a delta–sigma modulator in a frequency synthesizer. By using the counter to calibrate the frequency deviation of two-point modulation to the desired value, the gain mismatch between two paths can be completely calibrated by modifying the gain of the VCO path. The frequency modulation therefore guarantees a robust performance against PVT variations without using any additional circuit. This technique is applied to Bluetooth Low Energy (BLE) applications. The proposed Two-Point Modulation achieves error vector magnitude (EVM) of −29.3 dB at 1 Mbps and is implemented in 55 nm CMOS process technology. The area of the chip is 0.28 mm2 and its power consumption is 2.9 mW.

Digital Calibration for Gain, Time Skew, and Bandwidth Mismatch in Under-Sampling Time-Interleaved System

This paper presents an all-digital background calibration method for gain, time skew, and bandwidth mismatch in M-channel under-sampling time-interleaved analog-to-digital converters (TI-ADCs) systems. Firstly, the characteristics of offset, gain, time skew, and bandwidth mismatch on the TI-ADCs system are analyzed. Secondly, a parameter vector is constructed to correct gain, time skew, and bandwidth mismatch. Then, the constructed parameter vector is calculated with the bandpass fractional delay filter and least squares (LS) algorithm. Based on the bandpass fractional delay filter, the proposed technique can work for ultra-high frequency signals. Additionally, the constructed parameter vector has a smaller number of filter taps than the derivative filter or Hilbert filter. Therefore, fewer computing resources are used to correct the input signal after obtaining the proposed parameter vector. Finally, there are matrix inversions in the LS algorithm. Additionally, implementing matrix inversion within FPGA is complex. For this reason, solving a system of linear equations is used to replace matrix inversions. The LS algorithm is affected by quantization error and white Gaussian noise. The simulation results verify the effectiveness of the proposed algorithm when the SNR of sub-ADC is from 30 dB to 100 dB or the ENOB of sub-ADC is from 5-bit to 16-bit. They show that the proposed algorithm is not limited by the first sub-ADC Nyquist. Additionally, the measurement results show that the proposed method is effective in the actual time-Interleaved system.

Time-interleaved system mismatch estimation based on correlation function and particle swarm optimization algorithm.

The time-interleaved analog-to-digital converters (TIADCs) technique is an efficient solution to improve the sampling rate of the acquisition system with low-speed ADCs. However, channel mismatches such as gain mismatch, time skew mismatch, and offset mismatch may seriously degrade the performance of TIADC. Furthermore, for high-speed signal acquisition, the gain and time skew mismatches would vary with the signal frequency, and the traditional fixed model does not work any longer. In this paper, a series of sinusoidal signals are adopted to estimate the variable mismatches. First, an autocorrelation-based approach is presented to estimate the gain mismatch. The information about the gain mismatch is extracted from the autocorrelation function of sub-ADC output samples. Then, the time skew mismatch is estimated by utilizing the particle swarm optimization algorithm. The reported simulation results show that the mismatches can be accurately estimated. Finally, a commercial 12.5 GSPS four-channel TIADC system is utilized to verify the performance of the proposed method. The spurious free dynamic range of the system can be improved by about 20 dB, and the effectiveness of the proposed estimation method is demonstrated.

A Background Calibration for Joint Mismatch in the OFDM System With Time-Interleaved ADC

Time-interleaved analog-to-digital converters (TIADCs) are widely used in multi-Gigabit communication systems due to their high conversion rates. In practice, the offset, gain, and time-skew mismatch of TIADC significantly degrade the performance of an OFDM-TIADC system. It is also the case that the addition of channel coding can even degrade the system further. In this brief, we analyze the modulation error floor caused by mismatches and propose a two-stage background joint mismatch calibration using Least-square estimation to detect the offset and gain mismatches, and the time-skew mismatches are estimated by golden-section search. This method significantly reduces the bit error rate (BER) and improves the reliability of the OFDM-TIADC system.

All-digital calibration algorithm based on channel multiplexing for TI-ADCs

An adaptively calibration structure featured by channel multiplexing that can simultaneously calibrate the offset, gain, and timing mismatch errors existing in TI-ADC (Time-Interleaved ADC) channels in pure digital domain is proposed, which focuses on the problem of limited input signal bandwidth and high calibration hardware overhead. In error compensation aspect, these three mismatch errors are compensated simultaneously by adaptive method. The gain mismatch compensation employed here can help to overcome the deviation that would exist when the first-order Taylor compensation was employed alone for the timing mismatch, which can significantly improve the calibration effect in high-frequency band instead of employing complex high-order Taylor compensation structure. The total calibration algorithm is implemented using FPGA. For the 4-channel, 1 GS/s and 14-bit TI-ADC, the signal-to-noise distortion ratio (SNDR) of the system is increased from 26.19 dB to 84.37 dB, and the spurious free dynamic range (SFDR) is increased from 29.35 dB to 98.49 dB when the input signal normalized frequency f in / f s is 0.975.