GaAs Metal-semiconductor Field-effect Transistors Research Articles

The volume production of GaAs and related compounds by MOVPE

An increasing market for advanced telecommunications has dramatically increased the demand for high-performance heterostructure compound semiconductor devices. Among a variety of epitaxial technologies for compound semiconductor materials growth, metalorganic vapor-phase epitaxy has succeeded in producing a wide variety of epitaxial wafers for optical devices such as laser diodes, optical detectors, and high-brightness light-emitting diodes. Although molecular-beam epitaxy has been applied to high-speed electronic devices, the continuous R&D efforts on metalorganic vaporphase epitaxy have made the technology a valuable alternative. The performance of the most advanced heterostructure devices, such as pseudomorphic high-electron mobility transistors or heterostructure bipolar transistors, greatly depends upon the qualities of the epitaxial wafer, as does the manufacturing cost. In the future, epitaxial materials supply must become a robust, real-production technology in order to keep the cost-performance ratio of the heterostructure devices competitive with other technologies (such as ion-implanted GaAs metal-semiconductor field-effect transistors) and silicon-based devices.

Symptoms of stress-induced gain degradation in power MESFETs

GaAs metal-semiconductor field effect transistors configured as microwave power amplifiers have been observed to degrade under normal device operations at high gate-to-drain fields. The nature of this degradation is an increase in the gate current, with a subsequent decrease in the gain. We present evidence that crystallographic defects in the active region are responsible for this “power slump” and that these defects originate during device operation due to the high strain fields which exist as the result of passivation layer processing. Strain data and x-ray topographic images support our assertion that passivation layer processing induces high strain in and around the gate-to-drain region of the device. Topographic images show that an increase in dislocation density occurs in the highly stressed regions after power slump. By varying deposition parameters, we can produce passivation films, which induce less stress in the active region, resulting in less dislocation generation and a less severe power slump.

A self-aligned gate GaAs MESFET with p-pocket layers for high-efficiency linear power amplifiers

This paper describes a newly developed GaAs metal semiconductor field-effect transistor (MESFET)-termed p-pocket MESFET-for use as a linear power amplifier in personal handy-phone systems. Conventional buried p-layer technology, the primary technology for microwave GaAs power MESFET's, has a drawback of low power efficiency for linear power applications. The low power efficiency of the buried p-layer MESFET is ascribed to the I-V kink which is caused by holes collected in the buried p-layer under the channel. In order to overcome this problem, we have developed the self-aligned gate p-pocket MESFET which incorporates p-layers not under the channel but under the source and drain regions. This new MESFET exhibited high transconductance and uniform threshold voltage. The problematic I-V kink was successfully removed and an improved power efficiency of 48% was achieved under bias conditions, which resulted in adjacent channel leakage power at 600-kHz offset as low as -59 dBc for 1.9-GHz /spl pi//4-shift QPSK modulated input.

Reliability of GaAs Metal-Semiconductor Field Effect Transistors Grown on Si Substrates

We report on the reliability of metal-semiconductor field effect transistors (MESFETs) fabricated on GaAs/Si compared to that of MESFETs on GaAs/GaAs, based on the results of the high-temperature storage test under dc bias. The failure mode was the non-pinch-off phenomenon with the increase in drain current for both types of MESFETs. From the results of observation using a scanning electron microscope and Auger electron analysis, gate metal dispersion and the possibility of a reaction between the metal and the GaAs channel were revealed for the failed devices. The mean time to failure for the MESFETs/Si at a channel temperature of 130°C was predicted to be 1.28×106 h from the storage test, which was almost equal to that for MESFETs/GaAs. This result indicates that the lifetime of MESFETs/Si is comparable to that of MESFETs/GaAs, and the high density of dislocations in the GaAs/Si does not affect the reliability of the devices.

Effects of active-channel thickness on submicron GaAs metal semiconductor field-effect transistor characteristics

In small signal GaAs metal semiconductor field-effect transistor (MESFET) fabrication technology where a gate recess is required, the optimum value of residual channel thickness is one of the most crucial parameters for high transconductance operation of the device. The effects of active channel thickness on device characteristics have been investigated. In a different strategy to that of previously reported work, in this study we have fixed gate length Lg at 200 nm and varied the channel thickness, a from 100 to 40 nm. This means that the shape of the depletion layer, which is a function of gate length, was largely fixed for all the devices. The variation in the device characteristics depended on the change in the active channel thickness, which modifies the field distribution inside the channel. It was found that, for optimum doping concentration, the value of transconductance increases in a parabolic fashion by decreasing the aspect ratio (Lg/a) of the device, and a highest value of transconductance is observed at Lg/a≈2. This aspect ratio is 2–3 times lower than the conventional reported values.

Generalized dc model of GaAs optical field effect transistor considering ion-implanted profile

Basic concepts and theory are developed for the effect of optical radiation on the dc characteristics of a generalized model of an ion-implanted GaAs metal-semiconductor field effect transistor (MESFET). The optical radiation is allowed to fall on a transparent or semitransparent Schottky gate and the spacing between the gate source and gate drain. The continuity equations are solved for the excess carriers in the depletion region below the Schottky gate in the channel region and in the depletion region at the junction of the active layer and the substrate. The current-voltage (/- V) characteristics show a remarkable enhancement in the drain source current compared to opaque gate optically controlled field effect transistor (OPFET) (a special case of the generalized dc model). This highlights the importance of two photovoltages developed across the Schottky junction and the channel-substrate junction. The transconductance, the channel conductance, and the photovoltages are also observed to be strongly affected by the flux densities.

Electroluminescence Measurement of n+ Self-Aligned Gate GaAs MESFETs

We studied the electroluminescence (EL) for n+ self-aligned gate GaAs metal-semiconductor field-effect transistors (MESFETs) at room temperature. It has been found that the spatial distribution of the EL intensity is dependent on the luminescence energy. The EL peak with bandgap energy is observed at a region between the source and the gate metals, while the EL with an energy higher than the band gap energy is observed on the drain-side edge of the gate. By studying the correlation between the integrated EL intensity and the drain/gate current, it is concluded that the electron-hole recombination is a dominant luminescence mechanism for both the high and low energy regions for the present n+ self-aligned gate GaAs MESFETs.

A simple one-dimensional model for the explanation and analysis of GaAs MESFET behavior

The explanation of GaAs metal-semiconductor field effect transistor (MESFET) operation often involves the use of simplistic analytical formulae, which serve to obscure the more subtle physics of device action. The authors consider here a simple one-dimensional (1-D) model for GaAs MESFETs, which avoids more confusing numerical modeling schemes, yet still facilitates an analysis of the physical functionality of the device. The model takes into account current saturation due to either velocity saturation or channel pinch-off, the modulation of effective gate length and the series resistance of the regions beyond the gate. The results of the model have been compared to experimental data readily obtained from the literature, and the agreement has been shown to be good.

Optically induced measurement anomalies with voltage-tunable analog-control MMIC's

Monolithic microwave integrated circuits (MMIC's) may be measured under relatively high-intensity lighting conditions. Later, when they are packaged, any anomalies found in subsequent measurements could be attributed to unwanted parasitics or box modes associated with the packaging. However, optical effects may not always be considered by radiofrequency (RF) and microwave engineers. For the first time, a qualitative assessment is given for the effects of photonic absorption on three broad-band voltage-tunable analog-control circuits. Each circuit has a different function, with each field-effect transistor (FET) operating in a different mode: a hot FET in a variable-gain amplifier, a cold FET in an analog attenuator, and an FET varactor in an analog phase shifter. All three circuit functions have been implemented using two different FET-based technologies. The first with ion-implanted 0.5-/spl mu/m GaAs metal-semiconductor FET's (MESFET's) in circuits operating at either 3 or 10 GHz. The second employs epitaxially grown 0.25-/spl mu/m AlGaAs-InGaAs pseudomorphic high electron-mobility transistors (HEMT's) in circuits operating at 38 GHz. All the MMIC's were fabricated using commercial foundry processes and illuminated under conventional optical microscope lighting conditions. Prominent error peaks have been found at bias points unique to the three different circuit topologies. Large error peaks are found with the MESFET-based circuits, while much smaller error peaks are achieved with the corresponding pseudomorphic HEMT (pHEMT) based circuits.

A 40-Gbit/s superdynamic decision IC fabricated with 0.12-μm GaAs MESFET's

This paper describes a 4O-Gbit/s decision integrated circuit (IC) fabricated with 0.12-/spl mu/m gate length GaAs metal-semiconductor field-effect transistors (MESFET's). A superdynamic flip-flop circuit and a wide-band amplifier were applied in order to attain 40-Gbit/s operation. A conventional static decision IC was also fabricated for comparison. The dynamic decision IC operated up to 40 Gbit/s, which is twice as fast as the conventional static decision IC. Error-free 40-Gbit/s operation is the fastest among GaAs MESFET decision IC's.

VCSELs bonded directly to foundry fabricated GaAs smart pixel arrays

This letter reports the flip-chip bonding of an 8×8 array of free standing VCSELs to a foundry fabricated GaAs metal-semiconductor field-effect transistor (MESFET) smart pixel array. The VCSELs have oxide defined apertures and are co-planar bonded directly to smart pixels which perform the selection function of a data filter. The V/sub th/ and series resistance of the VCSELs were on average approximately 2.1 V and 250 /spl Omega/, respectively, which indicates that good electrical contact was obtainable with this process. The I/sub th/ ranged between 2-4 mA, with a corresponding output power of between 400 μW and >1.0 mW depending on aperture size.

Thermal degradation mechanism of Ti/Pt/Au Schottky contact to n-type GaAs

The thermal stability of Ti/Pt/Au Schottky gates on high-low doped GaAs metal–semiconductor field-effect transistors (MESFETs) was investigated in the temperature range of 300–500 °C, using current–voltage and capacitance–voltage measurements and cross-sectional transmission electron microscopy with energy dispersive x-ray spectroscopy. At annealing temperatures >350 °C, the interfacial reactions cause the formation of a layered structure of Ti/Ti–Ga/Ti–As/GaAs. The depth distribution of electron concentration moves toward the Ti/GaAs interface as the annealing temperature increases. This is due to the growth of Ti–As, followed by the reduction of the channel thickness. The activation energy for the growth of Ti–As is determined to be 1.74 eV. The electron concentration in the channel layer decreases with the increase of the annealing temperature. This is due to the out-diffusion of Ga to the Ti film, resulting in the production of acceptor-type Ga vacancies and thereby the decrease of electron concentration in the channel. The activation energy for the reduction of electron concentration, equal to the formation energy of the acceptor-type Ga vacancies, is determined to be 1.42 eV. This is closed to the activation energy of 1.3 eV for the device failure obtained at annealing temperatures ranged from 300 to 350 °C. From these observations, it is proposed that the thermal degradation of GaAs MESFETs at temperatures <350 °C, mainly proceeds by the electron compensation with acceptor-type Ga vacancies in the channel, whereas it occurs by the growth of Ti–As below the original Ti/GaAs interface at temperatures >350 °C.

Compression in transconductance at low gate voltages in submicron GaAs metal semiconductor field-effect transistors

In submicron GaAs metal semiconductor field-effect transistors, the shift in the transconductance (gm) peak towards the high negative gate voltage end is often observed. Factors causing this abnormality were investigated. It is believed that if the surface potential and the Schottky barrier potential are of the same order of magnitude then there will be a strong probability that the peak gm value will appear at high negative gate voltages rather than near zero gate bias. It was shown that under these circumstances the drain current at low gate biases is not under the direct influence of gate depletion but rather is controlled by surface depletion in the gate-drain gap. At high negative gate voltages, depletion under the gate has the dominant effect on channel current, and the device exhibits an improved performance. Recessed gate technology is thought to be a solution to eliminate the surface state effects of a free drain-source surface. It was shown that a simple gate recess will not eliminate the possibility of gm compression and shift unless the Schottky barrier potential is greater than the free-surface potential.

0.1 μm WSiN-gate fabrication of GaAs metal-semiconductor field effect transistors using electron cyclotron resonance ion stream etching with SF6–CF4–SiF4–O2

We investigate etching characteristics of WSiN gates using electron cyclotron resonance ion stream etching with a SF6–CF4–SiF4–O2 gas mixture, and we fabricate 0.1 μm WSiN gates for ultrahigh speed GaAs metal-semiconductor field effect transistors (MESFETs). A vertical WSiN gate etched pattern is obtained as a result of CF4 addition. Moreover, uniform etching over the entire wafer can be attained with high selectivity between the WSiN and the GaAs and with accurate control of the gate length. A current-gain cutoff frequency (fT) of 131.4 GHz with a 3σ value of 5.0 GHz in whole wafer has been obtained for 0.1 μm gate GaAs MESFETs.

Tunable optical Doppler frequency detector usingsemi-insulatingGaAs semiconductor-metal field-effect transistors

A tunable optical Doppler frequency detector is demonstrated in semi-insulating GaAs metal-semiconductor field-effect transistors (MESFET) based on moving space charge field effects. The application of the gate bias voltage, which modifies the free carrier density in the conducting channel of the device, modulates both the response time as well as the magnitude of the photocurrent generated by non-stationary optical interference patterns.

Pd–Ge–Au Based Hybrid Ohmic Contacts to High-Low Doped GaAs Field-Effect Transistor

Effects of an intermediate layer, such as Mo or Ti, have been studied for developing Pd–Ge–Au based hybrid ohmic contacts in a high-low doped GaAs metal-semiconductor field-effect transistor (MESFET). The Pd–Ge–Au contact without the intermediate layer produces an alloyed AuGe contact at a high annealing temperature above 400° C. When Mo is added between Pd/Ge and Au, nonspiking Pd/Ge contact is formed at a low annealing temperature of 300° C. The addition of Ti, however, results in an ohmic contact with a low resistance of 0.43 Ω· mm in a wide annealing temperature ranging from 340 to 420° C. Auger depth profile and X-ray diffraction results suggest that the low resistance of the Pd/Ge/Ti/Au ohmic contact is due to formation both the Pd/Ge contact and AuGe contact through the appropriate control of Au indiffusion by Ti. The MESFET with the Pd/Ge/Ti/Au contact displays good DC characteristics. This supports that the Pd/Ge/Ti/Au contact is well suitable for application to high-low doped GaAs MESFETs due to its low-resistance and wide-process-window.

Electrical and microstructural characteristics of Ge/Cu ohmic contacts to n-type GaAs

It is shown that Cu–Ge alloys prepared by depositing sequentially Cu and Ge layers onto GaAs substrates at room temperature followed by annealing at 400 °C form a low-resistance ohmic contact to n-type GaAs over a wide range of Ge concentration that extends from 15 to 40 at. %. The contacts exhibit a specific contact resistivity of 7 × 10−7 Ω cm2 on n-type GaAs with doping concentrations of 1 × 1017 cm−3. The contact resistivity is unaffected by varying the Ge concentration in the range studied and is not influenced by the deposition sequence of the Cu and Ge layers. Cross-sectional high-resolution transmission electron microscopy results show that the addition of Ge to Cu in this concentration range causes Cu to react only with Ge forming the ξ and ε1–Cu3Ge phases which correlate with the low contact resistivity. The ξ and ε1–Cu3Ge phases have a planar and structurally abrupt interface with the GaAs substrate without any interfacial transition layer. It is suggested that Ge is incorporated into the GaAs as an n-type impurity creating a highly doped n+-GaAs surface layer which is responsible for the ohmic behavior. n-channel GaAs metal-semiconductor field-effect transistors using ohmic contacts formed with the ξ and ε1–Cu3Ge phases demonstrate a higher transconductance compared to devices with AuGeNi contacts.

Dry etch damage in GaAs metal-semiconductor field-effect transistors exposed to inductively coupled plasma and electron cyclotron resonance Ar plasmas

The effects of Ar plasma exposure on transconductance, channel sheet resistance, output resistance, and gate contact ideality factor of GaAs metal-semiconductor field-effect transistors (MESFETs) were investigated using two different high-density plasma sources, namely inductively coupled plasma and electron resonance plasma. Ion-induced damage is found to be reduced at moderate source powers (∼200 W) because of the reduction in cathode dc self-bias and hence ion energy, but at higher source powers the increase in ion flux produces significant deterioration of the device performance. Careful attention must be paid to both ion flux and ion energy in order to minimize ion-induced damage. Due to their relatively low channel doping levels, MESFETs are found to be more sensitive to plasma damage than devices with very heavily doped component layers such as heterojunction bipolar transistors.

Thermal analysis of GaAs power monolithic microwave IC's mounted with epoxy attachment

The effect of chip-mounting attachment on the thermal resistance of GaAs power field effect transistor (FET) modules has been experimentally investigated. The thermal resistance was evaluated for different GaAs chip thickness of 150 and 250 /spl mu/m through an electrical method utilizing temperature dependence of Schottky-barrier in the GaAs metal semiconductor FETs (MESFETs). The thermal resistance of low-cost epoxy-mounted GaAs chips, suitable for uniplanar monolithic microwave ICs (MMICs), was found not to increase even up to a chip thickness of 250 /spl mu/m, while that of AuSn-mounted GaAs chips increased as was conventionally expected. Numerical simulation has also been presented for the similar case of GaAs power MMICs. The result of simulation suggests that lower thermal conductivity of attachment material, such as epoxy attachment, leads to larger optimum chip thickness that minimizes the total thermal resistance.

Decrease in Surface States on GaAs Metal-Semiconductor Field-Effect Transistor by High Temperature Operation

The decrease mechanism of plasma-induced surface states in a GaAs metal-semiconductor field-effect transistor (MESFET) during high temperature operation has been studied by means of high temperature operational tests, drain current transient analysis and three-terminal gate current measurements. The energy level of trapped electrons in the surface states distributes widely in the band-gap, and its activation energy does not change after decreasing the density of surface states. In order to decrease the surface states effectively, hot-carriers generated by accelerated channel electrons under high temperature operation are required.