GaAs Metal-oxide-semiconductor Field-effect Transistors Research Articles

Top-down, in-plane GaAs nanowire MOSFETs on an Al2O3 buffer with a trigate oxide from focused ion-beam milling and chemical oxidation

The top-down fabrication of an in-plane nanowire (NW) GaAs metal–oxide–semiconductor field-effect transistor (MOSFET) with a trigate oxide implemented by liquid-phase chemical-enhanced oxidation (LPCEO) is reported. A 2 μm long channel having an effective cross section ∼70 × 220 nm2 is directly fabricated into an epitaxial n+-GaAs layer. This in-plane NW structure is achieved by focused ion beam (FIB) milling and hydrolyzation oxidation resulting in electronic isolation from the substrate through a semiconductor-on-insulator structure with an n+-GaAs/Al2O3 layer stack. The channel is epitaxially connected to the μm-scale source and drain within a single layer for a planar MOSFET to avoid any issues of ohmic contact and LPCEO to the NW. To fabricate a MOSFET, the top and the two sidewalls of the in-plane NW are oxidized by LPCEO to relieve the surface damage from FIB as well as to transform these surfaces to a ∼15 nm thick gate oxide. This trigate device has threshold voltage ∼0.14 V and peak transconductance ∼35 μS μm−1 with a subthreshold swing ∼150 mV/decade and on/off ratio of drain current ∼103, comparable to the performance of bottom-up NW devices.

Variable-angle spectroscopic ellipsometry of InAlP native oxide dielectric layers for GaAs metal–oxide–semiconductor field effect transistor applications

Variable angle spectroscopic ellipsometry models and data analysis have been developed to accurately determine the thickness of indium aluminum phosphide (InAlP) native oxide films used for the gate oxide in GaAs-based metal-oxide-semiconductor field effect transistor devices. The optical constants of the InAlP oxide, as well as InAlP and indium aluminum phosphide (InGaP) lattice matched to GaAs, have been determined by ellipsometry measurements using a photon energy range of 1.45 to 5.45 eV. Using the optical constants of InAlP and InAlP oxide, an ellipsometry-based model has been developed to characterize the oxidation kinetics of a thick partially oxidized InAlP epitaxial film grown on GaAs. The data indicate a delay in the full oxidation of In relative to Al as InAlP is fully oxidized. Excellent agreement between the thickness values determined by transmission electron microscopy imaging and by ellipsometric modeling validates the optical constants obtained. The ellipsometry material parameter models have also been extended to accurately fit the thickness of <100 Å InAlP oxides grown directly upon a multi-layer heterostructure for use as a transistor gate oxide. The InAlP oxide thicknesses determined by ellipsometry agree with those determined by electron microscopy to within 4%.

Self-aligned inversion-channel In0.2Ga0.8As metal-oxide-semiconductor field-effect transistor with molecular beam epitaxy Al2O3/Ga2O3(Gd2O3) as the gate dielectric

Self-aligned inversion-channel In0.2Ga0.8As metal-oxide-semiconductor field-effect transistors (MOSFETs) with in situ molecular beam epitaxy grown Al2O3/Ga2O3(Gd2O3) (GGO) as a gate dielectric and a TiN metal gate have been fabricated on GaAs (100) substrates. A 4 μm gate-length MOSFET using a gate dielectric of Al2O3 (3 nm thick)/GGO (8 nm thick) demonstrates a maximum drain current of 9.5 μA/μm and an extrinsic transconductance of 3.9 μS/μm. The device performances are compared favorably with those of other inversion-channel GaAs MOSFETs on GaAs (100) and also of the device on GaAs (111)A substrates using atomic layer deposited Al2O3 as a gate dielectric.

GaAs metal-oxide-semiconductor devices with a complex gate oxide composed of SiO2 and GaAs oxide grown using a photoelectrochemical oxidation method

In this study, a SiO2/GaAs oxide bi-layer layer was used as the gate oxide in GaAs-based metal-oxide-semiconductor (MOS) devices. The GaAs oxide layer of the bi-layer layer was directly formed on the GaAs surface by using the photoelectrochemical (PEC) oxidation method. Some samples were thermally treated at 200 °C and 300 °C in O2 ambience for 30 min. The surface state density of the oxide/GaAs interface with and without GaAs oxide thermal treatment was 7.2 × 1011 and 7.9 × 1011 cm−2 eV−1, respectively. The GaAs MOS field effect transistors (MOSFETs) with the PEC-deposited GaAs oxide thermally treated showed an output current of 152 mA mm−1 at VDS = 2.4 V and VGS = 0 V and an extrinsic transconductance of 89 mS mm−1.

Dry etching device quality high-κ Ga xGd yO z gate oxide in SiCl 4 chemistry for low resistance ohmic contact realisation in fabricating III–V MOSFETs

This paper investigates the reactive ion etching (RIE) of Ga x Gd y O z , a device quality high-κ gate oxide for a low resistance ohmic contact realisation in fabricating III–V metal–oxide semiconductor field-effect-transistors (MOSFETs) based on high mobility channel device layer structures. The etching of Ga x Gd y O z (GGO) was performed in an Oxford Instrument PlasmaLab System 100 RIE etcher with a SiCl 4 based chemistry. The GGO high-κ gate stacks for GaAs MOSFETs were grown by Molecular Beam Epitaxy (MBE) in a dual-chamber system. Etching profile was characterised by AFM, SEM and TEM methods. The effects of usual etching conditions, such as RF power and chamber pressure on etch process were investigated. Based on the etching process, a low resistance ohmic contact has been realised as well, which has successfully been used in the fabrication of GaAs MOSFETs.

Ge Epitaxial Growth on GaAs Substrates for Application to Ge-Source/Drain GaAs MOSFETs

Ge films were epitaxially grown on GaAs(100) substrates and (100) virtual substrates using an ultrahigh vacuum/chemical vapor deposition system. The incubation time of Ge growth depends on Ga(In)As surfaces that were processed by different wet chemical solutions. Growth behaviors, such as island growth at the initial stages and selective growth into recessed regions of GaAs, were studied by transmission electron microscopy. To test the quality of Ge grown on GaAs, an diode was fabricated. We propose that through Ge selective epitaxial growth, Ge can be used as the source–drain of a GaAs metal-oxide-semiconductor field-effect transistor (MOSFET) to overcome some intrinsic limitations of this device.

Atomic-layer-deposited Al2O3/GaAs metal-oxide-semiconductor field-effect transistor on Si substrate using aspect ratio trapping technique

High quality GaAs epilayers grown by metal-organic chemical vapor deposition are demonstrated on a SiO2-patterned silicon substrate using aspect ratio trapping technique, whereby threading dislocations from lattice mismatch are largely reduced via trapping in SiO2 trenches during growth. A depletion-mode metal-oxide-semiconductor field-effect transistor (MOSFET) is demonstrated on a n-doped GaAs channel with atomic-layer deposited Al2O3 as the gate oxide. The 10 μm gate length transistor has a maximum drain current of 88 mA/mm and a transconductance of 19 mS/mm. The surface mobility estimated from the accumulation drain current has a peak value of ∼500 cm2/Vs, which is comparable with those from previously reported depletion-mode GaAs MOSFETs epitaxially grown on semi-insulating GaAs substrates.

Inversion-channel enhancement-mode GaAs MOSFETs with regrown source and drain contacts

The use of compound semiconductors as the channel material has recently drawn great attention because of its potential to solve the upcoming Si metal–oxide–semiconductor field effect transistor (MOSFET) scaling problem for device beyond 22 nm node. In this work, a method of fabricating inversion-channel enhancement-mode GaAs n-MOSFET by incorporating molecular beam epitaxy regrown source and drain regions is demonstrated. By using regrown contact layers to avoid high-temperature processes and, thus, preserve the integrity of the oxide–semiconductor interface, the structure allows the fabrication of self-aligned III–V-based MOSFET. The fabricated n-channel enhancement-mode GaAs MOSFET with a 4 μm gate length shows a record high transconductance of 75 mS/mm.

Comprehensive Study of GaAs MOSFETs Using Gadolinium Oxide and Praseodymium Oxide Layers

The high-dielectric-constant (high-) gadolinium oxide layer and praseodymium oxide layer are demonstrated as gate dielectric insulator materials in GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) using in situ high oxygen flow rate electron-beam deposition technology. The dielectric constants of the and layers developed in this study were 9.2 and 9.8, respectively. The Schottky gate turn-on voltages of GaAs MOSFETs with and insulators were 2.23 and , respectively, representing an improvement on the conventional p-type high electron mobility transistors . Moreover, the MOSFETs had a higher thermal stability and thermal linearity than the MOSFET (temperature range ) due to its high binding energy, as revealed by X-ray photoelectron spectroscopy.

Inversion-type enhancement-mode HfO2-based GaAs metal-oxide-semiconductor field effect transistors with a thin Ge layer

Using a thin germanium (Ge) interfacial passivation layer (IPL), GaAs HfO2-based inversion-type enhancement-mode metal-oxide-semiconductor field effect transistors (MOSFETs) are realized. The n-channel MOSFETs on semi-insulating GaAs substrate clearly show surface modulation and excellent current control by gate bias. The threshold voltage of ∼0.5V, the transconductance of ∼0.25mS∕mm, the subthreshold swing of ∼130mV/decade, and the drain current of ∼162μA∕mm (normalized to the gate length of 1μm) at Vd=2V and Vg=Vth+2V are obtained. In comparison with previous reports, the dc characteristics of the inversion-type GaAs MOSFETs with a Ge IPL and HfO2 dielectric demonstrate much similar results.

A low damage Si3N4 sidewall spacer process for self-aligned sub-100 nm III–V MOSFETs

This paper investigates a low damage reactive ion etch (RIE) process to make thin silicon nitride sidewall spacers for the fabrication of self-aligned sub-100nm gate length III–V metal–oxide–semiconductor field-effect-transistors (MOSFETs). Self-alignment is essential to minimize the contribution to the parasitic series source/drain resistance (RSD) from the access region between the ohmic contact and the gate, whilst retaining the overall electrostatic integrity of the device. In this work, a blanket Si3N4 was deposited by room temperature inductively coupled plasma chemical vapour deposition (ICP-CVD) and etched by reactive ion etching in a SF6/N2 based chemistry. Conditions were optimised to ensure low damage to the underlying device layer stack. This process has successfully produced thin Si3N4 spacers for fabricating self-aligned GaAs MOSFETs. The sheet resistance of III–V MOSFET materials was monitored as a function of etch parameters to assess the impact of damage related effects on the electronic characteristics of the underlying material. The etching profile and the sheet resistance of the device layer structures were characterised by using scanning electronic microscope (SEM) and sonogage, respectively.

Ga 2 O 3 ( Gd 2 O 3 ) ∕ Si 3 N 4 dual-layer gate dielectric for InGaAs enhancement mode metal-oxide-semiconductor field-effect transistor with channel inversion

A dual-layer gate dielectric approach for application in III-V metal-oxide-semiconductor field-effect transistor (MOSFET) was studied by using ultrahigh vacuum deposited 7–8nm thick Ga2O3(Gd2O3) as the initial dielectric to unpin the surface Fermi level of In0.18Ga0.82As and then molecular-atomic deposition of ∼2–3nm thick Si3N4 as a second dielectric protecting Ga2O3(Gd2O3). The total equivalent oxide thickness achieved in this study is 5nm. We have demonstrated an enhancement mode In0.18Ga0.82As∕GaAs MOSFET with surface inverted n channel with drain current (Id) of 0.1mA for a gate length of 10μm and a gate width of 880μm at Vds=1V and Vg=4.5V.

Electrical measurements of voltage stressed Al2O3/GaAs MOSFET

Abstract Electrical characteristics of GaAs metal–oxide–semiconductor field effect transistor with atomic layer deposition deposited Al 2 O 3 gate dielectric have been investigated. The IV characteristics were studied after various constant voltage stress (CVS) has been applied. A power law dependence of the gate leakage current ( I g ) on the gate voltage ( V g ) was found to fit the CVS data of the low positive V g range. The percolation model well explains the degradation of I g after a high positive V g stress. A positive threshold voltage ( V th ) shift for both +1.5 V and +2 V CVS was observed. Our data indicated that positive mobile charges may be first removed from the Al 2 O 3 layer during the initial CVS, while the trapping of electrons by existing traps in the Al 2 O 3 layer is responsible for the V th shift during the subsequent CVS.

Interfacial trap characteristics in depletion mode GaAs MOSFETs

The trap-related characteristics in depletion mode GaAs metal-oxide-semiconductor field-effect-transistors (MOSFETs) were studied using two different electrical characterization techniques of current collapse and low-frequency noise measurements. With a high-quality MBE-grown gate oxide layer Ga 2O 3(Gd 2O 3)∼30 nm thick in situ on GaAs, an extremely small drain current collapse factor Δ I max of less than 5% was observed even with a high drain bias of 16 V. In addition, no kink effect was observed in the low-frequency AC I– V characteristics. Moreover, a normalized drain noise current spectral density in the range of 10 −11–10 −9 Hz −1 (at 10 Hz) was obtained, which is comparable to modern 0.13-μm Si complementary MOS (CMOS) technology under similar biasing conditions. The results indicate low interfacial trap densities for the studied GaAs MOSFETs.

Depletion-mode GaAs-based MOSFET with Ga 2O 3(Gd 2O 3) as a gate dielectric

Two depletion-mode GaAs-based metal–oxide–semiconductor field-effect transistor (MOSFETs) were made with molecular beam epitaxy (MBE) grown Ga 2O 3(Gd 2O 3) as the gate dielectric on different channel structures. The depletion-mode GaAs MOSFETs with a gate length of 1.6 μm show an accumulated drain current density of 335 mA/mm at V G up to 4 V. The In 0.15Ga 0.85As/GaAs MOSFET, with a 4-Å-thick amorphous Si cap layer exhibits a large drain current density of 510 mA/mm at V G up to 2 V. The output characteristics measured by a curve tracer show no I– V hysteresis and drain current drift. These excellent device characteristics were resulted from a high-quality, low-trap interface between Ga 2O 3(Gd 2O 3) and the channels.

Dry etching of a device quality high-k Ga xGd yO z gate oxide in CH 4/H 2–O 2 chemistry for the fabrication of III–V MOSFETs

This paper investigates the reactive ion etching of Ga x Gd y O z , a device quality high-k gate oxide for the fabrication of III–V metal-oxide-semiconductor field-effect-transistors (MOSFETs) based on high mobility channel device layer structures. The etching of Ga x Gd y O z (GGO) was performed in an SRS System ET340 with a CH 4/H 2/O 2 based chemistry The GGO high-k gate stacks for GaAs MOSFETs were grown by molecular beam epitaxy in a dual-chamber system. Etching profile was characterised by SEM using a wet chemical HCl/HF/H 2O decoration etch to assist layer identification. The effects of etching gas, RF power, and duration of CH 4/H 2 and O 2 gas cycles on etch process were investigated.

Formation and characterization of nanometer scale metal-oxide-semiconductor structures on GaAs using low-temperature atomic layer deposition

Atomic layer deposition (ALD) grown Al2O3 has excellent bulk and interface properties on III-V compound semiconductors and is used as gate dielectric for GaAs and GaN metal-oxide-semiconductor field-effect transistors (MOSFETs). The low-temperature (LT) ALD technology enables us to fabricate 100nm MOS structures on GaAs, defined by nanoimprint lithography. The electrical characterization of these nanostructured dielectrics demonstrates that the bulk oxide films and the oxide-GaAs interfaces are of high quality even in nanometer scale. The submicron gate length GaAs MOSFET formed by LT-ALD and lift-off process shows well-behaved transistor characteristics. This GaAs MOSFET process is ready to scale the gate length below 100nm for ultra-high-speed or THz transistor applications.

GaAs MOSFET Using InAlP Native Oxide as Gate Dielectric

GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) using wet thermally oxidized InAlP as the gate insulator are reported for the first time. Leakage current measurements show that the 11-nm-thick native oxide grown from an In/sub 0.49/Al/sub 0.51/P layer lattice-matched to GaAs has good insulating properties, with a measured leakage current density of 1.39/spl times/10/sup -7/ mA//spl mu/m/sup 2/ at 1 V bias. GaAs MOSFETs with InAlP native gate oxide have been fabricated with gate lengths from 7 to 2 /spl mu/m. Devices with 2-/spl mu/m-long gates exhibit a peak extrinsic transconductance of 24.2 mS/mm, an intrinsic transconductance of 63.8 mS/mm, a threshold voltage of 0.15 V, and an off-state gate-drain breakdown voltage of 21.2 V. Numerical Poisson's equation solutions provide close agreement with the measured sheet resistance and threshold voltage.

GaAs metal–oxide–semiconductor field-effect transistor with nanometer-thin dielectric grown by atomic layer deposition

A GaAs metal–oxide–semiconductor field-effect transistor (MOSFET) with thin Al2O3 gate dielectric in nanometer (nm) range grown by atomic layer deposition is demonstrated. The nm-thin oxide layer with significant gate leakage current suppression is one of the key factors in downsizing field-effect transistors. A 1 μm gate-length depletion-mode n-channel GaAs MOSFET with an Al2O3 gate oxide thickness of 8 nm, an equivalent SiO2 thickness of ∼3 nm, shows a broad maximum transconductance of 120 mS/mm and a drain current of more than 400 mA/mm. The device shows a good linearity, low gate leakage current, and negligible hysteresis in drain current in a wide range of bias voltage.

Optimization of AuGe-Ni_Au ohmic contacts for GaAs MOSFETs

GaAs-based metal-oxide-semiconductor field-effect transistors (MOSFETs) are promising devices for high-speed and high-power applications. One important factor influencing the performance of a GaAs MOSFET is the characteristics of ohmic contacts at the drain and source terminals. In this paper, AuGe-Ni-Au metal contacts fabricated on a thin (930 /spl Aring/) and lightly doped (4/spl times/10/sup 17/ cm/sup -3/) n-type GaAs MOSFET channel layer were studied. The effects of controllable processing factors such as the AuGe thickness, the Ni/AuGe thickness ratio, alloy temperature, and alloy time to the characteristics of the ohmic contacts were analyzed. Contact qualities including specific contact resistance, contact uniformity, and surface morphology were optimized by controlling these processing factors. Using the optimized process conditions, a specific contact resistance of 5.6/spl times/10/sup -6/ /spl Omega//spl middot/cm/sup 2/ was achieved. The deviation of contact resistance and surface roughness were improved to 1.5% and 84 /spl Aring/, respectively. Using the improved ohmic contacts, high-performance GaAs MOSFETs (2 /spl mu/m/spl times/100 /spl mu/m) with a large drain current density (350 mA/mm) and a high transconductance (90 mS/mm) were fabricated.