GaAs MESFET Research Articles

Drain temperature determination in dual-gate GaAs MESFETs

This paper describes the temperature dependence of the drain current and the drain temperature in dual-gate GaAs MESFETs. The model presented, effectively couples together the effects of the operating temperature and the polarization voltages on the electron temperature and the drain current. This offers improved accuracy over existing models by considering a nonlinear field-dependent diffusivity-to-mobility ratio. Two-dimensional numerical simulation is used to describe significant physics in the characteristics for 0.5 µm gates GaAs DGMESFET.

The Effect of Electrostatic Discharge on Electrical Overstress Susceptibility in a Gallium Arsenide MESFET-Based Device

The electrostatic discharge (ESD) and electrical overstress (EOS) susceptibility of gallium arsenide (GaAs) MESFET microwave monolithic integrated circuits is investigated using a combination of threshold ESD/EOS tests, ESD step stress tests, and multiple low-level ESD stresses of constant magnitude less than the hard failure threshold voltage. The ESD stresses applied were based on standard ESD test models. Multiple low-level ESD stresses produced no stress hardening or weakening effect on the hard ESD failure threshold voltage of the device and no detectable degradation in electrical performance. However, such stresses were found to increase the device susceptibility to subsequent EOS failure, suggesting that low-level ESD stresses can latently damage GaAs MESFET-based devices. EOS susceptibility did not recover with annealing. The failure signatures suggest that the hard failure mechanisms caused by EOS following the application of low-level ESD stresses are dependent on the amplitude of the pre-ESD stress and that field failures may be caused by successive ESD and EOS stresses. The findings indicate the need for dual ESD and EOS protection in the GaAs MESFET component studied and suggest that the relationship between ESD and EOS susceptibility may need to be considered for other semiconductor technologies.

A comprehensive four parameters I– V model for GaAs MESFET output characteristics

A comparison of nine different nonlinear I– V models for the simulation of submicron GaAs MESFET dc characteristics has been made. Drain-to-source current, I ds as a function of gate-to-source, V gs and drain-to-source, V ds voltages has been simulated and then compared with experimental data. To determine the accuracy of a model, root-mean-square (RMS) errors were calculated. The lowest RMS error was observed for Ahmed model whereas it was highest for Statz model. An ideal Schottky barrier junction free from interface states has been assumed in these models and thus their applications in device simulation are limited. To simulate output characteristics of a GaAs MESFET having finite density of sates at Schottky barrier, Ahmed model has been modified. It has been demonstrated that the proposed model is a comprehensive one and can simulate the device characteristics, with significant improved accuracy, for varying Schottky barrier conditions.

TIME DOMAIN ANALYSIS OF ACTIVE TRANSMISSION LINE USING FDTD TECHNIQUE (APPLICATION TO MICROWAVE/MM- WAVE TRANSISTORS)

In this paper, an accurate modeling procedure for GaAs MESFET as active coupled transmission line is presented. This model can consider the effect of wave propagation along the device electrodes. In this modeling technique the active multiconductor transmission line (AMTL) equations are obtained, which satisfy the TEM wave propagation along the GaAs MESFET electrodes. This modeling procedure is applied to a GaAs MESFETs by solving the AMTL equations using Finite-Difference Time-Domain (FDTD) technique. The scattering parameters are computed from time domain results over a frequency range of 20-220 GHz. This model investigates the effect of wave propagation along the transistor more accurate than the slice model, especially at high frequencies.

Accurate large-signal single current source thermal model for GaAs MESFET/HEMT

An accurate approach to the simulation of the DC and pulsed IV characteristics of GaAs MESFETs over the −70 to +70°C temperature range is presented. The new approach, suitably modified, can be applied to existing DC models to increase their accuracy and range of operation.

An Improved Model for GaAs MESFETs Suitable for a Wide Bias Range

In this letter, we present a new large signal model for GaAs metal-semiconductor field effect transistors, incorporating features for enhancing the bias range for which accuracy is maintained, for use in the simulation of microwave circuits. The model parameters for a specific case were extracted from a wide range of dc I-V and S-parameter data, and the simulated behavior was observed to match the measured data closely. The model includes the possibility of showing negative slopes of the I-V curves at high power without sacrificing accuracy in predicting radio frequency behavior, while remaining simple enough for use in simulation tools

2.4 GHz Class-E power amplifier with transmission-line harmonic terminations

The design procedure, fabrication and measurement of a Class-E power amplifier with excellent second- and third-harmonic suppression levels are presented. A simplified design technique offering compact physical layout is proposed. With a 1.2 mm gate-width GaAs MESFET as a switching device, the amplifier is capable of delivering 19.2 dBm output power at 2.41 GHz, achieves peak PAE of 60% and drain efficiency of 69%, and exhibits 9 dB power gain when operated from a 3 V DC supply voltage. When compared to the classical Class-E two-harmonic termination amplifier, the Class-E amplifier employing three-harmonic terminations has more than 10% higher drain efficiency and 23 dB better third-harmonic suppression level. Experimental results are presented and good agreement with simulation is obtained. Further, to verify the practical implementation in communication systems, the Bluetooth-standard GFSK modulated signal is applied to both two- and three-harmonic amplifiers. The measured RMS FSK deviation error and RMS magnitude error were, for the three-harmonic case, 1.01 kHz and 0.122%, respectively, and, for the two-harmonic case, 1.09 kHz and 0.133%.

A new analytical model for photo-dependent capacitances of GaAs MESFET’s with emphasis on the substrate related effects

A new analytical model for optical and bias dependent nonlinear capacitances of GaAs MESFET which is valid for both linear and saturation regions has been proposed in this paper. The novelty lies in modeling of internal and external photovoltaic effects that includes deep level traps in the substrate and surface recombination at metal–semiconductor interface of the gate. The effect of high field domain formation at the drain end in the saturation region has also been included to improve the accuracy of the present model. The model presents backgating effects on gate–source and gate–drain capacitances of GaAs MESFET for the first time in literature. Finally, the proposed model has been compared to the reported results to show the validity. The proposed model may be very useful for the designing of photonic MMIC’s and optical receivers using GaAs MESFET’s.

Active inductances controlled in GaAs MESFET technology

Active inductances controlled in GaAs MESFET technology

Energy Efficiency: The Commercial Pull for SiC Devices

As SiC devices begin to become commercially available, it is becoming clear that electrical efficiency improvement is one of the key drivers for their adoption. For RF applications, SiC MESFETs have the ability to be easily linearized via digital pre-distortion to offer a 47% improvement in efficiency. In broadband WiMax applications, SiC MESFETs offer more than double the efficiency versus using GaAs MESFETs. SiC Schottky diodes are allowing up to a 25% reduction in losses in power supplies for computers and servers when used in the power factor correction circuit. For motor control, SiC Schottkys allow up to a 33% reduction in losses, as demonstrated for a 3 HP motor drive. Even higher efficiencies can be obtained when the Schottkys are combined with a SiC switch. A 400 W boost converter has been demonstrated using a SiC MOSFET and Schottky diode, operating at >200° C, with an extremely high efficiency of 98%. These improvements in electrical efficiency can have a significant impact in reducing overall electricity consumption worldwide, impacting virtually every aspect of electrical usage, ranging from information technology to motor control, with potential savings of $35 billion/yr.

Structure of neutron-induced defect clusters in GaAs MESFETs

A method is proposed for the structural investigation of defect clusters produced by neutron irradiation of semiconductors. It involves simulation of defect formation and analysis of the distribution of point defects within individual clusters. The method enables one to characterize point-defect aggregations in a cluster in terms of size, separation, and arrangement. It could be applied to advanced devices based on a nanoscale heterostructure.

A new feedback method for power amplifier with unilateralization and improved output return loss

Given a device with a conventionally optimized P/sub 1 dB/ point, this paper proposes a new theory for feedback amplifiers to optimize gain and improves S/sub 22/ (ideally resulting in S/sub 22/=0). The design procedure only requires the small-signal S-parameters and the measured load-pull data of the transistor. To verify this theory, two 800-mW 2-GHz GaAs MESFET amplifiers with and without the lossless feedback were implemented and evaluated. The feedback amplifier achieved significant improvement in linear gain (6 dB), reverse isolation (12 dB), and output return loss (5 dB) with the same output P/sub 1/dB for both types of amplifiers.

Safe Operating Area of GaAs MESFET for Nonlinear Applications

This paper provides a new approach to evaluate the transistor safe operating area for a nonlinear operation in the overdrive operating conditions. This approach has been implemented for a MESFET technology. The methodology consists in performing ON-state and OFF-state accelerated DC step stresses for bias conditions, which can be reached by V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> sweeps in the overdrive operating conditions. Hence, the results of an RF ageing test performed in nonlinear conditions have confirmed the methodology used in this paper

Analysis and experiments for high-efficiency class-F and inverse class-F power amplifiers

This paper presents analytic and experimental comparisons for high-efficiency class-F and inverse class-F amplifiers. The analytic formula of the efficiencies, output powers, dc power dissipations, and fundamental load impedances of both amplifiers are derived from the ideal current and voltage waveforms. Based on the formula, the performances are compared with a reasonable condition: fundamental output power levels of class-F and inverse class-F amplifiers are conditioned to be identical. The results show that the inverse class-F amplifier has better efficiency than that of class-F amplifiers as the on-resistance of the transistor increases. For experimental comparison, we have designed and implemented the class-F and inverse class-F amplifiers at I-GHz band using a GaAs MESFET and analyzed the measured performances. Experimental results shows 10% higher power-added efficiency of the inverse class-F amplifier than that of the class-F amplifier, which verifies the waveform analysis.

Optical modulation of the effective channel thickness in GaAs field effect transistors with a Schottky gate (MESFETs)

Using a model relating the change in drain current with modulation of the effective channel thickness upon IR illumination of GaAs field effect transistors with a Schottky gate (MESFETs), it is shown that it is possible to determine the change in channel thickness and the concentration profile for deep centers in an FET channel. Profiles are given for the distribution of deep centers in the channels of GaAs MESFETs with different noise temperatures.

A photo-dependent capacitance model of GaAs MESFET's

A new and simple analytical model for determining the photo-effects on the gate–source and gate–drain capacitances of GaAs MESFET's has been presented for both the linear and saturation regions. A new model for the photovoltage developed across the Schottky junction due to the illumination has been used to investigate the photo-dependent characteristics of the above capacitances. It has been observed that the gate–source and gate–drain capacitances are increased with the increase in the incident illumination level to the device in its linear region of operation whereas in the saturation region, the gate–source capacitance is increased but the gate–drain capacitance is observed to be decreased with the increase in the incident optical intensity level. (© 2006 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

High‐linear‐power MESFET devices using source‐degeneration inductance and input‐impedance mismatch

AbstractLinearity can be improved drastically by sacrificing power gain with the same output power. GaAs MESFET devices with via‐hole ground and with bond‐wire ground are used to investigate the effect of source‐inductive feedback and input‐impedance mismatch on the effect of linearity. At 2.4 GHz, the device without bond‐wire ground and mismatched input impedance has the highest linearity OIP3 = 50 dBm, gain = 13.5 dB gain, and P1dB = 29 dBm, while the device with via‐hole ground and matched input impedance has the lowest linearity OIP3 = 40 dBm, 18.3 dB gain, and P1dB = 29 dBm. © 2006 Wiley Periodicals, Inc. Microwave Opt Technol Lett 48: 953–954, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21530

Off‐state and on‐state breakdown of GaAs MESFET, PHEMT and Power PHEMT

We present a comparison of the breakdown loci of a MESFET, PHEMT and Power PHEMT. It is based on the study of the correlation between breakdown loci and device output characteristics. This study aims at performing a technology choice for amplifier design operating in non linear conditions with operating level close to the maximum operating conditions of the transistor. We found that the MESFET is the best candidate for circuits operating in overdrive conditions as it presents abrupt on-state breakdown voltage loci and the highest breakdown voltage. (© 2006 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Efficient numerical simulation of GaAs MESFET's based on energy model and using interpolating wavelet

A fast wavelet based non-uniform grid generation method is presented for time domain simulation of active semiconductor devices. The proposed approach solves the active part model of the semiconductor device. This approach is used to solve the non-linear equations of semiconductors on the self-adaptive grids, obtained by applying wavelet. Non-uniform mesh size is implemented and controlled by the wavelet coefficients. A fine mesh is used where the unknowns are varying rapidly and a coarser mesh where the unknowns are varying slowly. The energy model is considered for active layer of transistor and its results are compared with those of the classical drift diffusion model. Performance of this method is compared with the conventional finite difference on a uniform mesh. A reduction over 80 percent of unknowns in grid together with good accuracy in simulation is obtained using this non-uniform mesh while accurate physical behaviour of the device can be predicted. This represents an ongoing effort toward a numerical technique that uses wavelet to solve physical modelling problem of semiconductor devices. Copyright © 2006 John Wiley & Sons, Ltd.

High performance GaAs MESFETs with molecular implanted and optimized lowly-doped drain structure for maximized speed, gain and breakdown performance

GaAs MESFETs with novel lowly-doped drain structures have been developed utilizing molecular implants of silicon trifluoride. Short-channel effects in the 1/4 μm enhancement- and depletion-mode transistors have been suppressed with drain-induced barrier height lowering of less than 70 mV/V and pinch-off voltage shifts of less than 220 mV as the gate length was scaled from 1.0 to 1/4 μm. The 3-terminal breakdown, the transconductance to output conductance ratio, and the unity current gain, cut-off frequency were simultaneously optimized. The E-mode device possessed breakdown of >10 V, G m · R ds > 9.5, F t > 55 GHz, and nominal on-resistance of 2.1 Ω mm while the D-mode device had breakdown >10 V, G m · R ds > 6.0, F t > 45 GHz, and nominal on-resistance of 1.9 Ω mm. These optimized transistors enabled the realization of a variety of low-power digital and high-power mixed signal circuits, using 3-level source-coupled transistor and common-mode logic, such as laser and electro-optic drivers, highly integrated transceivers, multiplexers, demultiplexers, and clock data recover circuits.