GaAs Logic Circuit Research Articles

Novel GaAs enhancement-mode/depletion-mode pHEMTs technology using high-k praseodymium oxide interlayer

In this study, a novel metal–semiconductor gate enhancement-mode (E-mode) and a metal–insulator-metal–semiconductor (MIMS) gate depletion-mode (D-mode) AlGaAs/InGaAs pseudomorphic high electron mobility transistor (pHEMT) on a single GaAs substrate have been developed by using high dielectric constant praseodymium insulator layer. The epitaxial layers were design for an enhancement-mode pHEMT after gate recess process. To achieve E/D-mode pHEMTs on single GaAs wafer, traditional Pt/Ti/Au metals were deposited as Schottky contact for E-mode pHEMTs and Pr/Pr 2O 3/Ti/Au were deposited as MIMS-gate for D-mode pHEMTs. This AlGaAs/InGaAs E-mode pHEMTs exhibit a gate turn-on voltage ( V ON) of +1 V and a gate-to-drain breakdown voltage of −5.6 V, and these values were +7 V and −34 V for MIMS-gate D-mode pHEMTs, respectively. Therefore, this high-k insulator in D-mode pHEMT is beneficial for suppressing the gate leakage current. Comparing to previous E/D-mode pHEMT technology, this E-mode pHEMTs and MIMS-gate D-mode pHEMTs exhibit a highly potential for high uniformity GaAs logic circuit applications due to its single recess process.

Dependence of the SEU window of vulnerability of a logic circuit on magnitude of deposited charge

A pulsed picosecond laser was used to measure the time during which gates in a GaAs logic circuit were sensitive to single event upset (SEU). Circuit analysis showed that those gates would be most sensitive if the laser light arrived just prior to the clock signal going from low to high voltage. By delaying the clock signal with respect to the arrival time of the laser pulse, it was possible to measure a window of vulnerability, which is the time interval prior to the arrival of the clock signal during which the gate is sensitive to upsets. The width of that window was found to depend on the energy of the light pulse. Similar behavior is expected when the circuit is exposed to ions. These results suggest that, at high frequencies and in the presence of ions and with large LETs (linear energy transfers) gates in logic circuits may be sensitive to upsets during a large fraction of their duty cycle. The technique described provides an in situ way of measuring charge collection times at individual transistors and signal propagation times between logic gates using the circuit itself as the detector. >

Laser confirmation of SEU experiments in GaAs MESFET combinational logic (for space application)

Majority vote and self-scrubbing circuitry were utilized to harden the registers of a GaAs logic circuit to single event upsets (SEUs). Ion beam testing of the hardened part at low scrub frequencies showed fewer system upsets than that of an unhardened part. At high frequencies, the upset rate increased with frequency, indicating a clock-dependent SEU sensitive node. A pulsed laser was used to identify an input node in the self-scrubbing circuitry as being the source of the upsets at high frequencies. Because the node was only sensitive for a short duration prior to the rising clock edge, more clock-edge-dependent SEUs could occur at higher frequencies. The relative SEU thresholds of the registers and the input node measured with the laser showed excellent agreement with ion data. All single-point SEU failure nodes were identified and their upset thresholds measured. With this information it was possible to redesign the circuit to reduce its sensitivity to SEU at high scrub frequencies.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Modeling of multiconductor buses and analysis of crosstalk, propagation delay and pulse distortion in high speed GaAs logic circuits

Crosstalk, propagation delay, pulse distortion in multiconductor buses for high-speed GaAs logic circuits are analyzed. A simple but accurate quasi-TEM model of the bus is developed, and a critical analysis is carried out both on the accuracy of different approximate lumped and distributed models and on the impact of such approximations on the time-domain response. Results on the behavior of multiconductor buses in the presence of realistic input waveforms, are presented and design criteria are obtained. >

Simulation of load‐current‐controlled gaas logic circuits

AbstractSince the mobility of the hole is low in GaAs, P‐channel MESFET is of low speed. This makes it difficult to utilize the feature of the complementary logic circuit. Consequently, a direct‐coupled logic circuit is usually constructed using N‐channel MESFET. On the other hand, using the load‐current‐controlled logic circuit proposed in this paper, the speed and the power consumption can be improved compared with the directcoupled logic circuit. In other words, by limiting the load current according to the input state, the current counteracting the transition of the logic state can be decreased drastically. This speeds up the logic transition, thereby increasing the logic swing and reducing the power consumption.In this paper, the whole‐region model of the field‐effect transistor is introduced, and the logic swing of the GaAs ring‐oscillator is determined using Poincaré's mapping. Then the transient response of the load‐current‐controlled logic circuit is determined by simulation, leading to high speed and low power consumption.

Coupling effects in the time domain for an interconnecting bus in high-speed GaAs logic circuits

In the present paper, we evaluate the behavior of an eight-line bus in GaAs technology for high-velocity logic signals with a 10-ps rise (or fall) time. We highlight the great importance of coupling effects in the time domain on the distortion of the signals. Two possible solutions are studied to reduce these phenomena and to improve the transmission of the signals on lines. These solutions are to earth some lines between active lines or to add a second ground plane over the lines.

The effects of plasma and ion beam processing on the properties of n-GaAs Schottky diodes

Plasma and ion beam processing are being used increasingly in the fabrication of GaAs Logic circuits, for which the basic components are MESFETS and Schottky diodes. In this work GaAs surfaces have been subjected to typical dry processes and Schottky diodes subsequently fabricated to assess the extent of damage introduced. Measurements of the current-voltage and capacitance voltage characteristics, together with deep level transient spectroscopy (DLTS), indicate that ion milling and plasma etching both cause substantial damage within 10 nm of the metal-semiconductor interface in addition to less severe damage extending further into the semiconductor. The damage can be reduced by annealing at moderate temperatures. Ion beam sputter and plasma enhanced deposition produce less damage since particles with lower incident energies are involved and the surface becomes protected by the growing film.

Electron-beam fabricated high-speed digital GaAs integrated circuits

The fabrication and performance of high-speed GaAs logic circuits incorporating submicrometer gate length FET's fabricated by electron-beam lithography are discussed. The process technology required for realizing 0.5-µm gate length devices is detailed. High-speed results including a 10-GHz logic gate, 34-ps gate delay for a ring oscillator, and a 4-GHz flip-flop are described.

The prospects for ultrahigh-speed VLSI GaAs digital logic

Recent advances of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance GaAs digital ICs with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. The authors evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. GaAs IC fabrication and logic circuit approaches is reviewed. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits.

The prospects for ultrahigh-speed VLSI GaAs digital logic

Recent advances in the state of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance ( \tau_{d} \sim 100 ps) GaAs digital IC's with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. It is the purpose of this paper to evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. The paper includes a performance comparison analysis of Si and GaAs FET's and switching circuits which indicates that, for equivalent speed-power product operation, GaAs IC's should be about six times faster than Si IC's. The state of the art in GaAs IC fabrication and logic circuit approaches is reviewed, with particular emphasis on those approaches which are LSI/VLSI compatible in power and density. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits (which have demonstrated equivalent gate delays as low as \tau_{d} = 110 ps).

MA-4 the prospects for ultra-high speed VLSI GaAs digital logic

Recent advances in the state of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance ( \tau_{d} \sim 100 ps) GaAs digital IC's with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. It is the purpose of this paper to evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. The paper includes a performance comparison analysis of Si and GaAs FET's and switching circuits which indicates that, for equivalent speed-power product operation, GaAs IC's should be about six times faster than Si IC's. The state of the art in GaAs IC fabrication and logic circuit approaches is reviewed, with particular emphasis on those approaches which are LSI/VLSI compatible in power and density. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits (which have demonstrated equivalent gate delays as low as \tau_{d} = 110 ps).