GaAs FET Model Research Articles

Six-parameter DC GaAs FET modelfor nonlinear circuit simulation

By emphasising the aspects of simplicity and accuracy for GaAs FET modelling, a six-parameter DC GaAs FET model is developed. Good agreement between simulated and measured data is obtained.

A new approach for the extraction of an FET equivalent circuit from measured S parameters

A new method for the extraction of the 13-element GaAs FET model from hot S parameters is presented. The method reduces the uniqueness problem that exists between the parasitic gate resistance Rg and the channel resistance Ri. Thirteen error functions are used, with the order of optimization determined through a principle-components sensitivity analysis. © 1996 John Wiley & Sons, Inc.

An enhanced simulated annealing algorithm for extracting electronic component model parameters

An Enhanced Simulated Annealing Algorithm, adapted to continuous variables problems, has been previously elaborated. Variables discretization has received special attention and several complementary stopping criteria have been developed and implemented to reduce the computational cost. This method, coupled with an ‘open” circuit simulator — SPICE PAC — has been used for minimizing objective functions which describe circuit performance optimization problems or component model fitting to experimental data. In the same way synaptic coefficients of analogue multilayer neural networks have also been determined. In the paper, various parameters of a non-linear general purpose GaAs FET model are directly determined by our Enhanced Simulated Annealing. We minimize an objective function of several continuous variables — model parameters — based on the relative and absolute least squares errors between a measured drain current/voltage characteristics data set and computed model responses. The model is described by fairly simple explicit expressions and, hence, can be easily implemented in programs of computer-aided analysis and design of circuits with GaAs FETs. Our optimization procedure, which does not require heavy and inaccurate derivatives computations, reaches, in a reasonable time, a good accuracy for representing complex GaAs MESFET transistor behaviour.

Evaluating nonlinear models for microwave GaAs FETs

It is pointed out that although quite a number of nonlinear descriptions are available for modeling microwave GaAs MESFETs (GaAs FETs), their accuracy is much debated. Like their silicon bipolar counterparts, the GaAs FET models are based on experimental curve tracer measurements and a limited set of scattering parameters (S-parameters) measured at convenient bias points. Hence, it is impossible to be confident of their validity under conditions for which they have not been tested. This situation is complicated by a trend toward proprietary models, developed by software companies who are unwilling to share the details of their work with customers for fear of giving secrets away to potential competitors. Most of the GaAs FET models available today as part of a commercial design packages are characterized by a hyperbolic tangent or polynomial fit to the device current-voltage (I-V) curve, which is determined by actual measurement, not by studying the underlying physics. Thus, the different mathematical manipulations employed by the various developers yield significantly different results when applied to a nonlinear circuit analysis.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

GaAs FET device and circuit simulation in SPICE

We have developed a GaAs FET model suitable for SPICE Circuit simulations. The dc equations are accurate to about 1 percent of the maximum drain current. A simple but accurate interpolation formula for drain current as a function of gate-to-source voltage connects the square-law behavior just above pinchoff and the square-root law for larger values of the drain current. The ac equations, with charge-storage elements, describe the variation of the gate-to-source and gate-to-drain capacitances as the drain-to-source voltage approaches zero and when this voltage becomes negative. Under normal operating conditions the gate-to-source capacitance is much larger than the gate-to-drain capacitance. At zero drain-to-source voltage both capacitances are about equal. For negative drain-to-source voltages the original source acts like a drain and vice versa. Consequently the normally large gate-to-source capacitance becomes small and acts like a gate-to-drain capacitance. In order to model these effect it is necessary to realize that, contrary to conventional SPICE usage, there are no separate gate-to-source and gate-to-drain charges, but that there is only one gate Charge which is a function of gate-to-source and gate-to-drain voltages. The present treatment Of these capacitances permits simulations-in which the drain-to-source voltage reverses polarity, as occurs in pass-gate circuits.

A Nonlinear GaAs FET Model for Use in the Design of Output Circuits for Power Amplifiers

A nonlinear equivalent circuit model for the GaAs FET has been developed based upon the small-signal device model and separate current measurements, including drain-gate avalanche current data. The harmonic-balance technique is used to develop the FET RF load-pull characteristics in an amplifier configuration under large-signal operation. Computed and experimental load-pull results show good agreement.

Self-Consistent GaAs FET Models for Amplifier Design and Device Diagnostics

A procedure has been developed for producing accurate and unique small-signal equivalent circuit models for carrier-mounted GaAs FET's. The procedure utilizes zero drain-source bias S parmeter tests to determine accurate values of carrier parasitics, and dc measurements to evaluate the FET's gate, source, and drain resistances. Subsequent S-parameter measurements at full bias are then used to resolve the FET into an equivalent circuit model that has only 8 unknown elements out of a possible 16. A technique for evaluating the frequency range of accurate data is presented and the FET model shown is useful well above the maximum frequency of measurement. Examples of device diagnostics are presented for RCA flip-chip mounted GaAs FET's.

A GaAs FET Model for Large-Signal Applications

The use of GaAs FET's under large-signal conditions requires a knowledge of the nonlinear behavior of these devices. A computer program, based on a circuit model with nonlinear elements, has been developed which provides this information. Results from the computer model and examples of its use in microwave circuit design are given.

GaAs FET large-signal model and its application to circuit designs

A large-signal GaAs FET model is derived based on dc characteristics of the device. Analytical expressions of modeled nonlinear elements are presented in a form convenient for circuit design. Power saturation and gain characteristics of a GaAs FET are studied theoretically and experimentally. An oscillator design employing the large-signal model is demonstrated.

A Parameters Extraction Method For GaAsFET Model Based On An EnhancedSimulated Annealing Algorithm

An Enhanced Simulated Annealing, adapted to continuous variables problems, has been previously elaborated. Variables discretization has received special attention and several complementary stopping criteria have been developed and implemented to reduce the computational costs. This method, coupled with an open circuit simulator _SPICE-PAC_ has been used for minimizing objective functions which describe circuit performance optimization problems or component model fitting to experimental data. In the same way synaptic coefficients of analogue multilayer neural networks have been also determined. In the paper, various parameters of a non linear general purpose GaAs FET model are directly determined by our Enhanced Simulated Annealing. This technique minimizes an objective function of several continuous variables _model parameters_ based on the relative and absolute least squares errors between a measured drain current/voltage characteristics data set and computed model responses. The model is described by fairly simple explicit expression and, hence, can be easily implemented in programs of computer aided analysis and design of circuits with GaAs FETs. Our optimization procedure, which does not require heavy and inaccurate derivatives computations, reaches, in a reasonable time, a good accuracy for representing complex GaAs MESFET transistor behaviour. Transactions on Engineering Sciences vol 3, © 1993 WIT Press, www.witpress.com, ISSN 1743-3533 256 Software Applications in Electrical Engineering