Carbon nanotubes are exceptional semiconductors that offer larger current densities and faster switching than conventional Si and GaAs devices, making nanotubes promising for meeting the performance and energy efficiency needs of next-generation electronics. However, the successful commercialization of carbon nanotubes necessitates the control over semiconducting purity, alignment, packing density, and scalability. The simultaneous control of these characteristics has been a major challenge preventing the integration of nanotubes in industrial electronics and the full exploitation of their electronic properties. This talk will present an overview of recent technological developments and methods that progress towards these goals.In these methods, semiconducting (purity of >99.99%) carbon nanotubes are deposited on target substrates via scalable alignment methods at room temperatures. These individual methods separately enable the deposition of quasi-aligned (±28°) nanotube arrays (~50 nanotubes µm-1) demonstrated across 100 mm substrates, highly-aligned (±6°) nanotube arrays (~100 nanotubes µm-1) demonstrated across 100 mm substrates, and the selective-area deposition of highly-aligned nanotube (±7°) arrays (~up to 250 nanotubes µm-1). The nanotube arrays with high packing density (~250 nanotubes μm-1) yield exceptional current densities of 2 mA μm-1 and transconductances of 1 mS μm-1 at VD of -0.6V. Importantly, due to the low-temperature nature of the deposition processes, these techniques offer a direct path towards the alignment of carbon nanotubes directly on Si and other materials, such as GaN or plastics, to enable high-performance 3D integrated circuits.