Impact of Channel Thickness on the Performance of GaAs and GaSb DG-JLMOSFETs: An Atomistic Tight Binding Based Evaluation

Muhammad Shaffatul Islam,Ibrahim M Mehedi,Md Rafiqul Islam,Md Soyaeb Hasan,Ahmed Iskanderani,Md Tanvir Hasan

doi:10.1109/access.2021.3106141

Muhammad Shaffatul Islam, Ibrahim M Mehedi + Show 4 more

Open Access

https://doi.org/10.1109/access.2021.3106141

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Abstract

In this paper, the performance of GaAs and GaSb based sub-10 nm double-gate junctionless metal-oxide-semiconductor field-effect transistors (DG-JLMOSFETs) have been studied for high-performance switching applications. The quantum transmitting boundary method (QTBM) has been considered for electron transport, and the band structures are accounted for sp3d5s* tight-binding modeling. The channel thickness, t ch is varied from 1.7 to 4.7 nm to evaluate the device figure of merits (FOMs). The thinner channel’s device shows a lower OFF-state current, while the ticker channel device allows a higher ON-state current. The threshold voltage is approximately 0.4 V for GaAs DG-JLMOSFETs with t ch = 1.7 nm, whereas it reduces to ~0.05 V for that of t ch = 4.7 nm. Similar characteristics have been shown in GaSb devices. Besides, a significant impact of t ch on the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) is found in GaSb DG-JLMOSFETs compared with those of GaAs devices. The devices show a higher leakage-power dissipation in both channel materials and low-intrinsic delay for thicker t ch due to a substantial amount of energy drop. The above results indicate that III-V-based DG-JLMOSFETs are very promising for next-generation high-performance switching technology.

Highlights

The roadmap of enhancing transistor density through miniaturization initiates several drawbacks in conventional MOSFETs such as Short Channel Effects (SCE’s), Drain Induced Barrier Lowering (DIBL), Hot Carrier Effects (HCEs), Channel Length Modulation (CLM), etc [1], [2]
This characteristic is due to the higher source-to-channel barrier height, which might be attributed to the one-dimensional quantum confinement effect (QCE) that becomes pronounced at thinner tch [35]
More QCE is observed in GaSb based DG-JLMOSFETs at OFF-state in compare with GaAs

Summary

Introduction

The roadmap of enhancing transistor density through miniaturization initiates several drawbacks in conventional MOSFETs such as Short Channel Effects (SCE’s), Drain Induced Barrier Lowering (DIBL), Hot Carrier Effects (HCEs), Channel Length Modulation (CLM), etc [1], [2]. The successful fabrication of junctionless transistor (JLT) in 2010 has mitigated the significant drawbacks of existing MOSFETs [3]. The junctionless MOSFETs (JLMOSFETs) have overcome the challenges that originate from the. Requirement of too high gradients in doping concentration in present transistors, mainly designing for sub-10 nm gate length [4]. The JLMOSFETs have received significant attention for their technological feasibility and theoretical modeling. The DG-JLMOSFETs are becoming more promising due to their superior performances in high speed and low power applications [19].

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