The Semiconductor Laboratory of the Max Planck Society is designing and producing cutting edge radiation and particle sensors for experiments in basic science conducted by institutes of the German Max Planck Society and other international partners. One of the most challenging projects is the construction of so-called vertex detectors for experiments at high energy particle colliders like KEKB in Japan and the future International Linear Collider (ILC) as the next big international high energy physics project after the LHC at CERN, Geneva, Switzerland. Modern vertex detectors are pixelated position sensitive particle sensors based on highly specialized silicon technology similar to CMOS or CCD sensors for commercial optical applications. The goal is to measure the track of a secondary particle and extrapolate to the point of its origin. One of the main challenges for up-to-date vertex detectors is the requirement of low mass to minimize the effect of scattering of the traversing particle in the sensor material itself and the sensor support structures. We are developing ultra-low-mass sensors based on the DEPFET (DEpleted P-channel FET) pixel technology. DEPFETs are MOS transistors made on fully depleted detector grade silicon and combine the sensing and first signal amplification element in the same device. The thickness of the sensor is minimized and optimized for the best vertexing performance of the detector arrangement as whole. The detector is a cylindrical arrangement of sensor modules around the primary beam interaction point. The sensor module is a silicon based multi-chip module with the module substrate being the sensor wafer itself. There are three functional regions on the MCM: the 50 μm thin sensitive active pixel area with the DEPFETs in a two metal and two poly-silicon layer technology, the ‘end of stave’ with three metal layers (two Al and one Cu) where the read-out electronic is placed and the narrow frame in the same interconnect technology with the steering ASICs. Three types of ASICs are used: a mixed-signal ASICs as the analogue front-end and ADC, a digital data handling chip and a steering chip in HV-MOS technology for the row-wise addressing and clearing of the pixel matrix. There are 12 chips in total on the module, all bump-bonded to the substrate, about 3000 area array bumps in total. The finished module has 250 kPixels and is read out at a frame rate of 50 kHz via a wire-bonded flex cable. Our paper will describe the technology for the production of ultra-thin DEPFET sensors and the monolithically integrated support, testing challenges during production and their solutions as well as electrical, thermal, and mechanical properties of the assembled MCMs. An outlook will be given on how micro-channels for active cooling will be integrated in the current MCM concept.