Future Hardware Implementation Research Articles

Fast, bias-free algorithm for tracking single particles with variable size and shape

We introduce a fast and robust technique for single-particle tracking with nanometer accuracy. We extract the center-of-mass of the image of a single particle with a simple, iterative algorithm that efficiently suppresses background-induced bias in a simplistic centroid estimator. Unlike many commonly used algorithms, our position estimator requires no prior information about the shape or size of the tracked particle image and uses only simple arithmetic operations, making it appropriate for future hardware implementation and real-time feedback applications. We demonstrate it both numerically and experimentally, using an inexpensive CCD camera to localize 190 nm fluorescent microspheres to better than 5 nm.

Combined Statistical and Multiscale View on Ultrasonic Liver Images for Characterization

Combined Statistical and Multiscale View on Ultrasonic Liver Images for Characterization

Optimised PWL recursive approximation and its application to neuro-fuzzy systems

In this work, a piecewise-linear (PWL) function approximation is described by a lattice algebra. The maximum (∨) and minimum (∧) lattice operators have been modified to incorporate interpolation capability of generated PWL function vertexes. As a result of that, a new recursive method called centred recursive interpolation (CRI) based on such operators is proposed and analysed for successive function smoothing and more accurate approximation. The resultant computational scheme is accurate but simple, as few parameters are needed for function definition. The method is tested by applying it to the optimum approximation of some sample functions, and it turns out to be a natural quadratic approximation. Due to its advantageous characteristics and the properties that Gaussian-like function based neuro-fuzzy systems show, optimised approximation of programmable Gaussian functions has been studied in detail. A table of optimum parameters has been obtained for approximating the function through different design schemes. This constitutes a previous theoretical work for the future hardware implementation of function generators in neuro-fuzzy systems.

Application of an artificial neural network to land-cover classification of thematic mapper imagery

This paper explores the applicability of an artificial neural network (ANN) approach to land-cover classification of Thematic Mapper imagery. The ANN is presented training site examples to “learn” the association between these sites and the desired land-cover classes. The classification produced by the neural network is comparable to a conventional supervised classification using the same training sites. The ANN used in this research is a software simulation developed at the Jet Propulsion Laboratory. The motivations for the research are to substantiate the efficacy of a neural network for satellite image processing and to determine design parameters for future hardware implementation.

A dynamic-time-warp integrated circuit for a 1000-word speech recognition system

The design of a custom MOS-LSI chip capable of performing the pattern matching portion of a 1000-word speech recognition algorithm in real time is reported. The chip implements a dynamic-time-warp algorithm. The chip is part of a single-board speech recognition system that performs spectral analysis, dictionary storage and management, and speech recognition for both isolated and connected word applications of up to 1000 words. Speech recognition algorithms are normally refined to work well on general-purpose machines without the influence of future special-purpose hardware implementation. With general-purpose machines, chip implementation issues such as bit widths and parallelism cannot be utilized so they are ignored in favor of increasing algorithmic complexity by techniques such as pruning. If developed together, the chip architecture and algorithm can be refined to fully use parallelism and increasing throughput, while retaining efficient silicon area utilization. The resulting special-purpose architecture is sufficiently general that connected speech can be recognized without a speed penalty.

Computer trees: a concept for parallel processing

This paper describes the multimicrocomputer concept called ‘computer tree’ which is currently being investigated at the institute. The first part summarizes the global idea and characteristic features of the concept and complexity considerations concerning the main application of computer trees: parallel execution of recursive algorithms. The paper then goes on to describe a simple hardware implementation of the concept, which has been undertaken in a first stage of the project, and a proposal for a future hardware implementation that goes beyond the capabilities of the first in that a flexible connection of processor modules and, thereby, an adaptation of the hardware structure to the structure of the algorithm during execution time is provided.