Fundamental Frequency Switching Research Articles

Less switch cascaded H-bridge multilevel inverter based on SHE technique

In this article, a less switch cascaded H-bridge multilevel inverter has been proposed using reduced number of switches. A standard cascaded multilevel inverter requires 4h number of switches for (2h + 1) levels, whereas h is the number of dc sources. This proposed scheme allows reduced number of switches for the same level. Less switch cascaded H-bridge multilevel inverter-fed induction motor shows the better performance due to fundamental frequency switching scheme using Selective Harmonic Elimination technique. High-quality output is derived due to the absence of lower order harmonics. High conversion efficiency is also achieved for induction motor drive when it is operated with the proposed method. When the levels are increased, the number of switches used is very less compared to the conventional cascaded H-bridge multilevel inverter. The performance of three-phase less switch cascaded H-bridge multilevel inverter with equal dc sources is simulated using MATLAB platform. Harmonic analysis is done on the proposed cascaded H-bridge multilevel inverter with various levels.

Application of memetic algorithm for selective harmonic elimination in multi‐level inverters

Multi-level inverter (MLI) is a promising technology, able to generate high-quality power with lower switching frequency. Therefore it leads to high conversion efficiency and low switching losses. Selective harmonic elimination is a fundamental frequency switching strategy that theoretically provides desirable output waveform for MLIs by elimination of low order harmonics. Unfortunately, complexity, non-linearity and solvability features attached to this method have limited its industrial application. In this study, a particle swarm optimisation (PSO)-based memetic algorithm (MA) guided by mesh adaptive direct search is introduced as a suitable choice for the harmonic optimisation problem. This algorithm is precise and applicable to any MLI. The results show that MA converges to the exact solution for feasible modulation index. When the problem has no exact solution, the algorithm finds a relatively proper solution to regulate the fundamental component of the voltage. Furthermore, the comparison between MA and other methods shows that the probability of convergence of MA is higher than others. For 48% of the analysed data MA reaches to a fitness value lower than 10 -30 whereas this probability is 5% for PSO and almost zero for genetic algorithm and bee algorithm. The proposed method has been implemented on a cascade seven-level inverter.

Reduced sensor configuration of a power factor correction based single‐ended primary inductance converter fed brushless DC motor drive

This study presents a power factor correction-based single-ended primary inductance converter (PFC-SEPIC) feeding brushless DC (BLDC) motor drive for low-power household appliances. In a conventional scheme of BLDC motor, the speed is varied by controlling the duty ratio of high-frequency pulse width modulation signals, which increase the switching losses in the voltage source inverter (VSI) feeding BLDC motor. However, this study presents a BLDC motor of which the speed is controlled by adjusting the DC bus voltage of the VSI feeding BLDC motor. Moreover, a fundamental switching frequency of VSI is employed for reduction of its switching losses by operating the BLDC motor in electronic commutation. A PFC-based SEPIC is designed for its operation in discontinuous inductor current mode such that the voltage control is achieved using a single voltage sensor with inherent PFC at AC mains; which also makes it a cost effective solution for low power applications. The proposed drive is implemented on the developed converter for the performance evaluation. This drive shows high efficiency as compared with conventional schemes of BLDC motor drive with satisfactory power quality performance at various speeds satisfying IEC 61000-3-2 standard.

A Unity Power Factor Bridgeless Isolated Cuk Converter-Fed Brushless DC Motor Drive

This paper presents a power factor correction (PFC)-based bridgeless isolated Cuk converter-fed brushless dc (BLDC) motor drive. A variable dc link voltage of the voltage source inverter (VSI) feeding the BLDC motor is used for its speed control. This allows the operation of VSI in fundamental frequency switching to achieve an electronic commutation of the BLDC motor for reduced switching losses. A bridgeless configuration of an isolated Cuk converter is derived for the elimination of the front-end diode bridge rectifier to reduce conduction losses in it. The proposed PFC-based bridgeless isolated Cuk converter is designed to operate in discontinuous inductor current mode to achieve an inherent PFC at the ac mains. The proposed drive is controlled using a single voltage sensor to develop a cost-effective solution. The proposed drive is implemented to achieve a unity power factor at the ac mains for a wide range of speed control and supply voltages. An improved power quality is achieved at ac mains with power quality indices within the limits of the IEC 61000-3-2 standard.

Embedded Control of n-Level DC–DC–AC Inverter

A generalized multilevel inverter (MLI) with frontend dc-dc conversion stage followed by a synchronized H-bridge is presented. By using this configuration along with the proposed embedded control, any desired number of levels (n) in the output voltage can be produced. The dc-dc conversion stage employs an asynchronous buck converter. The duty cycle of dc-dc converter is varied in the form of m-level piecewise constant (PWC) unidirectional sine wave to produce a similar output voltage across the dc-link capacitor. The unidirectional PWC voltage is made into n-level ac voltage, where n = (2m - 1), by the synchronized H-bridge. Hence, it is named as dc-dc-ac MLI. An 8-bit Xilinx SPARTAN 3AN field programmable gate array (FPGA)-based digital controller is utilized for the simultaneous generation of high-frequency switching pulses for dc-dc converter and synchronized fundamental frequency switching pulses for H-bridge. The desired number of levels in ac output voltage and its frequency are the essential inputs to the pulse generation algorithm implemented in FPGA. The proposed MLI is simulated in MATLAB/Simulink environment; its functioning is verified with resistive (R) and resistive-inductive (R-L) loads. The hardware prototype of MLI is built in the laboratory and its performance is validated with R, R-L loads, and few home appliances.

Grid-connected Switched Reluctance Generator based Wind Farm Control using Modified Hybrid Multicell Converter

This study deals with analysis of grid integrated Switched Reluctance Generator (SRG) based wind farm control using Modified Hybrid Multicell Converter (MHMC). A Finite Element Analysis (FEA) model is developed for the existing machine geometry using MagNet 7.1.1 and solved to obtain the parameters like flux linkage, inductance and torque. The data obtained from FEA Model is utilized to develop model of SRG in the MATLAB/SIMULINK environment. Asymmetric Half Bridge Converter (AHBC) with dedicative buses for source and load is used for excitation. Developed wind turbine with Maximum Power Point Tracking (MPPT) algorithm to extract maximum power from the wind turbine. Output of the SRG is integrated with grid through Modified Hybrid Multicell Converter. The MHMC uses a flying capacitor module on each cell to generate a positive variable dc-link voltage. The variable dc link is inverted at fundamental switching frequency by an H-bridge to generate the cell output voltage. Phase-Disposition level-shifted Pulse Width Modulation (PD-PWM) Technique is used to obtain the high performance waveforms. In this study wind farm having four SRG’S controlled through MHMC is proposed.

Modulation and Closed-Loop-Based DC Capacitor Voltage Control for MMC With Fundamental Switching Frequency

This paper presents a novel modulation and capacitor voltage control method for the modular multilevel converter (MMC) allowing the fixed switching frequency of 50 Hz. In the proposed modulation method, the switching angles are calculated through a new approach with reference to the nearest voltage level control. And then, every four pulse patterns are grouped together for averaging the dc and fundamental ac components in the output voltage of individual submodules. Accordingly, the absorbed power of each submodule could be self-balanced during few line periods simply by periodically swapping the pulse patterns. Moreover, the different power losses or different initial energy states of the submodules may also cause the dc capacitor voltage deviation although the absorbed power is equally distributed. Therefore, a closed-loop-based method of exchanging the leading or falling edges of pulse patterns is developed for dc capacitor voltage control. Simulation results show that the MMC circuit together with the proposed method functions very well in both rectifier and inverter modes. Experimental results on a single-phase MMC-based inverter with four submodules in one arm show the validity of the proposed method.

A BL-CSC Converter-Fed BLDC Motor Drive With Power Factor Correction

This paper presents a power factor correction (PFC)-based bridgeless canonical switching cell (BL-CSC) converter-fed brushless dc (BLDC) motor drive. The proposed BL-CSC converter operating in a discontinuous inductor current mode is used to achieve a unity power factor at the ac mains using a single voltage sensor. The speed of the BLDC motor is controlled by varying the dc bus voltage of the voltage source inverter (VSI) feeding the BLDC motor via a PFC converter. Therefore, the BLDC motor is electronically commutated such that the VSI operates in fundamental frequency switching for reduced switching losses. Moreover, the bridgeless configuration of the CSC converter offers low conduction losses due to partial elimination of diode bridge rectifier at the front end. The proposed configuration shows a considerable increase in efficiency as compared with the conventional scheme. The performance of the proposed drive is validated through experimental results obtained on a developed prototype. Improved power quality is achieved at the ac mains for a wide range of control speeds and supply voltages. The obtained power quality indices are within the acceptable limits of IEC 61000-3-2.

Three-Level 48-Pulse STATCOM with Pulse Width Modulation

In this paper, a new control strategy of a three-level 48-pulse static synchronous compensator (STATCOM) is proposed with a constant dc link voltage and pulse width modulation at fundamental frequency switching. The proposed STATCOM is realized using eight units of three-level voltage source converters (VSCs) to form a three-level 48-pulse STATCOM. The conduction angle of each three-level VSC is modulated to control the ac converter output voltage, which controls the reactive power of the STATCOM. A fuzzy logic controller is used to control the STATCOM. The dynamic performance of the STATCOM is studied for the control of the reference reactive power, the reference terminal voltage and under the switching of inductive and capacitive loads.

Simplified embedded control scheme for two‐stage multistring off‐grid inverter

This study proposes an embedded control for an off-grid single-phase multistring inverter with front-end DC–DC conversion stage followed by a synchronised H-bridge. In this inverter, the duty cycle of DC–DC converter is varied in the form of fully rectified sinusoidal fashion to produce a similar output voltage across the DC-link capacitor. This unidirectional voltage is converted into an AC voltage by the synchronised H-bridge. An application of this inverter topology with the proposed control scheme in micro-grid is investigated in the present study. The proposed control scheme not only possesses better steady-state performance with both linear and non-linear loads but also provides fast dynamic response during a step change in load. A digital controller based on field programmable gate array is utilised for the simultaneous generation of high-frequency switching pulses for DC–DC converter and synchronised fundamental frequency switching pulses for H-bridge. The entire system is simulated in MATLAB/Simulink® environment and its functioning is verified with linear and non-linear loads. The hardware prototype of inverter is also built in the laboratory and its performance is validated. Further, the better performance of the proposed system for supplying household appliances is ascertained in the laboratory.

Asymmetrical Cascaded Multilevel Inverter Based on Transistor-Clamped H-Bridge Power Cell

This paper presents an asymmetrical cascaded multilevel inverter based on a five-level transistor-clamped H-bridge power cell. A two-cell configuration with a dc link voltage ratio of 4 : 1 is presented. The modulation method is based on the fundamental frequency switching. An analysis of the inverter output voltage and harmonics is presented. Injection of the third harmonic voltage as to maximize the output voltage and the issue of the inverse power flow or regeneration in the low-voltage cell are presented. The prototype of the proposed inverter was built, and its functionality was verified through experimental results.

Reduced sensor configuration of brushless DC motor drive using a power factor correction‐based modified‐zeta converter

This study deals with the design and development of a power factor (PF) correction-based modified-zeta converter fed brushless DC (BLDC) motor drive. A single-phase supply followed by a diode bridge rectifier and a modified-zeta converter operating in discontinuous inductor current mode (DICM) is used to feed a voltage source inverter (VSI) driving a BLDC motor. The modified-zeta converter operating in DICM acts as an inherent PF pre-regulator. A single-voltage sensor is used for the DC-link voltage control, which is used to control the speed of the BLDC motor. This facilitates the operation of VSI in fundamental frequency switching for reducing the switching losses in VSI. The proposed BLDC motor drive is designed and its performance is simulated in MATLAB/Simulink environment for achieving an improved power quality at AC mains for wide range of speed control. The obtained power quality indices are under the recommended limits of international power quality standard IEC 61000-3-2. Finally, the performance of the proposed drive is validated with test results obtained on a developed prototype of the proposed BLDC motor drive.

A Modified Single Phase H-Bridge Inverter for High Power Applications with Power Quality Improvement

Various multilevel inverter topologies are widely being used for real power exchange, reactive power compensation, harmonic current mitigation on grid and industrial drive applications with fundamental frequency switching mode of gate control. Still so many topologies are being currently developed with reduced number of switches, improved waveform for power quality improvement with fundamental frequency switching and pwm switching gate control mode. This paper presents the performance analysis of modified H-bridge single phase inverter for high voltage and high power applications. The switching method has been selected to operate the inverter at fundamental frequency switching mode of gate control to be free from lower order harmonics. The inverter has the modulation technique with pre calculated switching angles to generate the required fundamental voltage with reduced Total Harmonic Distortion (THD). So, the switching losses have been reduced hence the efficiency is improved with Power Quality (PQ) improvement in voltage-current waveform. The DC input power is feed to the inverter from DC capacitor voltage divider source, contributed to give various dc voltage levels during fundamental frequency switching of different switching combinations for the generation of stepping output voltage. During dynamic load condition, the magnitude of input dc voltage level across each capacitor has not undergone through big swing to feed the power to the load without affecting generated output ac voltage. The performance of the proposed inverter has been analyzed for dynamic reactive load and induction motor. The MATLAB based simulations have been presented to validate the inverter operation for dynamic reactive load and industrial drive applications with pre calculated THD reduced switching conduction angles for PQ improvement in waveform.

An Adjustable-Speed PFC Bridgeless Buck–Boost Converter-Fed BLDC Motor Drive

This paper presents a power factor corrected (PFC) bridgeless (BL) buck-boost converter-fed brushless direct current (BLDC) motor drive as a cost-effective solution for low-power applications. An approach of speed control of the BLDC motor by controlling the dc link voltage of the voltage source inverter (VSI) is used with a single voltage sensor. This facilitates the operation of VSI at fundamental frequency switching by using the electronic commutation of the BLDC motor which offers reduced switching losses. A BL configuration of the buck-boost converter is proposed which offers the elimination of the diode bridge rectifier, thus reducing the conduction losses associated with it. A PFC BL buck-boost converter is designed to operate in discontinuous inductor current mode (DICM) to provide an inherent PFC at ac mains. The performance of the proposed drive is evaluated over a wide range of speed control and varying supply voltages (universal ac mains at 90-265 V) with improved power quality at ac mains. The obtained power quality indices are within the acceptable limits of international power quality standards such as the IEC 61000-3-2. The performance of the proposed drive is simulated in MATLAB/Simulink environment, and the obtained results are validated experimentally on a developed prototype of the drive.

Comprehensive review of a recently proposed multilevel inverter

As multilevel inverters are gaining increasing importance, newer topologies are being proposed to reduce part count for large number of levels in output voltage. A simplified five-level inverter has been recently reported in the literature to reduce component count. The topology comprises of floating input DC sources connected in opposite polarities through power switches. The structure requires lesser active switches as compared with conventional cascaded H-bridge topology with much reduced switching losses. Available literature present generalisation of the topology with symmetrical sources, but no investigations are made for equal load sharing and asymmetrical configurations. This study presents a comprehensive analysis of the aforementioned topology, referred to as cross-connected sources-based multilevel inverter (CCS-MLI). The topology is analysed for both symmetric and asymmetric source configurations. Also, a new algorithm for asymmetric source configuration suitable for CCS-MLI is proposed. A control scheme is also proposed for equal load sharing in five-level topology. Investigations are made for possibility of equal load sharing in higher level structures and fundamental frequency switching of switches bearing higher voltage stresses. Various concepts are verified with simulations and experimental studies.

Power quality improvements in power factor correction Luo converter fed brushless direct current motor drive

Summary This paper presents a power factor correction (PFC) Luo converter based voltage source inverter (VSI) fed brushless direct current (BLDC) motor drive using a single voltage sensor. A single-phase diode bridge rectifier followed by a Luo converter operating in discontinuous inductor current mode (DICM) is used for the direct current link voltage control and PFC operation at alternating current (AC) mains. The speed control is achieved by varying the direct current link voltage of VSI and electronically commutating the BLDC motor using fundamental frequency switching of VSI for reduced switching losses. The proposed PFC-based Luo converter fed BLDC motor drive is designed, and its performance is simulated and validated experimentally for achieving a unity power factor at AC mains over a wide range of speed control at universal AC mains. The achieved power quality indices are observed under the acceptable limits of international power quality standard such as IEC 61000-3-2. Copyright © 2014 John Wiley & Sons, Ltd.

An Active Cancellation Circuit for Reducing Electrical Noise from Three-Phase AC Motor Drivers

A novel active cancellation circuit for reducing common-mode (CM) noise in vehicular three-phase ac motor drives is described. The cancellation circuit features a feed-forward voltage-detecting-voltage-compensating structure. Unlike other voltage-compensating circuitry employing CM transformers on the thick phase wires, the proposed circuit is compactly integrated on the inverter printed circuit board. A prototype low-voltage space-vector-pulse-width-modulation (SVPWM) inverter employing this active cancellation technique was built and tested. This cost-effective and light-weight circuit significantly reduced the CM noise at the fundamental switching frequency and harmonics up to 2 MHz.

An Improved Power Quality BIBRED Converter-Based VSI-Fed BLDC Motor Drive

Abstract This paper presents an IHQRR (integrated high-quality rectifier regulator) BIBRED (boost integrated buck rectifier energy storage DC-DC) converter-based VSI (voltage source inverter)-fed BLDC (brushless DC) motor drive. The speed control of BLDC motor is achieved by controlling the DC link voltage of the VSI using a single voltage sensor. This allows VSI to operate in fundamental frequency switching mode for electronic commutation of BLDC motor which reduces the switching losses due to high-frequency switching used in conventional approach of PWM (pulse width modulation)-based VSI-fed BLDC motor drive. A BIBRED converter is operated in a dual-DCM (discontinuous conduction mode) thus using a voltage follower approach for PFC (power factor correction) and DC link voltage control. The performance of the proposed drive is evaluated for improved power quality over a wide range of speed control and supply voltage variation for demonstrating the behavior of proposed drive. The power quality indices thus obtained are within the recommended limits by international PQ (power quality) standards such as IEC 61000-3-2.

Predictive Sorting Algorithm for Modular Multilevel Converters Minimizing the Spread in the Submodule Capacitor Voltages

The modular multilevel converter is a suitable topology for bidirectional ac-dc conversion in high-voltage high-power applications. By connecting submodule circuits in series, a high-voltage waveform with excellent harmonic performance can be achieved with a very high efficiency and low switching frequency. The balancing of the capacitor voltages will, however, become increasingly difficult as the switching frequency is reduced. Although the capacitor voltages can be kept balanced over time even at the fundamental switching frequency, the spread and thus also the peak variation in the capacitor voltages will typically increase at lower switching frequencies. This paper presents a capacitor voltage balancing strategy which aims to combine a low switching frequency with a low capacitor voltage ripple. This is done by a predictive algorithm that calculates the amount of charge that must be stored in the submodule capacitors during the following fundamental frequency period. The converter is then controlled in such a way that the stored charge in the submodule capacitors is evenly distributed among all the submodules when the capacitor voltages reach their maximum values. In this way, it is possible to limit the peak voltage in the capacitor at switching frequencies as low as 2-3 times the fundamental frequency. The capacitor voltage balancing strategy is first validated by simulation results at 110 Hz switching frequency. It is observed that when the proposed method is used, the capacitor voltage ripple is 35% lower compared to the case when a conventional sorting algorithm is used. The capacitor voltage balancing strategy is also validated experimentally at 130 Hz switching frequency. The experimental results show that it is possible to combine the proposed method with previously presented circulating-current control methods.

Controlled Strategies Using DC Voltage for Asymmetric Twin Converter for a High Power STATCOM

The proposed controller can balance individual dc capacitor voltages when H-bridges run with different switching patterns and have parameter variations. It has two advantages: 1) the controller can work well in all operation modes (the capacitive mode, the inductive mode, and the standby mode) and 2) the impact of the individual dc voltage controller on the voltage quality is small. This topology suggests further improvement Here we have to using fuzzy logic controllers in the control scheme to reduce total harmonic distortion. A three phase cascaded H-bridge inverter this control method uses a discrete-time model of the system to predict the future value of the current for all voltage vectors, and selects the vector which minimizes a cost function. Analytical solutions of pulse width-modulation (PWM) strategies for multilevel inverters are used to identify that alternative phase opposition disposition PWM for diode clamped inverters produces the same harmonic performance as phase-shifted carrier PWM for cascaded inverters, and hybrid PWM for hybrid inverters, when the carrier frequencies are set to achieve the same number of inverter switch transitions over each fundamental cycle. In order to improve the performance, a phase-shifted carrier based pulse width modulation technique is used. A mathematical model of the system is derived, based on which a controller for the scheme is designed. The effectiveness of the scheme is verified through detailed simulation study. Index Terms: DC voltage regulation, fuzzy logic controllers, voltage source converter (VSC), Pulse width modulation (PWM), static compensator (STATCOM) I. Introduction The static synchronous compensator (STATCOM) is a flexible ac transmission system device, which is connected as a shunt to the power system, for generating or absorbing reactive power (5). A STATCOM works in the capacitive mode if it injects reactive power to the power system and in the inductive mode it absorbs reactive power from the power system. A multi pulse converter uses more than one voltage source converter (VSC), with common dc link, operating with nearly fundamental switching frequency, and the output of each module is connected in series through the multi pulse transformer. By adjusting the triggering pulses of different VSCs, specified total harmonic distortion (THD) of the injected current is achieved with reduced switching losses as compared to that of single-VSC-based solution. The major drawback of this scheme is the high cost and complex structure of the bulky multi pulse transformer. Multilevel converter technology is a very efficient alternative for medium voltage and high-power applications and also for other applications where high-quality voltages and currents are required (1), (2). The other commonly used multilevel topology, i.e., cascaded converter topology comprises several single-phase H-bridge/full-bridge converters, with separate dc links. The following are the two associated problems of this topology: 1) The size of the dc-link capacitor required is high because the instantaneous power involved with each module varies at twice the fundamental frequency. 2) Regulating voltage across a large number of self supported dc-link capacitors makes the controller design complex.