Functional Hardware Description Language Research Articles

Generating circuits with generators

The most widely used languages and methods used for designing digital hardware fall into two rough categories. One of them, register transfer level (RTL), requires specifying each and every component in the designed circuit. This gives the designer full control, but burdens the designer with many trivial details. The other, the high-level synthesis (HLS) method, allows the designer to abstract the details of hardware away and focus on the problem being solved. This method however cannot be used for a class of hardware design problems because the circuit's clock is also abstracted away. We present YieldFSM, a hardware description language that uses the generator abstraction to represent clock-level timing in a digital circuit. It represents a middle ground between the RTL and HLS approaches: the abstraction level is higher than in RTL, but thanks to explicit information about clock-level timing, it can be used in applications where RTL is traditionally used. We also present the YieldFSM compiler, which uses methods developed by the functional programming community -- including continuation-passsing style translation and defunctionalization -- to translate YieldFSM programs to Mealy machines. It is implemented using Template Haskell and the Clash functional hardware description language. We show that this approach leads to short and conceptually simple hardware descriptions.

Connecting the Dots: Computer Systems Education using a Functional Hardware Description Language

A functional hardware description language enables students to gain a working understanding of computer systems, and to see how the levels of abstraction fit together. By simulating circuits, digital design becomes a living topic, like programming, and not just a set of inert facts to memorise. Experiences gained from more than 20 years of teaching computer systems via functional programming are discussed.

Processor design using a functional hardware description language

This contribution documents the development, implementation, and verification of a RISC microprocessor using the functional hardware description language Lava. Basic methods to describe hardware in Lava are introduced and extended towards implementation of instruction set architecture and pipeline structure and control. FPGA synthesis results are presented and compared against a traditional VHDL-based design flow. An implementation of a coprocessor interface used to accelerate application-specific code is discussed supported by the case study of fast Fourier transform. To authors’ best knowledge it is the first attempt to describe, simulate, verify, synthesize and test-run a complete von Neumann machine in Lava. Project experiences are summarized followed by a sketch of possible directions for further improvement of Lava in particular and functional hardware description languages in general.

A calculus for hardware description

AbstractIn efforts to overcome the complexity of the syntax and the lack of formal semantics of conventional hardware description languages, a number of functional hardware description languages have been developed. Like conventional hardware description languages, however, functional hardware description languages eventually convert all source programs into netlists, which describe wire connections in hardware circuits at the lowest level and conceal all high-level descriptions written into source programs. We develop a calculus, calledlλ (linear lambda), which may serve as an intermediate functional language just above netlists in the hierarchy of hardware description languages. In order to support higher-order functions,lλ uses a linear type system, which enforces the linear use of variables of function type. The translation oflλ into structural descriptions of hardware circuits is sound and complete in the sense that it maps expressions only to realizable hardware circuits, and that every realizable hardware circuit has a corresponding expression inlλ. To illustrate the use oflλ as a practical intermediate language for hardware description, we design a simple hardware description language that extendslλ with polymorphism, and use it to implement a fast Fourier transform circuit and a bitonic sorting network.

Functional netlists

In efforts to overcome the complexity of the syntax and the lack of formal semantics of conventional hardware description languages, a number of functional hardware description languages have been developed. Like conventional hardware description languages, however, functional hardware description languages eventually convert all source programs into netlists, which describe wire connections in hardware circuits at the lowest level and conceal all high-level descriptions written into source programs. We develop a variant of the lambda calculus, called l λ (linear lambda), which may serve as a high-level substitute for netlists. In order to support higher-order functions, l λ uses a linear type system which enforces the linear use of variables of function type. The translation of l λ into structural descriptions of hardware circuits is sound and complete in the sense that it maps expressions only to realizable hardware circuits and that every realizable hardware circuit has a corresponding expression in l λ. To illustrate the use of l λ as a high-level substitute for netlists, we design a simple hardware description language that extends l λ with polymorphism, and use it to implement a Fast Fourier Transform circuit.

Description and verification of more-dimensional regular and non-homogeneous structures using a functional hardware description language

The transformational design or guided synthesis of realistic hardware systems, starting from a high level specification and going all the way down to the gate level, imposes high demands on the formalism used for the description and verification of both system and transformations. By means of vertical transformations, a description is mapped onto a guaranteed correct, but naive implementation at a lower level of abstraction, which has to be optimized further by horizontal transformations. During this design process, an initially regular structure will gradually be transformed into a non-homogeneous one. The study of the CATHEDRAL Booth multiplier accumulator module showed that existing formalisms cannot cope with the complete guided synthesis process, especially when dealing with irregular and more-dimensional structures. For such more-dimensional structures various descriptions that are structurally equivalent can be given. In existing formalism the mutual transition or the equivalence proof is tedious. In this paper a formalism is presented that encapsulates a methodology which solves the latter problem and which supports both non-indexed descriptions, suited for regular structures, and indexed ones suited for non-homogeneous structures. The transition is completely determined within the formalism.