Function Of Drain Bias Research Articles

Physical insights into the reliability of sunken source connected field plate GaN HEMTs for mm-wave applications

This article investigates the incorporation of field plates in AlGaN/GaN High Electron Mobility Transistors (HEMTs) which leading to enhancement in the device breakdown voltage and a reduction in the reverse leakage current. Using Atlas TCAD software breakdown behavior of gate-connected field plate (GFP), gate-source (dual) field plate, and discrete source-connected field plate (Sunken SC-FP) designs with field plate length variation is probed and physical insight is developed through electric field profile, and impact ionization contour plots. By employing a Sunken SC-FP with gate length of 0.4 μm in the gate-drain access region the device breakdown voltage is improved and has high JFOM (4.8 THz·V). Also, on-resistance (RON) degradation is minimum in the Sunken SCFP (20.12 %), compared with GFP (31.20 %) and dual FP (24.96 %) architectures, when the device is stressed in the off-state (VGS = −40 V) for 1 min. The RF performance of the Sunken SC-FP HEMT is studied using small signal parameters and the load pull measurements as a function of drain bias.

Contact resistance in sub-micron and nanoscale organic thin-film transistors

Two improved methods for evaluating contact resistance in organic thin-film transistors (TFTs) are presented. These methods can be applied to TFTs with any arbitrary geometry and are also suitable for retroactive analysis of current-voltage characteristics. The first method is based on the analysis of the differential conductance of TFTs and in separating the conductivity contributions from the contacts and the channel. This method provides accurate results when the contact resistance is approximately 0.1–10 times the channel resistance. The second method is especially applicable to nanoscale and short channel length TFTs. The minimum value of differential on-resistance as a function of drain bias is used to separate the contributions of the channel and contact resistances at various drain voltages. This method is accurate when the contact resistance is approximately 0.3–10 times the channel resistance, as verified by simulations. It works even when there is no distinct saturation in current-voltage characteristics with increasing drain voltage. Both methods have been applied to experimental data from organic TFTs with channel lengths in the range 10 nm to 5 μm. • Two novel methods of extracting contact resistance in OTFTs are introduced. • Contact resistance of various channel lengths OTFTs are extracted and analyzed. • Effects of contact resistance in short channel pentacene TFTs are discussed. • New design of ultra-short channel TFTs is proposed to improve carrier injection.

An optimized nanoscale Quasi-Ballistic DG MOSFET model with diffusive carrier scattering dependency

ABSTRACT The work proposes a physically accurate quasi-ballistic drain current model valid for Double Gate (DG) MOSFETs in the nanoscale regime. The proposed quasi-ballistic model considers the carrier scattering physics and includes both ballistic and diffusive transport. Based on the concepts of scattering theory, a semi-empirical approach is used to determine the diffusive carrier scattering at the critical channel length as a function of drain bias. A generalised three region scale length model is applied to the proposed device structure with arbitrary dielectric constants and oxide thicknesses to examine the device channel length scaling limits. The significance of Eigen values and the scale length equations applicable for the proposed device structure is discussed. The drain current model essentially captures the key signature effect observed in rigorously scaled short channel devices. Further, the proposed quasi-ballistic model demonstrates its physical aptness and optimal accuracy when compared with other similar recent works. The model results obtained are verified using numerical simulations and are found to exhibit excellent continuity in all regions of the device operation.

High RF Performance GaN-on-Si HEMTs With Passivation Implanted Termination

This work reports recent progress in the sub-6 GHz power performance of GaN-based HEMTs grown on high resistivity silicon substrates with passivation implanted termination (PIT) process. Thanks to the mitigated electric field crowding at the gate edge and the suppressed negative fixed charge-induced carrier depletion, the fabricated HEMTs demonstrate a low leakage current, a high ON/OFF current ratio of 10⁸, and improved breakdown voltage associated with a current collapse at 40 V drain quiescent condition of as low as 5.6&#x0025;. S-band continuous-wave large signal measurements yield a high power-added efficiency (PAE) of 69&#x0025;, a drain efficiency (DE) of 72&#x0025;, and an output power density (<inline-formula> <tex-math notation="LaTeX">${P}_{\text{out}}$ </tex-math></inline-formula>) of 7.2 W/mm at <inline-formula> <tex-math notation="LaTeX">${V}_{\text{DS}}=30$ </tex-math></inline-formula> V. Moreover, the transistor delivers a maximum <inline-formula> <tex-math notation="LaTeX">${P}_{\text{out}}$ </tex-math></inline-formula> up to 10.2 W/mm with a peak PAE of 63.8&#x0025; at <inline-formula> <tex-math notation="LaTeX">${V}_{\text{DS}}=40$ </tex-math></inline-formula> V. The PAE and <inline-formula> <tex-math notation="LaTeX">${P}_{\text{out}}$ </tex-math></inline-formula> as a function of drain bias indicate that the transistors remain constant high PAE and linearly increased <inline-formula> <tex-math notation="LaTeX">${P}_{\text{out}}$ </tex-math></inline-formula> over a wide range of drain voltage variation. These excellent results have demonstrated the PIT process could be an attractive technique to facilitate the application of high-performance and cost-competitive GaN-on-Si HEMTs for 5G wireless base stations.

Electrical Behavior of Effects LCE and PAMDLE of the Ellipsoidal MOSFETs in a Huge Range of High Temperatures

Introduction: There is a growing interest in new electronic systems that must operate at high temperature (T) for automotive and space electronics, etc. To reach this purpose new device architectures have been proposed, such as the Gate-All-Around, double-gate, Multigate SOI MOSFETs, etc. [1]. However, there is a new concept, still little explored by the integrated circuits industries, which is based on the simple change of the gate geometry of MOSFETs [2]. This pioneering technique is capable for boosting the electrical performance of MOSFETs, thanks to two new effects of these structures, called “Longitudinal Corner Effect” (LCE) and “PArallel connection of MOSFETs with Different channel Lengths Effect” (PAMDLE) [2]. The Ellipsoidal layout style for MOSFET (EM) [4] is an example this new concept. Thus, this manuscript performs a comparative study by three-dimensional (3D) numerical simulations of the effects caused by the high T (300K-573K) in main electrical parameters of the EM in relation to the Rectangular MOSFET (RM) counterpart, regarding the same gate area, channel width and bias conditions. Furthermore, for the first time, is analyzed the electrical behaviors of LCE and PAMDLE in these conditions. Based on these results, we conclude that the EM always presents a better electrical performance {two times higher for the drain current normalized [IDS/(W/L)] and 77% higher for the transconductance normalized [gm/(W/L)]} than that found in the RM counterpart at high T. Besides, the LCE and PAMDLE always keep actives in the EM as the T increases. Results: The 3D numerical simulations were performed by using of the Sentaurus TCAD/Synopsys. The doping concentrations of the drain/source and channel are 1019cm-3 and 1017cm-3, respectively, gate thin-oxide thickness is 4.2nm and work-function of polysilicon is 4.15eV. The threshold voltages for both devices are equal to 50mV in room T.Fig.1 shows the IDS/(W/L) as a function of gate voltage (VGS) for different temperatures of the EM (Fig.1a) and RM counterpart (Fig.1b). Based on results, we observe that the Zero Temperature Coefficient (ZTC) biases of the EM and RM (VZTC) are practically similar (difference of 6%), while the EM IDS/(W/L) in the ZTC point is 142% higher than the one measured of RM, thanks the LCE and PAMDLE present in the EM structure.Fig.2 illustrates IDS/(W/L) as a function of drain bias (VDS) considering different temperatures. The EM IDS/(W/L) in all temperatures studied, considering the triode and saturation regions, are always higher (2 times higher) than the ones observed in RM counterpart.Based in these previous results, Fig.3 presents the gmmax/(W/L) and IDS_SAT/(W/L) as a function of the T. We have observed that the gmmax/(W/L) (72% and 81% for 300K and 573K, respectively, Fig.3a) and EM IDS_SAT/(W/L) (2 times higher, Fig.3b) are always higher than those found in the RM counterpart thanks to LCE and PAMDLE and they reduce with the T increases. Therefore, we have concluded that the LCE and PAMDLE are always active in this huge range of high temperatures, according Fig.4, which the resultant longitudinal electric field (RLEF) in the center of the channel length (L) of the EM (Fig.4a) reduces 6% as the T varies (300K-573K). The maps of the EM RLEF lines are illustrated in Fig.4b for different 2 Ts, wherein the width of the depletion region (d) composed by the source/channel regions reduces as the T increases. Furthermore, Fig.4c illustrates de map of the EM IDS lines which are curves near to the edges and straight in the center of the L, due to the interactions of the longitudinal electric field components (3 in the straight defined by the foci of the ellipse and 2 out of it). Conclusion: We have concluded that the LCE and PAMDLE are always actives as the T increases and consequently are capable of boosting the EM electrical performance in comparison to the one of the RM counterpart, regarding all T studied. Furthermore, as the T increases, the magnitude of the RLEF reduces 6%, because of the reduction of the Fermi Potential that defines the surface potential. Besides, we observe that the width of the region where the RLEF acts along the channel region of the EM increases due to reduction of depletion region width between source/channel regions (from d1 to d2), as the T increases. Acknowledgment: We thank to the São Paulo Research Foundation (FAPESP), grant #2017/10718-7 and CNPq, grant #308702/2016-6 for financial support.

Bias-Dependent Variation in FinFET SRAM

In this brief, we investigate device variability in advanced fin field effect transistor (FinFET) static random access memory (SRAM) devices (12 and 7 nm) as a function of drain-to-source (Vds) bias. Drain-induced barrier lowering (DIBL) and the variation in DIBL are found to exhibit a logarithmic dependence with drain bias in the advanced node FinFET devices. Correctly capturing the DIBL and device variation as a function of drain bias is required, as the SRAM operation voltage range is expanded. We show the improved hardware correlation in Vmin yield and the improved slow corner read performance when the Vds-dependent variation is considered.

ScAlN/GaN High-Electron-Mobility Transistors With 2.4-A/mm Current Density and 0.67-S/mm Transconductance

We report the dc and RF performance of ScAlN/GaN high-electron-mobility transistors (HEMTs). The ScAlN/GaN material was epitaxially grown onto a GaN template on a 4-in 4H-SiC substrate by molecular beam epitaxy. The sheet resistance was measured to be 236 ± 4 $\Omega /\square $ across the wafer by the transfer length measurement. Selective area regrowth of highly doped GaN was implemented to reduce contact resistance ( ${R}_{C}$ ) as low as 0.1 $\Omega \cdot \textsf {mm}$ . HEMT devices with $\textsf {2}\times \textsf {150}\,\,\mu \text{m}$ gate width and 140-nm T-gate process show a maximum current density and a transconductance of 2.4 A/mm and 0.67 S/mm, respectively. The extrinsic small-signal gain was measured as a function of drain bias and gate length with extrinsic cutoff frequency and maximum oscillation frequency reported up to 88 and 91 GHz, respectively.

3-D multilayer monolithic integration of vertical-oriented double-heterojunction GaAs based pHEMT and thermal influence on device parameters

This study focuses on 3-D multilayer monolithic integration of vertical-oriented double-heterojunction AlGaAs/InGaAs/GaAs based pseudomorphic high electron mobility transistors. The effects of the presence of 3-D components above the active layer were accomplished by comparing three multilayer fabricated device of different thickness with a virgin device where the thickness of the 3-D components e.g., both metal and polyimide layer were varied. The output current, on-state gate leakage, transconductance are found to be decrease with the increase in thickness of the 3-D components and on the other hand, the on-state resistance, knee voltage and off-state gate leakage is increased. Lastly, the thermal influences on the device behaviour such as off-state and on-state gate leakage, barrier inhomogeneities at Schottky contacts, zero temperature coefficients at the transfer curve, and the threshold voltage as a function of drain bias were measured and analyzed for the both pre and post fabricated multilayer devices. These effective comparisons in terms of thickness and temperature of the both device are useful for future designs and optimizations of multilayer vertical stacked 3-D MMICs.

Field-assisted emission in AlGaN/GaN heterostructure field-effect transistors using low-frequency noise technique

We utilized low-frequency noise measurements to probe electron capture and emission from the traps in AlGaN/GaN heterostructure field-effect transistors as a function of drain bias. The excess noise-spectra due to generation-recombination effect shifted higher in frequency with the elevated temperature from room temperature up to 446 K. These temperature dependent noise measurements were carried out for four different drain-bias values from 4 up to 16 V with 4 V increments. The shift of the excess-noise in frequency was also seen with increasing drain bias. The characteristic recharging times for the trapped electrons varied within the range of 26 μs − 32 ms for the highest and lowest values of the drain voltage and temperature used in the experiment, respectively. The activation energies of the traps corresponding to the four different voltage values were extracted using temperature dependence by Arrhenius analysis. The trap energy at zero drain-bias was obtained as 0.71 eV by the extrapolation technique. This result suggests that the LFN is a very sensitive diagnostic tool to characterize trap states.

Drain disturb during CHISEL programming of NOR flash EEPROMs-physical mechanisms and impact of technological parameters

The origin of drain disturb in NOR Flash EEPROM cells under channel initiated secondary electron (CHISEL) programming operation is identified. A comparative study of drain disturb under channel hot electron (CHE) and CHISEL operation is performed as a function of drain bias and temperature on bitcells having different floating gate length and junction depth. The disturb mechanism is shown to originate from band-to-band tunneling under CHISEL operation, unlike that under CHE operation that originates from source-drain leakage. The effect of technological parameters (channel doping and drain junction depth) on CHISEL drain disturb is studied for both the charge gain (erased cell) and charge loss (programmed cell) disturb modes. Fullband Monte Carlo device simulations are used to explain the experimental results. It is shown that methods for improving CHISEL programming performance (higher channel doping and/or lower drain junction depth or halo) increase drain disturb, which has to be carefully considered for efficient design of scaled cells.

Transient behavior of the kink effect in partially-depleted SOI MOSFET's

The behavior of transients in the drain current of partially-depleted (PD) SOI MOSFET's down to L/sub eff/=0.2 /spl mu/m is examined as a function of drain bias, gate pulses of varying magnitude (V/sub GS/), pulse duration, and pulse frequency. At fixed V/sub DS/, the gate is pulsed to values ranging from 0.1 V above V/sub T/ to V/sub GS/=V/sub DS/. A slow transient is seen when the drain is biased at a V/sub DS/ where the current kink is observable. This slow transient can be on the order of microseconds depending on the relative magnitude of the impact ionization rate. For short times after the pulse edge or for very short pulses at low frequencies, it is shown that the subthreshold drain current value can be very different from the corresponding DC, and that the kink characteristic of PD MOSFET's disappears. However, the kink values can be approached when the pulse frequency and/or duration applied to the gate is increased, due to the latent charge maintained in the floating body at higher frequencies. No transient current effects were observed in fully-depleted SOI MOSFET's. >

Measuring the drain voltage dependent series resistance in submicron LDD MOSFET's

Though already much attention was paid to the gate-voltage dependence of the MOSFET series resistance [1] the behaviour of the drain series resistance as a function of drain bias could not be measured until now. In this paper a general measurement principle to determine the series resistance in a LDD MOSFET as a function of drain bias is developed. Measured results for a 0.7 ?m device are given.

Hot-carrier degradation of single-drain PMOSFETs with differing sidewall spacer thicknesses

The effect of the sidewall spacer thickness on the hot-carrier degradation of buried-channel PMOS transistors with a sidewall-offset single drain structure was studied. At the bias stress condition of maximum gate current, a large degradation was observed for transistors with no overlap between gate and drain. Results of measurements using the charge-pumping technique suggest that trapping of a large number of electrons in the CVD SiO/sub 2/ sidewall spacer is responsible for the enhanced degradation. This was also confirmed by the measurement of the threshold voltage as a function of drain bias. >