Fully-depleted SOI Research Articles

Low-Power Redundant-Transition-Free TSPC DET-FF with STCB for Enhanced Power and Area Efficiency

Abstract: In the contemporary era dominated by graphics processing units (GPUs) and artificial intelligence (AI), flip-flops (FFs) have emerged as power-intensive components within processors. Addressing this power consumption challenge, a pioneering approach introduces a single-phase clock dual-edge-triggering (DET) FF leveraging a single-transistor clocked (STC) buffer (STCB). This STCB employs a singular clocked transistor in the data sampling path, eliminating clock redundant transitions (RTs) and internal RTs observed in alternative DET designs. Validated through post-layout simulations in 22 nm fully depleted silicon on insulator (FD-SOI) CMOS, the proposed STC-DET surpasses existing state-of-the-art low-power DETs in power efficiency, boasting the lowest power-delay-product (PDP) among its counterparts. The modified clock gating, Sapon, Transmission Gate, and gate approach, detailed in the base paper, further refines the TSPC STCDET design, presenting techniques to reduce parameters such as delay or power

Monolithically Integrated Quantum Dots in a 22‐nm Fully Depleted Silicon‐on‐Insulator Process Operating at 3 K

ABSTRACTQuantum computers comprising large‐scale arrays of qubits will enable complex algorithms to be executed to provide a quantum advantage for practical applications. A prerequisite for this milestone is a power‐efficient qubit control and detection system operating at cryogenic temperatures. Implementing such systems in complementary metal‐oxide‐semiconductor (CMOS) technology offers clear advantages in terms of scalability. Here, we present a fully integrated quantum dot array in which silicon quantum wells are co‐located with control and detection circuitry on the same die in a commercial 22‐nm fully depleted silicon‐on‐insulator (FDSOI) process. Our system comprises a two‐dimensional quantum dot array, integrated with 8 detectors and 32 injectors, operating at 3 K inside a cryo‐cooler. The power consumption of the control and detection circuitry is 2.5 mW per qubit without body biasing. The design utilizes 0.8‐V nominal devices. The setup allows us to verify discrete charge injection control and detection at the quantum dot array and demonstrate the feasibility of this architecture for scaling up the existing quantum core to hundreds and thousands of physical qubits.

Asynchronous interface circuit for nonlinear connectivity in multicore spiking neural networks

AbstractTo expand the scale of spiking neural networks (SNNs), an interface circuit that supports multiple SNN cores is essential. This circuit should be designed using an asynchronous approach to leverage characteristics of SNNs similar to those of the human brain. However, the absence of a global clock presents timing issues during implementation. Hence, we propose an intermediate latching template to establish asynchronous nonlinear connectivity with multipipeline processing between multiple SNN cores. We design arbitration and distribution blocks in the interface circuit based on the proposed template and fabricate an interface circuit that supports four SNN cores using a full‐custom approach in a 28‐nm CMOS (complementary metal–oxide–semiconductor) FDSOI (fully depleted silicon on insulator) process. The proposed template can enhance throughput in the interface circuit by up to 53% compared with the conventional asynchronous template. The interface circuit transmits spikes while consuming 1.7 and 3.7 pJ of power, supporting 606 and 59 Mevent/s in intrachip and interchip communications, respectively.

A novel nanoscale FD-SOI MOSFET with energy barrier and heat-sink engineering for enhanced electric field uniformity

This paper aims to present a novel method to mitigate the undesirable issues associated with short-channel-effects (SCEs) and the critical lattice temperature of a fully depleted silicon-on-insulator (FD-SOI) MOSFET in the nanoscale regime. The proposed approach is based on simultaneously merging the energy barrier and heat-sink engineering simultaneously. Hafnium oxide as a high-k dielectric inside the channel region around the drain region is embedded to redistribute the band energy resulting in the enhancement of the energy barrier. This reformation of the band profile reduces variations in the channel depletion charge volume percentage caused by the drain voltage, thereby mitigating short-channel effects (SCEs). In order to promote effective thermal conduction, a portion of the buried oxide is replaced by doped P-type silicon which acts as an effective heat-sink. The devices under the investigation have been simulated using SILVACO software, considering the comprehensive physical models. Drain-Induced Barrier Lowering (DIBL), leakage current, Ion to Ioff ratio, subthreshold swing, hot carrier effect and lattice temperature as the essential parameters have been successfully improved for the proposed device in comparison to the conventional device.

Nonlinear behaviors in back-gate effects of FDSOI MOSFETs at cryogenic temperatures

In this work, we systematically investigate the DC performance of fully depleted silicon-on-insulator (FD-SOI) MOSFETs at both room and cryogenic temperatures as low as 77 K. The influences of back-gate bias on normal and flip-well devices are measured and analyzed. Both types devices display non-linear behaviors when adjusting the back-gate voltage at cryogenic temperatures. Notably, the non-linear effects are more prominent in normal-well devices. The possible reasons are analyzed and verified by technology computer aided design simulation, suggesting that normal-well devices are more susceptible to the formation of depletion regions between the buried oxide layer and the well. This phenomenon disrupts the linearity of the back-gate effect. This research contributes to understanding and characterizing of the back-gate effects in cryogenic environments and holds potential for high-performance computing applications.

A two-stage slicer employing body biasing for 64-Gb/s PAM4 wireline receiver in 22-nm FDSOI technology

—A 64Gbps 4-level pulse amplitude modulation (PAM4) mixed-signal receiver incorporating a decision-feedback equalizer (DFE) for application in wireline communication is implemented in fully-depleted silicon-on-insulator (FDSOI) 22nm technology. A two-stage slicer with body biasing is proposed to alleviate the stringent timing constraint of the closed-loop DFE. The smaller loading of the first stage shortens the output delay so as to provide a much larger differential input for the second stage. Moreover, body biasing is applied to the proposed slicer to allow higher drive and faster switching capabilities. Simulation results demonstrate that the receiver with body biased two-stage slicer achieves at least 9.9 % and 14.3 % improvements in recovered eye height and eye width over the receiver with StrongArm slicer. The receiver consumes a power of 117.1mW, achieving 1.83pJ/bit energy efficiency.

Expanding the time-interleaving design capabilities: A 28 GS/s 4-bit time-interleaved current-steering DAC case study

In this work, a novel approach of designing high-speed time-interleaved Digital-to-Analog Converters (DACs), that exploits high-order time-interleaved factors, was proposed. The presented time-interleaving design approach is based on the current superposition principle, capable of expanding the time-interleaved factor of DACs without compromising the conversion linearity and accuracy. For the validation of the proposed design approach, a 28 GS/s 4-bit 4 × Time-Interleaved current-steering DAC was designed using a 22 nm Fully-Depleted Silicon-On-Insulator (FDSOI) CMOS process node. Post-layout simulations were carried out by developing a custom, hybrid RC/RLCk parasitic extraction methodology, capable of capturing all possible layout parasitic effects due to the high conversion speed of the designed DAC. Using the proposed approach, the designed time-interleaved DAC was capable of achieving ENOB>3.83 bits, SFDR>28.7 dBc for fin≤1.75 GHz, with no missing codes and a low power consumption of Pdiss=3.1 mW/core.

Shallow Trench Isolation Patterning to Improve Photon Detection Probability of Single-Photon Avalanche Diodes Integrated in FD-SOI CMOS Technology

The integration of Single-Photon Avalanche Diodes (SPADs) in CMOS Fully Depleted Silicon-On-Insulator (FD-SOI) technology under a buried oxide (BOX) layer and a silicon film containing transistors makes it possible to realize a 3D SPAD at the chip level. In our study, a nanostructurated layer created by an optimized arrangement of Shallow Trench Isolation (STI) above the photosensitive zone generates constructive interferences and consequently an increase in the light sensitivity in the frontside illumination. A simulation methodology is presented that couples electrical and optical data in order to optimize the STI trenches (size and period) and to estimate the Photon Detection Probability (PDP) gain. Then, a test chip was designed, manufactured, and characterized, demonstrating the PDP improvement due to the STI nanostructuring while maintaining a comparable Dark Count Rate (DCR).

Research on the Coupling Effect of NBTI and TID for FDSOI pMOSFETs.

The coupling effect of negative bias temperature instability (NBTI) and total ionizing dose (TID) was investigated by simulation based on the fully depleted silicon on insulator (FDSOI) PMOS. After simulating the situation of irradiation after NBT stress, it was found that the NBTI effect weakens the threshold degradation of FDSOI PMOS under irradiation. Afterward, NBT stress was decomposed into high gate voltage stress and high-temperature stress, which was applied to the device simultaneously with irradiation. The devices under high gate voltage exhibited more severe threshold voltage degradation after irradiation compared to those under low gate voltage. Devices at high temperatures also exhibit more severe threshold degradation after irradiation compared to devices under low temperatures. Finally, the simultaneous effect of high gate voltage, high temperature, and irradiation on the device was investigated, which fully demonstrated the impact of the NBT stress on the TID effect, resulting in far more severe threshold voltage degradation.

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology.

After more than five decades, Moore's Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

Gradient voltage amplification effect in FDSOI NCFET with thickness-variable ferroelectric layer

In this paper, a negative capacitance field effect transistor with thickness variable ferroelectric layer (TVFL NCFET) based on the fully depleted silicon on insulator (FDSOI) is proposed. The TVFL NCFET features the linearly increased ferroelectric layer thickness along the channel from source to drain. The gradient voltage amplification effect caused by the TVFL is analyzed according to the proposed capacitance model and simulation. Both of the model and numerical results indicate that the TVFL leads to a gradient increased electrostatic potential distribution along the bottom of the ferroelectric layer. The influences of gradient voltage amplification effect on the transfer characteristics, the output characteristic, the ratio between on-state-current (I ON) and off-state-current (I OFF), the drain induced barrier lowering (DIBL) and the subthreshold swing (SS) are investigated. The results show that the TVFL NCFET achieves the SS of 53.14 mV/dec, which is reduced by 19% when compared to the conventional NCFET. Meanwhile, large ION/IOFF is also realized and up to 1012 at most.

Enabling low-power analog and RFIC design through advanced semiconductor FDSOI MOSFETs

This study investigates the electrical performance of advanced semiconductor Ge-pocket-doped fully depleted silicon-on-insulator MOSFETs in comparison to conventional fully depleted silicon-on-insulator (FDSOI) MOSFETs. In this study vital electrical parameters such as the drain current, band diagram, lateral electric field, surface potential, and work function of the gate material were investigated. The advanced Ge pocket-doped FDSOI MOSFET structure demonstrates superior characteristics, such as a higher Ion/Ioff ratio, smaller subthreshold slope, lower capacitance, and higher cut-off frequency, when compared to conventional FDSOI MOSFETs. The structure of the Ge pocket-doped FDSOI MOSFET in the source and drain regions is designed to overcome the scaling effects of the transistor. In addition, this paper delves into the fabrication of the proposed device structure, outlining the key steps and intricacies involved. This study shows that the proposed device can be used for both digital and analog applications because it has good switching performance and a low cut-off frequency. In addition, the fabrication steps of the proposed structure were compatible with the existing fabrication process steps for conventional FDSOI MOSFETs. The simulation and analysis of the advanced semiconductor structure were performed using the Sentaurus TCAD simulator.

A Broadband Millimeter-Wave 5G Low Noise Amplifier Design in 22 nm Fully Depleted Silicon-on-Insulator (FD-SOI) CMOS

This paper presents a broadband millimeter-wave (mm-Wave) low noise amplifier (LNA) designed in a 22 nm fully depleted silicon-on-insulator (FD-SOI) CMOS technology. Electromagnetic (EM) simulations suggest that the LNA has a 3-dB bandwidth (BW) from 17.8 to 42.4 GHz and a fractional bandwidth (FBW) of 81.7%, covering the key frequency bands within the mm-Wave 5G FR2 band, with its noise figure (NF) ranging from 2.9 to 4.9 dB, and its input-referred 1-dB compression point (IP1dB) of −17.9 dBm and input-referred third-order intercept point (IIP3) of −8.5 dBm at 28 GHz with 15.8 mW DC power consumption (PDC). Using the FOM (figure-of-merit) developed for broadband LNAs (FOM = 20 × log((Gain[V/V] × S21-3 dB-BW [GHz])/(PDC [mW] × (F-1)))), this LNA achieves a competitive FOM (FOM = 18.9) among reported state-of-the-art mm-Wave LNAs in the literature.

Characteristics and ultra-high total ionizing dose response of 22 nm fully depleted silicon-on-insulator

The radiation response of MOS transistors in a 22 nm Fully Depleted Silicon-On-Insulator (FDSOI) technology exposed to ultra-high total ionizing dose (TID) was investigated. Custom structures including n- and p-channel devices with different sizes and threshold voltage flavours were irradiated with X-rays up to a TID of 100 Mrad(SiO2) with different back-gate bias configurations, from -8 V to 2 V. The investigation revealed that the performance is significantly affected by TID, with the radiation response being dominated by the charge trapped in the buried oxide.

Simulation study of trap-induced noise characteristics in FDSOI MOSFETs

The trap-induced noise characteristics of fully-depleted SOI (FDSOI) MOSFETs with ultra-thin body and buried oxide are essential for high-performance applications. However, accurate noise modeling and traps identification of the device remains challenging. In this work, we investigate the noise characteristics of FDSOI MOSFETs arising from traps in both the gate dielectric (GD) and the buried oxide (BOX). By using TCAD tool, we examine the noise generated by traps at various energy levels and spatial positions in GD and BOX under different biases. The simulation results reveal that traps in GD and BOX exhibit distinctly different behaviors as Vg increases, providing insights for identifying traps from noise measurement results.

Analysis and 3D TCAD simulations of single-qubit control in an industrially-compatible FD-SOI device

In this study, 3D simulations are introduced to analyze electric-dipole spin resonance (EDSR) for a spin qubit defined in a 28nm-node Ultra-Thin Body and Buried oxide (UTBB) Fully-Depleted Silicon-On-Insulator (FD-SOI) device operated at cryogenic temperatures. The device under consideration is designed to be compatible with STMicroelectronics’ standard fabrication techniques. The simulations predict the experimental and device parameters (e.g. drive amplitude, leakage, and Rabi frequency) required to make EDSR a viable means of qubit control before the device is fabricated. This work highlights how 3D TCAD tools which can simulate quantum-mechanical effects can help steer the design of quantum devices.

Synaptic Characteristics of Fully Depleted Silicon‐on‐Insulator Metal‐Oxide‐Semiconductor Field‐Effect Transistors and Synapse‐Neuron Arrayed Neuromorphic Hardware System

A fully depleted silicon‐on‐insulator (FDSOI) metal‐oxide‐semiconductor field‐effect transistors (MOSFETs) device is investigated as for an electronic synapse emulating the synaptic functions of the human brain with stable characteristics. Gate‐last processed FDSOI MOSFET with a high‐k/metal gate stack features a memory window of 103. Synaptic conductance is stably regulated by utilizing the FDSOI MOSFET, which offers the advantage of mitigating leakage current when compared to bulk Si MOSFET. Short‐ and long‐term plasticity are investigated by applying engineered pulse, verifying the long‐term synaptic properties of pattern recognition processes. With controllable synaptic conductance, the trade‐off between conductance change and linearity regarding the recognition rate is evaluated, attaining a recognition rate of 0.83. To verify the pre‐ and post‐synaptic weights within a real hardware‐based neuromorphic system, 5 × 6 FDSOI field‐effect transistor (FET) synapse array is interconnected to 10 × 10 leaky integrate‐and‐fire (LIF) neuron array. The synaptic plasticity of FDSOI MOSFET in post‐neurons following neuron firing in the neuron device is successfully demonstrated. These results indicate that FDSOI MOSFET devices could be applicable as synapse devices due to controllability and capability to realize signal transmissions and self‐learning processes simultaneously and used to mimic a synapse neuron network system by configuring a hardware system interconnected with the LIF neuron.

Digit-Serial DA-Based Fixed-Point RNNs: A Unified Approach for Enhancing Architectural Efficiency.

The next crucial step in artificial intelligence involves integrating neural network models into embedded and mobile systems. This requires designing compact and energy-efficient neural network models in silicon for optimized performance. This article introduces a unified approach for enhancing the architectural efficiency of long short-term memory (LSTM) recurrent neural networks (RNNs). Precisely, two new structures (I and II) based on the two's complement (TC) digit-serial distributed arithmetic (DSDA) technique are presented. The block-circulant matrix-vector multiplications (MVMs) and element-wise multiplications (EWMs) are formulated using TC DSDA. In addition, a fixed-point (FxP) training procedure for quantized LSTM RNNs is considered and validated for speech recognition tasks. Both structures leverage the circular rotation of weights and generate partial products with input digit slices. A new partial-product generator (PPG) and partial-product selector (PPS) designed to work with both unsigned and signed digits is introduced. In Structure I, a nonpipelined MVM is realized with a few PPGs and PPSs, followed by a shift-accumulate unit (SAU). Conversely, in Structure II, a suitably chosen depth-pipelined MVM is achieved with multiple PPGs and PPSs, followed by a shift-to-add tree (SAT). A critical path delay (CPD) analysis for both the proposed structures is also presented. Compared with previous works, post-synthesis results on 28 -nm fully depleted silicon-on-insulator (FDSOI) technology reveal that for a model size of 128 × 128 , Structures I and II provide 39.87% , 95.63% , and 30.95% , 91.18% more area and energy efficiencies, respectively.

Two-dimensional analytical model for fully depleted SOI MOSFETs with vertical trapezoid doping including effects of the interface trapped charges

The two-dimensional (2D) potential distribution for vertical trapezoidal doping thin-body fully depleted (FD) silicon-on-insulator (SOI) devices is derived by adopting the evanescent mode analysis method, in which the 2D effects in gate oxide region, channel region and buried oxide region are taken into account. Moreover, the effects of interface trapped charge are considered. Using this potential model, the subthreshold performance of the device including subthreshold current, and subthreshold swing under various conditions have been studied. The result shows that the analytical model is good agreement with the simulated results. Therefore, it provides a feasible way of developing new 2D models for vertical trapezoidal doping thin-body FD SOI devices. Besides offering the physical insight into device physics, the analytical model provides the basic designing guidance for vertical trapezoidal doping thin-body FD SOI devices.

Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET.

Single-port ferroelectric FET (FeFET) that performs write and read operations on the same electrical gate prevents its wide application in tunable analog electronics and suffers from read disturb, especially in the high-threshold voltage (VTH) state as the retention energy barrier is reduced by the applied read bias. To address both issues, we propose to adopt a read disturb-free dual-port FeFET where the write is performed on the gate featuring a ferroelectric layer and the read is done on a separate gate featuring a nonferroelectric dielectric. Combining the unique structure and the separate read gate, read disturb is eliminated as the applied field is aligned with polarization in the high-VTH state, thus improving its stability, while it is screened by the channel inversion charge and exerts no negative impact on the low-VTH state stability. Comprehensive theoretical and experimental validation has been performed on fully depleted silicon-on-insulator (FDSOI) FeFETs integrated on a 22 nm platform, which intrinsically has dual ports with its buried oxide layer acting as the nonferroelectric dielectric. Novel applications that can exploit the proposed dual-port FeFET are proposed and experimentally demonstrated for the first time, including FPGA that harnesses its read disturb-free feature and tunable analog electronics (e.g., frequency tunable ring oscillator in this work) leveraging the separated write and read paths.