Full Si Research Articles

Deciphering the Impact of Current, Composition, and Potential on the Lithiation Behavior of Si-Rich Silicon-Graphite Anodes.

Adding silicon (Si) to graphite (Gr) anodes is an effective approach for boosting the energy density of lithium-ion batteries, but it also triggers mechanical instability due to Si volume changes upon (de)lithiation reactions. In this work, component-specific (de)lithiation dynamics on Si-rich (30 and 70wt.% Si) SiGr anodes at various charge/discharge C-rates are unveiled and compared to a graphite-only electrode (100Gr) via operando synchrotron X-ray diffraction coupled with differential capacity plots analysis. Results show preferential lithiation of amorphous Si above ≈200mV and competing lithiation of Gr, amorphous Si, and crystalline Si below ≈200mV. Discharge proceeds via sequential delithiation of Gr and amorphous lithium silicide. Si shifts the interconversion potentials of graphite intercalation compounds, lowering the Gr state of charge compared to 100Gr. In the 30%Si electrode, crystalline Si amorphization at potentials <110mV is found to be kinetically hindered at C-rates higher than C/5, which can be key for enhancing the cycling stability of SiGr anodes. The 70%Si electrode exhibits restricted lithium diffusion in Gr, full Si amorphization, and Li15Si4 formation. These findings related to the potential- and current-dependent dynamic changes on SiGr blends are crucial for designing stable high energy density SiGr anodes.

The Fate of “Immobile” Ti in Hyaloclastites: An Evidence from Silica–Iron-Rich Sedimentary Rocks of the Urals Paleozoic Massive Sulfide Deposits

The formation of Paleozoic silica–iron-rich sedimentary rocks in the Urals volcanic-hosted massive sulfide (VHMS) deposits is considered a result of seafloor alteration of hyaloclastites mixed with calcareous/organic or sulfide material. These rocks host various Ti mineral phases pointing to the transformation of precursor metacolloidal TiO2 phases to disordered anatase during seafloor alteration of hyaloclastites, which was later converted to globules and clusters and further to diagenetic rutile. The LA-ICP-MS analysis showed that the Ti content of hyaloclasts partly replaced by finely dispersed Si–Fe aggregates increases to 540–2950 ppm and decreases (&lt;5 ppm) in full Si–Fe pseudomorphs after hyaloclasts. LA-ICP-MS element mapping reveals the enrichment in V, U, Cr, W, Nb, Pb, and Th of the anatase globules and the local accumulation of Zr, Y, and REE on their periphery. Corrosive biogenic textures in the outer zones of some hyaloclasts and biomorphic aggregates in rocks contain anatase particles in assemblage with apatite indicating the biophilic properties of Ti. This work fills the knowledge gaps about Ti mobilization during low-temperature seafloor alteration of hyaloclastites in VHMS deposits.

Modelling atomic and nanoscale structure in the silicon–oxygen system through active machine learning

Silicon–oxygen compounds are among the most important ones in the natural sciences, occurring as building blocks in minerals and being used in semiconductors and catalysis. Beyond the well-known silicon dioxide, there are phases with different stoichiometric composition and nanostructured composites. One of the key challenges in understanding the Si–O system is therefore to accurately account for its nanoscale heterogeneity beyond the length scale of individual atoms. Here we show that a unified computational description of the full Si–O system is indeed possible, based on atomistic machine learning coupled to an active-learning workflow. We showcase applications to very-high-pressure silica, to surfaces and aerogels, and to the structure of amorphous silicon monoxide. In a wider context, our work illustrates how structural complexity in functional materials beyond the atomic and few-nanometre length scales can be captured with active machine learning.

High-Performance Dual-Ion Battery Based on Silicon-Graphene Composite Anode and Expanded Graphite Cathode.

Dual-ion batteries (DIBs) are a new kind of energy storage device that store energy involving the intercalation of both anions and cations on the cathode and anode simultaneously. They feature high output voltage, low cost, and good safety. Graphite was usually used as the cathode electrode because it could accommodate the intercalation of anions (i.e., PF6-, BF4-, ClO4-) at high cut-off voltages (up to 5.2 V vs. Li+/Li). The alloying-type anode of Si can react with cations and boost an extreme theoretic storage capacity of 4200 mAh g-1. Therefore, it is an efficient method to improve the energy density of DIBs by combining graphite cathodes with high-capacity silicon anodes. However, the huge volume expansion and poor electrical conductivity of Si hinders its practical application. Up to now, there have been only a few reports about exploring Si as an anode in DIBs. Herein, we prepared a strongly coupled silicon and graphene composite (Si@G) anode through in-situ electrostatic self-assembly and a post-annealing reduction process and investigated it as an anode in full DIBs together with home-made expanded graphite (EG) as a fast kinetic cathode. Half-cell tests showed that the as-prepared Si@G anode could retain a maximum specific capacity of 1182.4 mAh g-1 after 100 cycles, whereas the bare Si anode only maintained 435.8 mAh g-1. Moreover, the full Si@G//EG DIBs achieved a high energy density of 367.84 Wh kg-1 at a power density of 855.43 W kg-1. The impressed electrochemical performances could be ascribed to the controlled volume expansion and improved conductivity as well as matched kinetics between the anode and cathode. Thus, this work offers a promising exploration for high energy DIBs.

Medium-Temperature-Oxidized GeOx Resistive-Switching Random-Access Memory and Its Applicability in Processing-in-Memory Computing

Processing-in-memory (PIM) is emerging as a new computing paradigm to replace the existing von Neumann computer architecture for data-intensive processing. For the higher end-user mobility, low-power operation capability is more increasingly required and components need to be renovated to make a way out of the conventional software-driven artificial intelligence. In this work, we investigate the hardware performances of PIM architecture that can be presumably constructed by resistive-switching random-access memory (ReRAM) synapse fabricated with a relatively larger thermal budget in the full Si processing compatibility. By introducing a medium-temperature oxidation in which the sputtered Ge atoms are oxidized at a relatively higher temperature compared with the ReRAM devices fabricated by physical vapor deposition at room temperature, higher device reliability has been acquired. Based on the empirically obtained device parameters, a PIM architecture has been conceived and a system-level evaluations have been performed in this work. Considerations include the cycle-to-cycle variation in the GeOx ReRAM synapse, analog-to-digital converter resolution, synaptic array size, and interconnect latency for the system-level evaluation with the Canadian Institute for Advance Research-10 dataset. A fully Si processing-compatible and robust ReRAM synapse and its applicability for PIM are demonstrated.Graphical

Preparation of Low Surface Area Si-Alloy Anodes for Li-Ion Cells by Ball Milling

A new and simple 2-step milling technique is utilized to produce Si–Ti–N alloys with significantly reduced surface area compared to conventional ball milling, while still attaining a full amorphous active Si phase. Surface area reductions of up to 100% were obtained by this method. Surprisingly, this did not result in significant differences in cycling stability compared to conventionally ball milled high surface area alloy materials. This is likely because cycling caused severe fracturing of the alloy surfaces, resulting in a high surface area, regardless of the initial surface area of the alloy. This suggests that, unlike other anode materials such as graphite, reducing the initial surface area of Si alloys does not translate into reduced electrolyte reactivity.

Performance Evaluation of Si/SiC Hybrid Switch-Based Three-Level Active Neutral-Point-Clamped Inverter

In this paper, two types of Silicon (Si) IGBT and Silicon Carbide (SiC) hybrid switch (Si/SiC HyS) based three-level active neutral-point-clamped (3L-ANPC) inverter are proposed for high efficiency and low device cost. The proposed Si/SiC HyS-based 3L-ANPC inverters are compared with the full Si IGBT, full SiC MOSFET, and Si with SiC devices-based hybrid 3L-ANPC solutions on the inverter efficiency, power capacity, and device cost. It is shown that compared with the full Si IGBT 3L-ANPC solution, the inverter efficiency improvement by Si/SiC HyS is 2.4% and 1.8% at light load condition and heavy load condition, respectively. Compared to the full SiC MOSFET solution and 2-SiC MOSFETs hybrid scheme, the device cost of 2-Si/SiC HyS-based 3L-ANPC is reduced by 78% and 50% with 0.28% and 0.21% maximum inverter efficiency sacrifices. The testing results show that the proposed Si/SiC HyS-based 3L-ANPC inverter is a cost-effective way to realize high inverter efficiency. Between the two proposed Si/SiC HyS-based 3L-ANPC inverters, the 2-Si/SiC HyS-based 3L-ANPC inverter has lower device cost which makes it more suitable for cost-sensitive and high efficiency applications. While the 4-Si/SiC HyS-based 3L-ANPC inverter has higher output power capacity, making it a better candidate for high power density, high power capacity, and high efficiency applications.

Epitaxial Ge-on-Nothing Virtual Substrates for 3D Device Stacking Technologies

Future monolithic heterogeneous integration of Ge and IIIV materials in electronic, optoelectronic and photonic devices requires advanced layer transfer and 3D device stacking technologies, which starts with the fabrication of suitable (virtual) substrates. A layer transfer process based on the reorganization of macro-porous Si at high temperature was developed by imec [1]. The developed fabrication scheme to fabricate macropores is based on standard UV lithography and dry etching techniques rather than electrochemical etching. This enables an easy transfer to full Si wafers (up to 300 mm). During a high-temperature step, the top part of the macro-porous Si reflows. By using proper anneal conditions, the layer detaches from the mother substrate, being anchored by a few attachment points only, forming a ‘Si on nothing’ (SoN) stack (Fig. 1a). The suspended Si layer can then easily be transferred to another substrate.In this contribution, we assess the suitability of macro-porous Si and SoN as starting material for Ge virtual substrates. The goal is to provide a fabrication scheme that allows an easy detachment of the virtual substrate after wafer to wafer bonding. Macro-porous Si was only fabricated in the inner 10x10 cm2 area of 200 mm wafers using imec’s qualified fabrication scheme. Ge layers were simultaneously grown on the inner macro-porous Si (or SoN) and the outer bulk Si. This allows to compare the material properties without the risk of wafer to wafer variations due to non-reproducibility issues. Our approach for making macro-porous Si and SoN provides mono-crystalline, nearly defect-free, and extremely smooth Si starting surfaces. A standard low temperature epitaxial Ge growth process in an ASM-Epsilon® 2000 system was used to deposit the Ge layers [2].As an example, Fig. 1b shows a 1.25 mm thick mono-crystalline epitaxial Ge layer grown on a macro-porous Si layer. The Ge growth proceeds in a 2-dimensional mono-crystalline growth mode. The surface morphology of the grown Ge is not affected by the starting surface (Fig. 1c,d). The Full Width at Half Maximum (FWHM) as extracted from w-2q High Resolution X-ray Diffraction scans acquired around the Ge (004) Bragg peak is strongly reduced after a post Ge deposition anneal, which was also reported for Ge on bulk Si [2]. Threading dislocations annihilate during the post-epi anneal. FWHM values as low as 160 arc sec have been measured for 1.25 mm thick Ge layers independent of the underlying layer. This reflects the high material quality of the grown Ge. The difference in thermal expansion coefficient between Si and Ge results in some tensile stress in the annealed Ge layer, which explains the well-known shift in XRD peak position. The improvement in material quality by using a post-epi anneal is also reflected in the carrier lifetime as extracted from room-temperature photoluminescence measurements. The carrier lifetime increases from <0.2 ns (as-grown layers) to 3.3 ns and 3.6 ns for Ge on porous Si and bulk Si, respectively. The TDD, as extracted from ECCI measurements, was identical for both parts of the Si wafer (2-4e7 cm-2) and close to the values expected from literature. The material properties listed above are not affected by the thickness of the closed Si layer in-between the Ge and the porous Si.In conclusion, we developed a fabrication scheme for strain-relaxed Ge grown on SoN (or on macroporous Si) starting from conventional Si substrates. The material properties of the virtual Ge substrate are identical to those obtained for Ge grown on bulk Si. The virtual substrate serves as starting material for layer transfer and 3D device stacking technologies. The fabrication scheme can be extended to (defect free) bulk Ge for which the fabrication of Ge on nothing followed by layer transfer has been demonstrated [3].

Fabrication and Characterization of a Thin-Body Poly-Si 1T DRAM With Charge-Trap Effect

A polycrystalline silicon (poly-Si) capacitorless one-transistor dynamic random-access memory (1T DRAM) has been successfully fabricated and characterized. The proposed 1T DRAM is based on the metal-oxide-semiconductor field-effect transistor with heavily-doped ${n}^{+}$ source and drain junctions, nearly intrinsic ${n}^{-}$ channel, 500-nm gate length ( ${L}_{{{\mathrm {G}}}}$ ), and 50-nm poly-Si body thickness ( ${T}_{{{\mathrm {body}}}}$ ). The floating-body for storing charges was schemed in the silicon-on-insulator (SOI)-like environment which was simply realized by deposited buried oxide and poly-Si layers for the high cost-effectiveness. The program and erase operations are performed by band-to-band tunneling and drift-diffusion mechanisms, respectively, and the retention is assisted by the grain boundaries capable of charge trapping, not solely depending on recombination in Si. The proposed cell achieved an initial sensing margin of $3.2~{\mu }\text{A}/{\mu }\text{m}$ and a long retention time of 1.2 s. The thin-body poly-Si 1T DRAM with full Si processing compatibility has the strong candidacy for the embedded DRAM in the advanced integrated systems.

Large Scale Self-Organization of 2D Hexagonal Ge and Au Nanodots on Patterned TiO2 for Optoelectronic Applications

We report a new strategy for the ordering of 2D arrays of Ge and Au nanodots on a silicon wafer using a patterned titanium oxide layer. In a rst step, a TiO 2 layer is prepared by block-copolymer-micelles-assisted sol-gel deposition on a full Si wafer, followed by a thermal annealing. The process leads to hexagonally positioned perforations of homogeneous size and spacing. In a second step, these TiO 2 Inorganic NanoPatterns (INPs) are used as templates for the organization of Ge and Au nanodots. Germanium adatoms deposited by Molecular Beam Epitaxy on INPs, diuse and self-assemble into nanodots, located within the INPs pores. They form homogeneous sub-20 nm Ge nanodots in epitaxy on the silicon substrate and regularly distributed with one dot per perforation. The same approach is used for the formation of Au nanodots. In this case, a gentle mechanical polishing is requiered to suppress the dots seating at 1 the top of the TiO 2 network. The process developed in this study paves the way to the large scale self-organisation of quantum dots that are highly interesting for various applications, such as opto-electronics, and microelectronics.

Ni/GeOx/p+ Si resistive-switching random-access memory with full Si processing compatibility and its characterization and modeling

In this study, a fully Si-compatible resistive-switching random-access memory (ReRAM) employing GeOx as the switching layer is fabricated, analyzed, and characterized. I–V curves and endurance characteristics have been obtained from the measurement of fabricated GeOx ReRAM devices. From the measurement results, the size dependence of the operation voltages is investigated. Here, we have carefully prepared the methods for GeOx switching layer and its interfaces. Physical vapor deposition (PVD) by an evaporator and subsequent thermal oxidation are the key processes for the switching layer. Additional annealing was performed and its effects on device performances have been closely investigated. It was revealed from the measurement results that the forming voltage of the GeOx ReRAM cell was lower than set voltage. This merit of forming-freeness gets rid of the necessity of preparing an additional voltage scheme and relatively complicated peripheral circuit for generating the forming voltage which is the highest value among the operation voltages in most cases. The low-resistance state (LRS) and high-resistance state (HRS) current ratio is larger than 103 and the number of endurance cycles reaches 400 even under the harsh condition of DC sweep mode. At the end of this study, a DC compact model for the fabricated ReRAM cell is schemed intuitively by simple elements including variable resistors, capacitors, and switches. The components in the conceived model are allowed to have highly accurate values by figuring out the predominant conduction mechanism and comparing with the measurement results in the recursive manner. The systematic study embracing process architecture, device fabrication and characterization, and circuit modeling would be highly beneficial in the array and system level architecture design.

Wafer-Level Vacuum-Packaged Flexible and Bendable Micro Accelerometer

This paper presents a wafer-level vacuum-packaged z-axis capacitive micro accelerometer fabricated on a flexible polyimide substrate and encapsulated by another polyimide superstrate enabling the flexibility, bendability, and portability of both the device and the package. The novel low-cost and low-temperature encapsulation procedure requires a fewer fabrication steps than the processes, where a thin epitaxial Si layer or a full Si wafer with cavity is used as a superstrate. It also provides a better pliability. The fabricated micro accelerometers demonstrated excellent integrity when bowed down to 2-cm radius of curvature with the sensitivity varying between 139 and 174 fF/g, depending on the design, under the application of ±4 g of acceleration. The resonant frequencies varied from 800 Hz for the largest device to 1050 Hz for the smallest device. The results reported here represent the best performing, wafer-level-packaged flexible micro accelerometers to date.

Beta-spectrometer with Si-detectors for the study of 144Ce–144Pr decays

Here we present the specifications of a newly developed beta-spectrometer, based on full absorption Si(Li) detector and thin transmission detector, allowing one to perform efficient separation beta-radiation and accompanying X-rays and gamma radiation. Our method is based on registration of coincident events from both detectors. The spectrometer can be used for precision measurements of various beta-spectra, namely for the beta-spectrum shape study of 144Pr, which is considered to be an advantageous anti-neutrino source for sterile neutrino searches.

A Silicon Detector Based Beta-spectrometer

Here we present the specifications of the newly developed beta-spectrometer based on thick full absorption Si(Li) detector. The spectrometer was designed for precision measurements of various beta-spectra, namely for the beta-spectrum shape study of 144Pr, which is considered to be one of the most promising anti-neutrino source for sterile neutrino searches.

Current Sharing Behavior in Si IGBT and SiC MOSFET Cross-Switch Hybrid

The cross hybrid (XS) concept has been demonstrated experimentally with 3.3-kV Si Insulated Gate Bipolar Transistor (IGBTs) and SiC MOSFETs in parallel, and used to calibrate 2D Technology Computer Aided Design simulations. The XS hybrid offers lower switching losses compared with full Si IGBTs and reduced oscillations compared with full SiC MOSFETs. The current sharing mechanism between the IGBT and the MOSFET in the XS hybrid has been elucidated, showing that under typical switching conditions, the IGBT dissipate 98% of the XS hybrid turn-OFF losses compared with the SiC MOSFET. Since the current density of the IGBT in the XS hybrid is twice of that of the full IGBT solution, it exhibits higher dynamic avalanche. These features results in stress at device and package level, thereby compromising robustness and reliability. In order to overcome such issues, we show that increasing the turn-OFF gate resistance improves current sharing in the XS hybrid by delaying the turn-OFF of the MOSFET, and thereby suppressing dynamic avalanche in the IGBT.

Characterization of a Silicon IGBT and Silicon Carbide MOSFET Cross-Switch Hybrid

A parallel arrangement of a silicon (Si) IGBT and a silicon carbide (SiC) MOSFET is experimentally demonstrated. The concept referred to as the cross-switch (XS) hybrid aims to reach optimum power device performance by providing low static and dynamic losses while improving the overall electrical and thermal properties due to the combination of both the bipolar Si IGBT and unipolar SiC MOSFET characteristics. For the purpose of demonstrating the XS hybrid, the parallel configuration is implemented experimentally in a single package for devices rated at 1200 V. Test results are obtained to validate this approach with respect to the static and dynamic performance when compared to a full Si IGBT and a full SiC MOSFET reference devices having the same power ratings as for the XS hybrid samples.

New Stacked Die Interconnect Technology for High-Performance and Low-Cost FPGA

This article introduces the first comprehensive demonstration of new innovative technology comprising multiple key technologies for highly cost-effective and high-performance Xilinx field programmable gate array (FPGA), which is so-called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex®-7 2000T FPGA product with chip-to-wafer stacking, wafer-level flux cleaning, microbump underfilling, mold encapsulation, and backside silicon removal. Of all technology elements, both full silicon removal process with faster etching and no dielectric layer damage and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. To manage the wafer warpage after full Si removal, a couple of knobs are identified and used such as top reinforcement layer, microbump underfill properties tuning, die thickness, die-to-die space, and total thickness adjustments. It is also discussed in the article how the wafer warpage behaves and how the wafer warpage is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ∼ −40 μm at room temperature (25°C) for 25 mm × 31 mm in size and +20 μm ∼ +25 μm at reflow temperature (250°C). Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T flip-chip ball grid array (FC-BGA) package using through silicon via interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.

High-Efficiency Large-Area Screen-Printed Solar Cell on Epitaxial Thin Active Layer With Porous Si Back Reflector Using Standard Industrial Process

Large area 17.3% high-efficiency screen-printed solar cells on a 90-μm-thick epitaxial silicon (epi-Si) active layer with a porous silicon (PSI) back reflector were fabricated using a 182-cm 2 epitaxial wafer equivalent (EpiWE) structure and a standard industrial process. The PSI layer was studied and optimized to serve as an efficient back reflector in the finished device. An effective back surface recombination velocity (BSRV) and back internal reflectance (Rb) of 90 cm/s and 88%, respectively, were extracted by PC1D modeling of the EpiWE cell. These values of BSRV and Rb are superior to a standard industrial full Al-BSF Si solar cell, where BSRV and Rb are usually ≥200 cm/s and ~65%, respectively. Model calculations showed very little drop in cell efficiency if the thickness of active epi-Si layer is reduced to ~30 μm because of the good-light trapping provided by the optimized PSI back reflector.

Cost Effective and High Performance 28nm FPGA with New Disruptive Silicon-Less Interconnect Technology (SLIT)

This paper introduces the first comprehensive demonstration of new disruptive innovation technology comprising multiple Xilinx patent-pending innovations for highly cost effective and high performance Xilinx FPGA, which is so called stack silicon-less interconnect technology (SLIT) that provides the equivalent high-bandwidth connectivity and routing design-rule as stack silicon interconnect (SSI) technology at a cost-effective manner. We have successfully demonstrated the overall process integration and functions of our new SLIT-employed package using Virtex® -7 2000T FPGA product. Chip-to-Wafer stacking, wafer level flux cleaning, micro-bump underfilling, mold encapsulation are newly developed. Of all technology elements, both full silicon etching with high etch selectivity to dielectric/fast etch rate and wafer warpage management after full silicon etching are most crucial elements to realize the SLIT technology. In order to manage the wafer warpage after full Si removal, a couple of knobs are identified and employed such as top reinforcement layer, micro-bump underfill properties tuning, die thickness/die-to-die space/total thickness adjustments. It's also discussed in the paper how the wafer warpage behaves and how the wafer warpge is managed. New SLIT module shows excellent warpage characteristics of only −30 μm ~ −40 μm at room temperature for 25 mm × 31 mm in size and +20 μm ~ +25 μm at reflow temperature. Thermal simulation results shows that thermal resistance of new SLIT package is almost comparable to that of standard 2000T FCBGA package using TSV interposer with standard heat sink configuration and air wind condition. The reliability assessment is now under the study.

Laue scanner: A new method for determination of grain orientations and grain boundary types of multicrystalline silicon on a full wafer scale

The grain structure, especially the grain orientation, number and type of grain boundaries, influences many of the properties of multicrystalline (mc) silicon (Si) wafers used for manufacturing solar cells. In order to increase the efficiency of silicon solar cells, the relation between material defects, such as dislocations, impurities and precipitates, and the grain structure must be understood. Currently no measurement system exists that can determine the grain orientation on a full mc Si wafer with an area of 156×156mm2. The most widely used measuring method is electron backscatter diffraction (EBSD). However, it is only possible to measure small sample sizes by EBSD depending on the scanning electron microscopy stage, and moreover a time-consuming surface preparation is needed. In this paper an innovative fast characterization method is presented that allows the orientation measurement of as-cut and polished Si samples up to 380×400mm2. This method, known as the Laue scanner, is based on X-ray diffraction. Experimental and theoretical considerations, limits of the system and example results of possible tasks are shown and discussed.