Full Search Block Matching Motion Research Articles

Tracking of electroencephalography signals across brain lobes using motion estimation and cross-correlation

Electroencephalography (EEG) is the signal generated by electrical activity in the human brain. EEG topographic maps (topo-maps) give an idea of brain activation. Functional connectivity helps to find functionally integrated relationship between spatially separated brain regions. Brain connectivity can be measured by several methods. The classical methods calculate the coherence and correlation of the signal. We have developed an algorithm to map functional neural connectivity in the brain by using a full search block matching motion estimation algorithm. We have used oddball paradigm to examine the flow of activation across brain lobes for a specific activity. In the first step, the EEG signal is converted into topo-maps. The flow of activation between consecutive frames is tracked using full search block motion estimation, which appears in the form of motion vectors. In the second step, vector median filtering is used to obtain a smooth motion field by removing the unwanted noise. For each topo-map, several activation paths are tracked across various brain lobes. We have also developed correlation activity maps by following the correlation coefficient paths between electrodes. These paths are selected when the correlation coefficient between electrodes is >70% . We have compared the motion estimation path with the correlation coefficient activation maps. The tracked paths obtained by using motion estimation and correlation give very similar results. The inter-subject comparison shows that four out of five subjects tracked path involves all four (occipital, temporal, parietal, frontal) brain lobes for the same stimuli. The intra-subject analysis shows that three out of five subjects show different tracked lobes for different stimuli.

A Two-Step Methodology for Minimization of Computational Overhead on Full Search Block Motion Estimation

In Video coding, Motion Estimation(ME) is the major step to remove the temporal redundancy between adjacent frames. Several algorithms have been developed for acceleration of ME by reducing the number of computations. In this paper, we propose, twostep motion estimation technique to minimize the computational overhead of general full search block matching motion estimation algorithm. In our proposed methodology, we first find the matching block using the trace and upon match, the Sum of Absolute Difference (SAD) is calculated for the entire block in order to ensure the best match motion prediction. In trace matching, the number of computations observed are O(n) rather than O(n 2 )in case of full search. Hence, the two- step methodology reduces the computational overhead and also ensures compression quality comparable with the existing fast motion search techniques.

A hierarchical design methodology for full-search block matching motion estimation

Many useful DSP algorithms have high dimensions and complex logic. Consequently, an efficient implementation of these algorithms on parallel processor arrays must involve a structured design methodology. Full-search block-matching motion estimation is one of those algorithms that can be developed using parallel processor arrays. In this paper, we present a hierarchical design methodology for the full-search block matching motion estimation. Our proposed methodology reduces the complexity of the algorithm into simpler steps and then explores the different possible design options at each step. Input data timing restrictions are taken into consideration as well as buffering requirements. A designer is able to modify system performance by selecting some of the algorithm variables for pipelining or broadcasting. Our proposed design strategy also allows the designer to study time and hardware complexities of computations at each level of the hierarchy. The resultant architecture allows easy modifications to the organization of data buffers and processing elements-their number, datapath pipelining, and complexity-to produce a system whose performance matches the video data sample rate requirements.

Low-power systolic array processor architecture for FSBM video motion estimation

A novel power-efficient systolic array architecture is proposed for full search block matching (FSBM) motion estimation, where the partial distortion elimination algorithm is used to dynamically switch off the computation of eliminated partial candidate blocks. The RTL-level simulation shows that the proposed architecture can reduce the power consumption of the computation part of the algorithm to about 60% of that of the conventional 2D systolic arrays.

Motion estimation with low resolution distortion metric

Considering all possible candidate motion vectors in a given search area and calculating a distortion measure at every search position, as with the full-search block-matching motion estimation algorithm (FSBME), places a prohibitively high computational burden on the video encoder, making it unsuitable for real-time/portable video applications. To reduce computational complexity while maintaining accuracy, a new version of the reduced-bit, sum of absolute difference (RBSAD) algorithm is presented, which allows for optional correction to full resolution (FSBME) when appropriate. Analysis of a number of video sequence shows that this correction is required for blocks for which there is little motion between frames.

LOW POWER FULL SEARCH BLOCK MATCHING MOTION ESTIMATION VLSI ARCHITECTURES

Power consumption is very critical for portable video applications. During compression, the motion estimation unit consumes the largest portion of power since it performs a huge amount of computation. Different low power architectures for implementing the full-search block-matching (FSBM) motion estimation are discussed. Also, architectural enhancements to further reduce the power consumed during FSBM motion estimation without sacrificing throughput or optimality are presented. The proposed approach achieves these power savings by disabling portions of the architecture that perform unnecessary computations. A comparison between the different architectures including our enhancements and others is presented using simulation and analytical analysis. Different benchmarks are used to test and compare the discussed architectures. Analytical and simulation results show the effectiveness of the enhancements.

An efficient motion estimation method for MPEG-4 video encoder

The designer who wishes to develop an efficient video encoding systems for consumer devices such as digital video cameras and recorders must find an fast motion estimation method to reduce the huge computation complexity. Block-matching motion estimation (BMME) is an essential part of several video-coding standards. Full-search block-matching motion estimation is always used in reference software as a benchmark. Most of these fast algorithms sacrifice search quality by using only a subset of the search area in order to reduce the total number of searches. Moreover, most of the existing fast algorithms focus on a macro-block full-pel motion estimation. In MPEG-4, a new 8/spl times/8 block full-pel ME is introduced. This paper describes an efficient method for MPEG-4 ME algorithm. The proposed method can significantly reduce the total number of searches and computations without degrading the search quality.

A new computationally adaptive formulation of block-matching motion estimation

This paper presents a new computationally adaptive formulation of the full-search block-matching (FSBM) motion estimation. A key feature of our approach is to progressively adjust the number of computations required per block to the picture variation by applying a data-driven thresholding. Unlike the related methods, the proposed algorithm utilizes a simple threshold updating mechanism which neither requires a large hardware overhead to eliminate redundant search candidates, nor affects the performance of the motion estimation. Compared to the FSBM, it executes four times fewer operations whilst preserving the same quality of results. The algorithm implicitly features array implementation and can be easily realized in VLSI. A supportive hardware design is outlined.

A low-power VLSI architecture for full-search block-matching motion estimation

This paper presents an architectural enhancement to reduce the power consumption of the full-search block-matching (FSBM) motion estimation. Our approach is based on eliminating unnecessary computation using conservative approximation. Augmenting the estimation technique to a conventional systolic-architecture-based VLSI motion estimation reduces the power consumption by a factor of 2, while still preserving the optimal solution and the throughput. A register-transfer level implementation as well as simulation results on benchmark video clips are presented.

Cost Effective VLSI Architectures for Full-SearchBlock-Matching Motion Estimation Algorithm

In this paper, we present efficient VLSI architectures for full-search block-matching motion estimation (BMME) algorithm. Given a search range, we partition it into sub-search arrays called tiles. By fully exploiting data dependency within a tile, efficient VLSI architectures can be obtained. Using the proposed VLSI architectures, all the block-matchings in a tile can be processed in parallel. All the tiles within a search range can be processed serially or concurrently depending on various requirements. With the consideration of processing speed, hardware cost, and I/O bandwidth, the optimal tile size for a specific video application is analyzed. By partitioning a search range into tiles with appropriate size, flexible VLSI designs with different throughput can be obtained. In this way, cost effective VLSI designs for a wide range of video applications, from H.261 to HDTV, can be achieved.

Motion compensation for very low bit-rate video

A combination of spatial transformation and image segmentation is used to compensate for non-uniform intensity changes in moving scenes. The method efficiently tracks movements such that the motion vectors alone can be employed to represent a moving object with complex motion. Using fast transformation and interpolation algorithms, it is shown that while the compression efficiency of the presented method is far superior to that of the conventional full search block-matching motion estimation, its computational complexity is still affordable.

A novel modular systolic array architecture for full-search block matching motion estimation

A novel modular systolic array architecture for the full search block matching motion estimation algorithm (FBMA) is presented. The design efforts are focused on matching the array computation to system level input/output constraints. Compared to previously proposed FBMA architectures, this new architecture delivers highest throughput rate, achieves 100% processor utilization, requires much fewer input/output lines (pin count), and is linearly scalable. As such, this architecture offers a feasible solution for progressive-scan HDTV picture format. >

Motion estimation architecture for video compression

A VLSI architecture which implements the full search block matching motion estimation algorithm in real time is proposed. The architecture consists of a 2D structure of basic cells (BCs), where each BC is capable of computing the mean absolute error. The interblock dependency is exploited and hence the architecture can meet the real-time requirement in various applications. Most importantly, the architecture is simple, modular, and cascadable. This makes possible VLSI implementation as a codec.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>