Full Search Block Matching Algorithm Research Articles

Modified block-matching algorithm for moving object tracking in video surveillance

Video surveillance has risen as one of the most promising methods for people who live alone in their dwellings. Few video surveillance innovations have recently been introduced. However, due to various changes in illumination, abrupt shifts in target appearance, identical non-target artifacts in the background, and occlusions, developing a reliable video surveillance algorithm remains a difficult challenge. This work attempts to introduce a new framework for moving object detection and tracking by following four major phases: “Video-to-Frame Conversion, Pre-Processing, Background Subtraction, Feature-Based Multi-object Detection, Multi-object Tracking by Filtering”. Initially, in the Video-to-Frame Conversion process, the recorded input video clips are transformed into distinct frames. During pre-processing, the noise is removed from the video frame using a filtering approach, and thereby the nature of the images will be enhanced. In the proposed work, a Weiner filter is used to remove noise and other undesirable features during the pre-processing. Then, to distinguish the frontal areas of objects, background subtraction is performed using the neutrosophic set in noiseless video frames (pre-processed frames). The objects in the background-subtracted frames are separated using Improved Region Growing (IRG) segmentation model in the Feature-Based Multi-object Detection phase. The objects in the frames are determined from this segmented image. The Modified Full Search Algorithm is being used to track the object (motion estimation) on the video frame after it has been identified in the segmented phase. The Modified full search block matching algorithm (MFSA) is introduced in this research work to find the appropriate mobility. Promising results have been obtained by the proposed work, and also the mathematical excellence of the new method is also proven over other state-of-the-art models.

A Novel Improved Multi-Point Matching Based Coronary Disease Quantitative Analysis for Speckle Tracking in Ultrasound Image

Ultrasonic imaging technology is one of the most direct and effective methods, which can prevent, treat cardiovascular disease, and it can make noninvasive observation and detection of cardiac motion. To calculate accurate myocardial motion parameters more directly, effectively and accurately, speckle tracking algorithm is put forward. However, the performance of speckle tracking is directly related to the diagnosis effect of coronary disease. Compared with the speckle tracking algorithm based on optical flow algorithm, the speckle tracking algorithm based on block matching algorithm has advantages of higher tracking accuracy and faster computation speed and better anti-interference immunity. According to the requirements of clinical application, the full search block matching algorithm whose accuracy is the highest is adopted as the basic algorithm of the speckle tracking algorithm. In paper, In view of the shortcomings of the full search block matching algorithm, the algorithm based on calculating tracking error is proposed. The speckle tracking algorithm based on calculating tracking error has good tracking results, which shows that this algorithm can effectively improve the applicability, stability and accuracy of tracking in different ultrasound images and multi-point tracking in the same ultrasound images.

A speed FPGA hardware accelerator based FSBMA-VBSME used in H.264/AVC

Image and video processing applications represent major challenge concerning real-time embedded systems. In video coding, adjacent frames are similar; this correlation can be exploited to reduce the amount of data to be transmitted, in this case reducing temporal redundancies. Actually, H.264/AVC is the most popular standard; the high performance that offers magnifies the difficulty of a real-time implementation. This complexity is mainly related to the operation of the motion estimation and requires high computational power. This paper presents an efficient hardware implementation of integer motion estimation for H.264/AVC encoder. The considered methodology is based on full search block matching algorithm for its regular algorithm implementation. The proposed architecture enables variable block size motion estimation and computes 41 motion vectors values (MVs) resulted from each 16 × 16 bloc and its derived sub-blocks. The proposed architecture calculates the best MV using a parallel process composed of three processor modules and a set of comparators three values. Implementation results based on field-programmable gate arrays devices uses Xilinx Virtex7 XC7VX550T show performance characteristics like low latency reduced up to 80 %, high processing speed reaching 443 MHz of frequency. The processing capacity is up to 1920 × 1088 HD video streams with a search range of 48 × 48.

Tracking of electroencephalography signals across brain lobes using motion estimation and cross-correlation

Electroencephalography (EEG) is the signal generated by electrical activity in the human brain. EEG topographic maps (topo-maps) give an idea of brain activation. Functional connectivity helps to find functionally integrated relationship between spatially separated brain regions. Brain connectivity can be measured by several methods. The classical methods calculate the coherence and correlation of the signal. We have developed an algorithm to map functional neural connectivity in the brain by using a full search block matching motion estimation algorithm. We have used oddball paradigm to examine the flow of activation across brain lobes for a specific activity. In the first step, the EEG signal is converted into topo-maps. The flow of activation between consecutive frames is tracked using full search block motion estimation, which appears in the form of motion vectors. In the second step, vector median filtering is used to obtain a smooth motion field by removing the unwanted noise. For each topo-map, several activation paths are tracked across various brain lobes. We have also developed correlation activity maps by following the correlation coefficient paths between electrodes. These paths are selected when the correlation coefficient between electrodes is >70% . We have compared the motion estimation path with the correlation coefficient activation maps. The tracked paths obtained by using motion estimation and correlation give very similar results. The inter-subject comparison shows that four out of five subjects tracked path involves all four (occipital, temporal, parietal, frontal) brain lobes for the same stimuli. The intra-subject analysis shows that three out of five subjects show different tracked lobes for different stimuli.

Real-time hardware implementation of a speed FSBMA used in H.264/AVC

Nowadays, H.264/AVC reaches very high resolutions, flexible depending on the application, which particularly leads to a very large amount of data compression. The motion estimation defines the most-complex process and the most interesting at the same time; its complexity appears with a consumption of more than 60% of total encoding time which make it difficult to achieve real-time encoding required in many video applications, but the interesting part is the flexibility to make its implementation variant according to the application. For this purpose, the following paper presents a speed real-time hardware implementation of integer motion estimation used in H.264/AVC, the method is based on the full-search block-matching algorithm. The proposed architecture calculates best motion vector using a parallel process. It is composed of three processor modules and a comparator three values. Implementation results based on Field Programmable Gate Array devices uses Xilinx Virtex7 XC7VX550T show performance characteristics like low latency, high processing speed reaching 473 MHz of frequency. The processing capacity is up to 1080HD video streams with a search range of 48 × 48.

Conservative Approximation–Based Full-Search Block Matching Algorithm Architecture for QCIF Digital Video Employing Systolic Array Architecture

This paper presents a power-efficient hardware realization for a motion estimation technique that is based on the full-search block matching algorithm (FSBMA). The considered input is the quarter common intermediate format of digital video. The mean of absolute difference (MAD) is the distortion criteria employed for the block matching process. The conventional architecture considered for the hardware realization of FSBMA is that of the shift register-based 2-D systolic array. For this architecture, a conservative approximation technique is adapted to eliminate unnecessary MAD computations involved in the block matching process. Upon introducing the technique to the conventional architecture, the power and complexity of its implantation is reduced, while the accuracy of the motion vector extracted from the block matching process is preserved. The proposed architecture is verified for its functional specifications. A performance evaluation of the proposed architecture is carried out using parameters such as power, area, operating frequency, and efficiency.

English

Movement of hands or camera while capturing video leads to unstable video. To stabilize those unstable videos many approaches are proposed. Out of those, Digital Video Stabilization consists of Motion Estimation, Padding & Histogram Equalisation and Motion Compensation. In the block based method the frame is divided into 16*16 square block called Macroblock. Motion Estimation is the process of finding particular macroblock of previous frame into current frame. For this block matching criterion are used. This paper uses Sum of Absolute Difference (SAD). Block Matching Algorithms suggests where to apply this SAD in the macroblock. This paper uses Full Search or Exhaustive Block matching Algorithm (EBMA). Using this block matching algorithm, motion vectors are calculated. Padding is the process of keeping these motion vectors within certain range. Histogram equalisation of motion vectors try to uniform these motion vectors.In motion compensation macroblocks are adjusted according to motion vectors to obtain stabilized frame.

A Robust Template Matching Algorithm Based on Reducing Dimensions

Template matching is a fundamental problem in pattern recognition, which has wide applications, especially in industrial inspection. In this paper, we propose a 1-D template matching algorithm which is an alternative for 2-D full search block matching algorithms. Our approach consists of three steps. In the first step the images are converted from 2-D into 1-D by summing up the intensity values of the image in two directions horizontal and vertical. In the second step, the template matching is performed among 1-D vectors using the similarity function sum of square difference. Finally, the decision will be taken based on the value of similarity function. Transformation template image and sub-images in the source image from 2-D grey level information into 1-D information vector reduce the dimensionality of the data and accelerate the computations. Experimental results show that the computational time of the proposed approach is faster and performance is better than three basic template matching methods. Moreover, our approach is robust to detect the target object with changes of illumination in the template also when the Gaussian noise added to the source image.

A Two-Step Methodology for Minimization of Computational Overhead on Full Search Block Motion Estimation

In Video coding, Motion Estimation(ME) is the major step to remove the temporal redundancy between adjacent frames. Several algorithms have been developed for acceleration of ME by reducing the number of computations. In this paper, we propose, twostep motion estimation technique to minimize the computational overhead of general full search block matching motion estimation algorithm. In our proposed methodology, we first find the matching block using the trace and upon match, the Sum of Absolute Difference (SAD) is calculated for the entire block in order to ensure the best match motion prediction. In trace matching, the number of computations observed are O(n) rather than O(n 2 )in case of full search. Hence, the two- step methodology reduces the computational overhead and also ensures compression quality comparable with the existing fast motion search techniques.

A low-power VLSI implementation for fast full-search variable block size motion estimation

Variable block size motion estimation (VBSME) is becoming the new coding technique in H.264/AVC. This article presents a low-power VLSI implementation for VBSME, which employs a fast full-search block-matching algorithm to reduce power consumption, while preserving the optimal motion vectors (MVs). The fast full-search algorithm is based on the comparison of the current minimum sum of absolute difference (SAD) to a conservative lower bound so that unnecessary SAD calculations can be eliminated. We first experimentally determine the specific conservative lower bound of SAD and then implement the fast full-search algorithm in FPGA and 0.18 µm CMOS technology. To the best of our knowledge, this is the first time that a fast full-search block-matching algorithm is explored to reduce power consumption in the context of VBSME and implemented in hardware. Experiment results show that the proposed design can save power consumption by 45% compared to conventional VBSME designs that give optimal MV based on the full-search algorithms.

Systolic array based motion estimation architecture of 3D DWT sub band component for video processing

This paper describes Full Search Block Matching Algorithm (FSBMA) performed on 3D image in the transformed domain. An image of size N×N×8 is first transformed in to eight sub bands each of size N/2 × N/2 × 4 employing 3D Discrete Wavelet Transform (3D DWT). FSBMA performed on LLL sub band component which achieves good Peak Signal to Noise Ratio (PSNR), Compression Ratio (CR) and reduces computation complexity when compared with the original image. Modified lifting scheme based DWT and Systolic Array Architecture (SAA) based FSBMA are implemented on Field Programmable Gate Array (FPGA). 3D DWT implemented on FPGA operates at 230 MHz and consumes a power of 0.29 W, while FSBMA implemented on FPGA to reduce the computational time for motion estimation, operates at 120 MHz and consumes a power less than 0.34 W.

A Systolic Array for High-Speed Computing of Full Search Block Matching Algorithm

This paper proposes a high speed systolic array architecture for full search block matching algorithm (FBMA). The pixels of the search area for a reference block are input only one time to find the matched candidate block and reused to compute the sum of absolute difference (SAD) for the adjacent candidate blocks. Each row of designed 2-dimensional systolic array compares the reference block with the adjacent blocks of the same row in search area. The lower rows of the designed array get the pixels from the upper row and compute the SAD with reusing the overlapped pixels of the candidate blocks within same column of the search area. This designed array has no data broadcasting and global paths. The comparison with existing architectures shows that this array is superior in terms of throughput through it requires a little more hardware.

Expert system based parallel multi-1D block matching algorithm with implementation for motion estimation

In this paper, we propose an expert-system based parallel multi-1-dimensional block matching algorithm (ESPM-1D-BMA) for motion estimation (ME). Instead of the conventional 2D block matching, we employ the parallel multi-1D blocks matching to improve the computing speed. To improve the ME accuracy, we design a knowledge base and inference engine to determine the true motion vector (MV) from the results of parallel multi-1D blocks matching. To speed up the computing speed further, we present a hardware architecture for implementing the ESPM-1D-BMA. We have demonstrated that the MV estimation accuracy achieved by the proposed ESPM-1D-BMA is much better than the comparing fast block matching algorithms and is close to the 2 dimensional full search block matching algorithm (2D-FSBMA). We also demonstrate that the computing speed of the proposed ESPM-1D-BMA is about two times as fast as the mixed-signal 2D-FSBMA (MS-2D-FSBMA).

A Low Cost Architecture for Variable Block Size Motion Estimation

Variable block size motion estimation is adopted in MPEG-4 AVC/H.264. This paper presents a new VLSI and FPGA architecture using full search block matching algorithm and online arithmetic. Several ways for data refreshing are described. There is not any increment in the number of clock cycles to process all sub-block formats. Only 54K gates are used, allowing to implement this architecture in devices with low hardware requirements. Moreover, low power consumption is obtained. A qualitative analysis of other designs is reported. Early termination of SAD calculation is analysed. Real-time video processing can be achieved for HDTV using early termination or increasing the parallelism.

An efficient VLSI processor chip for variable block size integer motion estimation in H.264/AVC

Motion estimation (ME) is the most critical component of a video coding standard. H.264/AVC adopts the variable block size motion estimation (VBSME) to obtain excellent coding efficiency, but the high computational complexity makes design difficult. This paper presents an effective processor chip for integer motion estimation (IME) in H264/AVC based on the full-search block-matching algorithm (FSBMA). It uses architecture with a configurable 2D systolic array to obtain a high data reuse of search area. This systolic array supports a three-direction scan format in which only one row of pixels is changed between the two adjacent subblocks, thus reducing the memory accesses and saving clock cycles. A computing array of 64 PEs calculates the SAD of basic 4×4 subblocks and a modified Lagrangian cost is used as matching criterion to find the best 41 variable-size blocks by means of a tree pipeline parallel architecture. Finally, a mode decision module uses serial data flow to find the best mode by comparing the total minimum Lagrangian costs. The IME processor chip was designed in UMC 0.18 μm technology resulting in a circuit with only 32.3 k gates and 6 RAMs (total 59kBits on-chip memory). In typical working conditions (25 °C, 1.8 V), a clock frequency of 300 MHz can be estimated with a processing capacity for HDTV (1920×1088 @ 30 fps) and a search range of 32×32.

Real-time motion detection using block matching algorithms on multicore processors

Block matching algorithms (BMAs) like sum of absolute difference (SAD) and normalised cross correlation (NCC) form the basic building block in many computer vision applications. Full search (FS) BMAs take into account every pixel in a block, and are therefore very effective for wide motion search using different blocks. However, FS is computationally very expensive and unsuitable for real-time applications. We present efficient strategies for extracting data parallelism in FS SAD and NCC algorithms with fine-grained optimisation techniques for fully exploiting the computational capacity of the NVIDIA's multicore graphic processing units (GPUs). We demonstrate that proposed parallel implementation achieves a speedup of around 34× for SAD and 59× for NCC on GPU GTX 280, compared to sequential implementation on dual socket quad core Xeon processor with 2.50 GHz and 16 GB DRAM. Since GPUs are quite cheap and popular, our algorithm can form the base for many real-time video systems.

Activity-Based Motion Estimation Scheme for H.264 Scalable Video Coding

This paper proposes a motion estimation scheme to reduce the computational complexity of multilayer motion estimation for scalable video coding. Based on the result of the motion estimation of the lower resolution layer referred to as base layer, we developed a new approach for exploring the search range of the enhancement layer with high coding efficiency. This approach is based on the activity defined as the absolute difference between the motion vector predictor and the final motion vector. Based on the correlation of the activities between neighboring layers, an inter-layer activity model was developed using a curve-fitted linear equation to exploit the activity in the base layer for deciding the search center and the search range of the enhancement layer. Each activity pair in the neighboring layers is used to associate the relevant macroblock to one of two groups; boundary region and interior region. The base-layer motion vector predictor is basically selected over all the activity regions; for each activity region, the proposed motion estimation algorithm decides whether to include the median motion vector predictor or not. Minimal sufficient search range is also decided from the inter-layer activity prediction factor that is adjusted to the given sequence. The proposed scheme reduced the execution time of motion estimation by 99.26% at the cost of 1.56% bit-rate increase and 0.048 dB peak signal-to-noise ratio (PSNR) decrease on average compared with the conventional full-search algorithm. The fast full-search block matching algorithm can also be incorporated to obtain the extra CPU time reduction in the motion estimation process. By adopting the fast full-search block matching algorithm (FFSBMA) in JSVM reference software, the CPU time was reduced by up to 91.84% and the memory bandwidth was reduced by 90% at the sacrifice of 1.27% bit-rate increase and 0.041 dB PSNR decrease on average compared with the FFSBMA only.

A Content-Motion-Aware Motion Estimation for Quality-Stationary Video Coding

The block-matching motion estimation has been aggressively developed for years. Many papers have presented fast block-matching algorithms (FBMAs) for the reduction of computation complexity. Nevertheless, their results, in terms of video quality and bitrate, are rather content-varying. Very few FBMAs can result in stationary or quasistationary video quality for different motion types of video content. Instead of using multiple search algorithms, this paper proposes a quality-stationary motion estimation with a unified search mechanism. This paper presents a content-motion-aware motion estimation for quality-stationary video coding. Under the rate control mechanism, the proposed motion estimation, based on subsample approach, adaptively adjusts the subsample ratio with the motion-level of video sequence to keep the degradation of video quality low. The proposed approach is a companion for all kinds of FBMAs in H.264/AVC. As shown in experimental results, the proposed approach can produce stationary quality. Comparing with the full-search block-matching algorithm, the quality degradation is less than 0.36 dB while the average saving of power consumption is 69.6%. When applying the proposed approach for the fast motion estimation (FME) algorithm in H.264/AVC JM reference software, the proposed approach can save 62.2% of the power consumption while the quality degradation is less than 0.27 dB.

Motion-Compensated Frame Rate Up-Conversion—Part I: Fast Multi-Frame Motion Estimation

Motion-compensated frame rate up-conversion is used to convert video/film materials of low frame rates to a higher frame rate so that the materials can be displayed with smooth motion and high-perceived quality. It consists of two key elements: motion estimation and motion-compensated frame interpolation. It requires accurate motion trajectories to ensure quality results and low computational cost to ensure practical applications. This paper presents a novel motion estimation algorithm that combines the accuracy of maximum a posteriori probability (MAP) estimation with the speed of hierarchical block-matching algorithm (BMA). This MAP estimation uses three consecutive pictures, instead of the conventional two, and one previously estimated motion field to exploit the temporal correlation between motion fields and to determine motion in occluded areas. The optimization of the MAP estimation is performed using full-search and implemented by means of look-up tables. The full search ensures that the optimization converges to the global minimum, while the look-up tables dramatically reduce the computational cost. Experimental results show that the proposed algorithm provides motion trajectories that are much more accurate than those obtained using either the full-search BMA or hierarchical BMA alone. Also, it is much faster than the full-search BMA.

An FFT-Based Full-Search Block Matching Algorithm with Sum of Squared Differences Criterion

An FFT-based full-search block matching algorithm (BMA) is described that uses the sum of squared differences (SSD) criterion. The proposed method does not have to extend a real signal into complex one. This reduces the computational load of FFT approaches. In addition, if two macroblocks share the same search window, they can be matched at the same time. In a simulation of motion estimation, the proposed method achieved the same performance as a direct SSD full search and its processing speed is faster than other FFT-based BMAs.